void __init_or_cpufreq s3c2443_setup_clocks(void) { unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON); unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0); struct clk *xtal_clk; unsigned long xtal; unsigned long pll; unsigned long fclk; unsigned long hclk; unsigned long pclk; xtal_clk = clk_get(NULL, "xtal"); xtal = clk_get_rate(xtal_clk); clk_put(xtal_clk); pll = s3c2443_get_mpll(mpllcon, xtal); clk_msysclk.rate = pll; fclk = pll / s3c2443_fclk_div(clkdiv0); hclk = s3c2443_prediv_getrate(&clk_prediv); hclk /= s3c2443_get_hdiv(clkdiv0); pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1); s3c24xx_setup_clocks(fclk, hclk, pclk); printk("S3C2443: mpll %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n", (mpllcon & S3C2443_PLLCON_OFF) ? "off":"on", print_mhz(pll), print_mhz(fclk), print_mhz(hclk), print_mhz(pclk)); s3c24xx_setup_clocks(fclk, hclk, pclk); }
void __init s3c2410_init_clocks(int xtal) { unsigned long tmp; unsigned long fclk; unsigned long hclk; unsigned long pclk; /* now we've got our machine bits initialised, work out what * clocks we've got */ fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal); tmp = __raw_readl(S3C2410_CLKDIVN); /* work out clock scalings */ hclk = fclk / ((tmp & S3C2410_CLKDIVN_HDIVN) ? 2 : 1); pclk = hclk / ((tmp & S3C2410_CLKDIVN_PDIVN) ? 2 : 1); /* print brieft summary of clocks, etc */ printk("S3C2410: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n", print_mhz(fclk), print_mhz(hclk), print_mhz(pclk)); /* initialise the clocks here, to allow other things like the * console to use them */ s3c24xx_setup_clocks(xtal, fclk, hclk, pclk); s3c2410_baseclk_add(); }
void __init_or_cpufreq s3c2412_setup_clocks(void) { struct clk *xtal_clk; unsigned long tmp; unsigned long xtal; unsigned long fclk; unsigned long hclk; unsigned long pclk; xtal_clk = clk_get(NULL, "xtal"); xtal = clk_get_rate(xtal_clk); clk_put(xtal_clk); /* now we've got our machine bits initialised, work out what * clocks we've got */ fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal * 2); clk_mpll.rate = fclk; tmp = __raw_readl(S3C2410_CLKDIVN); /* work out clock scalings */ hclk = fclk / ((tmp & S3C2412_CLKDIVN_HDIVN_MASK) + 1); hclk /= ((tmp & S3C2412_CLKDIVN_ARMDIVN) ? 2 : 1); pclk = hclk / ((tmp & S3C2412_CLKDIVN_PDIVN) ? 2 : 1); /* print brieft summary of clocks, etc */ printk("S3C2412: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n", print_mhz(fclk), print_mhz(hclk), print_mhz(pclk)); s3c24xx_setup_clocks(fclk, hclk, pclk); }
void __init_or_cpufreq s3c2412_setup_clocks(void) { struct clk *xtal_clk; unsigned long tmp; unsigned long xtal; unsigned long fclk; unsigned long hclk; unsigned long pclk; xtal_clk = clk_get(NULL, "xtal"); xtal = clk_get_rate(xtal_clk); clk_put(xtal_clk); fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal * 2); clk_mpll.rate = fclk; tmp = __raw_readl(S3C2410_CLKDIVN); hclk = fclk / ((tmp & S3C2412_CLKDIVN_HDIVN_MASK) + 1); hclk /= ((tmp & S3C2412_CLKDIVN_ARMDIVN) ? 2 : 1); pclk = hclk / ((tmp & S3C2412_CLKDIVN_PDIVN) ? 2 : 1); printk("S3C2412: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n", print_mhz(fclk), print_mhz(hclk), print_mhz(pclk)); s3c24xx_setup_clocks(fclk, hclk, pclk); }
void __init s3c2412_init_clocks(int xtal) { unsigned long clkdiv; unsigned long hclk, fclk, pclk; int hdiv = 1; /* now we've got our machine bits initialised, work out what * clocks we've got */ fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal); clkdiv = __raw_readl(S3C2410_CLKDIVN); /* work out clock scalings */ switch (clkdiv & S3C2412_CLKDIVN_HCLKDIV_MASK) { case S3C2412_CLKDIVN_HCLKDIV_1_2: hdiv = 1; break; case S3C2412_CLKDIVN_HCLKDIV_2_4: hdiv = 2; break; case S3C2412_CLKDIVN_HCLKDIV_3_6: hdiv = 3; break; case S3C2412_CLKDIVN_HCLKDIV_4_8: hdiv = 4; break; } if (!(clkdiv & S3C2412_CLKDIVN_ARMDIV)) fclk *= 2; hclk = fclk / hdiv; pclk = hclk / ((clkdiv & S3C2412_CLKDIVN_PCLKDIV)? 2 : 1); if (clkdiv & S3C2412_CLKDIVN_DVSEN) fclk = hclk; /* print brief summary of clocks, etc */ printk("S3C2412: core %lu.%03lu MHz, memory %lu.%03lu MHz, peripheral %lu.%03lu MHz\n", print_mhz(fclk), print_mhz(hclk), print_mhz(pclk)); /* initialise the clocks here, to allow other things like the * console to use them, and to add new ones after the initialisation */ s3c24xx_setup_clocks(xtal, fclk, hclk, pclk); #if defined CONFIG_CPU_FREQ && defined CONFIG_S3C24XX_DFS_CPUFREQ /* Setup the uartclk. Needs to be done this early so the console can use it. */ s3c2412_setup_uart_clk( xtal ); #endif }
void __init s3c244x_init_clocks(int xtal) { unsigned long clkdiv; unsigned long camdiv; unsigned long hclk, fclk, pclk; int hdiv = 1; /* now we've got our machine bits initialised, work out what * clocks we've got */ fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2; clkdiv = __raw_readl(S3C2410_CLKDIVN); camdiv = __raw_readl(S3C2440_CAMDIVN); /* work out clock scalings */ switch (clkdiv & S3C2440_CLKDIVN_HDIVN_MASK) { case S3C2440_CLKDIVN_HDIVN_1: hdiv = 1; break; case S3C2440_CLKDIVN_HDIVN_2: hdiv = 2; break; case S3C2440_CLKDIVN_HDIVN_4_8: hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4; break; case S3C2440_CLKDIVN_HDIVN_3_6: hdiv = (camdiv & S3C2440_CAMDIVN_HCLK3_HALF) ? 6 : 3; break; } hclk = fclk / hdiv; pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN)? 2:1); /* print brief summary of clocks, etc */ printk("S3C244X: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n", print_mhz(fclk), print_mhz(hclk), print_mhz(pclk)); /* initialise the clocks here, to allow other things like the * console to use them, and to add new ones after the initialisation */ s3c24xx_setup_clocks(xtal, fclk, hclk, pclk); s3c2410_baseclk_add(); }
void __init_or_cpufreq s3c244x_setup_clocks(void) { struct clk *xtal_clk; unsigned long clkdiv; unsigned long camdiv; unsigned long xtal; unsigned long hclk, fclk, pclk; int hdiv = 1; xtal_clk = clk_get(NULL, "xtal"); xtal = clk_get_rate(xtal_clk); clk_put(xtal_clk); fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2; clkdiv = __raw_readl(S3C2410_CLKDIVN); camdiv = __raw_readl(S3C2440_CAMDIVN); /* work out clock scalings */ switch (clkdiv & S3C2440_CLKDIVN_HDIVN_MASK) { case S3C2440_CLKDIVN_HDIVN_1: hdiv = 1; break; case S3C2440_CLKDIVN_HDIVN_2: hdiv = 2; break; case S3C2440_CLKDIVN_HDIVN_4_8: hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4; break; case S3C2440_CLKDIVN_HDIVN_3_6: hdiv = (camdiv & S3C2440_CAMDIVN_HCLK3_HALF) ? 6 : 3; break; } hclk = fclk / hdiv; pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN) ? 2 : 1); /* print brief summary of clocks, etc */ printk("S3C244X: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n", print_mhz(fclk), print_mhz(hclk), print_mhz(pclk)); s3c24xx_setup_clocks(fclk, hclk, pclk); }
void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll, fdiv_fn get_fdiv) { unsigned long epllcon = __raw_readl(S3C2443_EPLLCON); unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON); unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0); struct clk *xtal_clk; unsigned long xtal; unsigned long pll; unsigned long fclk; unsigned long hclk; unsigned long pclk; int ptr; xtal_clk = clk_get(NULL, "xtal"); xtal = clk_get_rate(xtal_clk); clk_put(xtal_clk); pll = get_mpll(mpllcon, xtal); clk_msysclk.clk.rate = pll; fclk = pll / get_fdiv(clkdiv0); hclk = s3c2443_prediv_getrate(&clk_prediv); hclk /= s3c2443_get_hdiv(clkdiv0); pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1); s3c24xx_setup_clocks(fclk, hclk, pclk); printk("CPU: MPLL %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n", (mpllcon & S3C2443_PLLCON_OFF) ? "off":"on", print_mhz(pll), print_mhz(fclk), print_mhz(hclk), print_mhz(pclk)); for (ptr = 0; ptr < ARRAY_SIZE(clksrc_clks); ptr++) s3c_set_clksrc(&clksrc_clks[ptr], true); /* ensure usb bus clock is within correct rate of 48MHz */ if (clk_get_rate(&clk_usb_bus_host.clk) != (48 * 1000 * 1000)) { printk(KERN_INFO "Warning: USB host bus not at 48MHz\n"); clk_set_rate(&clk_usb_bus_host.clk, 48*1000*1000); } printk("CPU: EPLL %s %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n", (epllcon & S3C2443_PLLCON_OFF) ? "off":"on", print_mhz(clk_get_rate(&clk_epll)), print_mhz(clk_get_rate(&clk_usb_bus))); }
void __init s3c2443_init_clocks(int xtal) { unsigned long epllcon = __raw_readl(S3C2443_EPLLCON); unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON); unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0); unsigned long pll; unsigned long fclk; unsigned long hclk; unsigned long pclk; struct clk *clkp; int ret; int ptr; /* s3c2443 parents h and p clocks from prediv */ clk_h.parent = &clk_prediv; clk_p.parent = &clk_prediv; pll = s3c2443_get_mpll(mpllcon, xtal); clk_msysclk.rate = pll; fclk = pll / s3c2443_fclk_div(clkdiv0); hclk = s3c2443_prediv_getrate(&clk_prediv); hclk /= s3c2443_get_hdiv(clkdiv0); pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1); s3c24xx_setup_clocks(xtal, fclk, hclk, pclk); printk("S3C2443: mpll %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n", (mpllcon & S3C2443_PLLCON_OFF) ? "off":"on", print_mhz(pll), print_mhz(fclk), print_mhz(hclk), print_mhz(pclk)); s3c2443_clk_initparents(); for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) { clkp = clks[ptr]; ret = s3c24xx_register_clock(clkp); if (ret < 0) { printk(KERN_ERR "Failed to register clock %s (%d)\n", clkp->name, ret); } } clk_epll.rate = s3c2443_get_epll(epllcon, xtal); clk_usb_bus.parent = &clk_usb_bus_host; /* ensure usb bus clock is within correct rate of 48MHz */ if (clk_get_rate(&clk_usb_bus_host) != (48 * 1000 * 1000)) { printk(KERN_INFO "Warning: USB host bus not at 48MHz\n"); clk_set_rate(&clk_usb_bus_host, 48*1000*1000); } printk("S3C2443: epll %s %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n", (epllcon & S3C2443_PLLCON_OFF) ? "off":"on", print_mhz(clk_get_rate(&clk_epll)), print_mhz(clk_get_rate(&clk_usb_bus))); /* register clocks from clock array */ clkp = init_clocks; for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) { ret = s3c24xx_register_clock(clkp); if (ret < 0) { printk(KERN_ERR "Failed to register clock %s (%d)\n", clkp->name, ret); } } /* We must be careful disabling the clocks we are not intending to * be using at boot time, as subsystems such as the LCD which do * their own DMA requests to the bus can cause the system to lockup * if they where in the middle of requesting bus access. * * Disabling the LCD clock if the LCD is active is very dangerous, * and therefore the bootloader should be careful to not enable * the LCD clock if it is not needed. */ /* install (and disable) the clocks we do not need immediately */ clkp = init_clocks_disable; for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { ret = s3c24xx_register_clock(clkp); if (ret < 0) { printk(KERN_ERR "Failed to register clock %s (%d)\n", clkp->name, ret); } (clkp->enable)(clkp, 0); } }