int s3c_gpio_setcfg_s5pc11x(struct s3c_gpio_chip *chip, unsigned int off, unsigned int cfg) { void __iomem *reg = chip->base; unsigned int shift = (off & 7) * 4; u32 con; if (s3c_gpio_is_cfg_special(cfg)) { cfg &= 0xf; cfg <<= shift; } #if CONFIG_ARIES_VER_B1 //UART_CHANGE if((cfg&0xfffffff0) == 0) { cfg &= 0xf; cfg <<= shift; } #endif con = __raw_readl(reg); con &= ~(0xf << shift); con |= cfg; __raw_writel(con, reg); #ifdef S5PC11X_ALIVEGPIO_STORE con = __raw_readl(reg); #endif return 0; }
int s3c_gpio_setcfg_s3c24xx_banka(struct s3c_gpio_chip *chip, unsigned int off, unsigned int cfg) { void __iomem *reg = chip->base; unsigned int shift = off; u32 con; if (s3c_gpio_is_cfg_special(cfg)) { cfg &= 0xf; /* Map output to 0, and SFN2 to 1 */ cfg -= 1; if (cfg > 1) return -EINVAL; cfg <<= shift; } con = __raw_readl(reg); con &= ~(0x1 << shift); con |= cfg; __raw_writel(con, reg); return 0; }
int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip, unsigned int off, unsigned int cfg) { void __iomem *reg = chip->base; unsigned int shift = (off & 7) * 4; u32 con; if (off < 8 && chip->chip.ngpio > 8) reg -= 4; if (s3c_gpio_is_cfg_special(cfg)) { cfg &= 0xf; cfg <<= shift; } #if defined CONFIG_S5PV210_VICTORY //UART_CHANGE if((cfg&0xfffffff0) == 0) { cfg &= 0xf; cfg <<= shift; } #endif con = __raw_readl(reg); con &= ~(0xf << shift); con |= cfg; __raw_writel(con, reg); return 0; }
int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip, unsigned int off, unsigned int cfg) { void __iomem *reg = chip->base; unsigned int shift = off * 2; u32 con; if (s3c_gpio_is_cfg_special(cfg)) { cfg &= 0xf; if (cfg > 3) return -EINVAL; cfg <<= shift; } #if defined CONFIG_S5PV210_VICTORY //UART_CHANGE if((cfg&0xfffffff0) == 0) { cfg &= 0xf; cfg <<= shift; } #endif con = __raw_readl(reg); con &= ~(0x3 << shift); con |= cfg; __raw_writel(con, reg); return 0; }
int s3c_gpio_setcfg_s5p64xx(struct s3c_gpio_chip *chip, unsigned int off, unsigned int cfg) { void __iomem *reg = chip->base; unsigned int shift = (off & 7) * 4; u32 con; if (s3c_gpio_is_cfg_special(cfg)) { cfg &= 0xf; cfg <<= shift; } con = __raw_readl(reg); con &= ~(0xf << shift); con |= cfg; __raw_writel(con, reg); return 0; }
int s3c_gpio_int_flt_s5pc1xx(struct s3c_gpio_chip *chip, unsigned int off, unsigned int cfg) { void __iomem *reg = chip->base; unsigned int shift = (off & 7) * 4; u32 con; if (s3c_gpio_is_cfg_special(cfg)) { cfg &= 0xf; cfg <<= shift; } reg=reg+0x848; con = 0x8000; __raw_writel(con, reg); return 0; }
int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip, unsigned int off, unsigned int cfg) { void __iomem *reg = chip->base; unsigned int shift = off * 2; u32 con; if (s3c_gpio_is_cfg_special(cfg)) { cfg &= 0xf; if (cfg > 3) return -EINVAL; cfg <<= shift; } con = __raw_readl(reg); con &= ~(0x3 << shift); con |= cfg; __raw_writel(con, reg); return 0; }
int s5p64x0_gpio_setcfg_4bit_rbank(struct s3c_gpio_chip *chip, unsigned int off, unsigned int cfg) { void __iomem *reg = chip->base; unsigned int shift; u32 con; switch (off) { case 0: case 1: case 2: case 3: case 4: case 5: shift = (off & 7) * 4; reg -= 4; break; case 6: shift = ((off + 1) & 7) * 4; reg -= 4; default: shift = ((off + 1) & 7) * 4; break; } if (s3c_gpio_is_cfg_special(cfg)) { cfg &= 0xf; cfg <<= shift; } con = __raw_readl(reg); con &= ~(0xf << shift); con |= cfg; __raw_writel(con, reg); return 0; }