コード例 #1
0
ファイル: irq.c プロジェクト: Asure/Dropad-kernel-2.6.35.7
void __init s5p_init_irq(u32 *vic, u32 num_vic)
{
	struct irq_chip *chip;
	int irq;

	/* initialize the VICs */
	for (irq = 0; irq < num_vic; irq++)
		vic_init(VA_VIC(irq), VIC_BASE(irq), vic[irq], 0);

	s3c_init_vic_timer_irq(IRQ_TIMER0_VIC, IRQ_TIMER0);
	s3c_init_vic_timer_irq(IRQ_TIMER1_VIC, IRQ_TIMER1);
	s3c_init_vic_timer_irq(IRQ_TIMER2_VIC, IRQ_TIMER2);
	s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3);
	s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4);

	s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs));

#ifdef CONFIG_PM
	/* Register wakeup source. */
	for (irq = 0; irq < ARRAY_SIZE(wakeup_source); irq++) {
		chip = get_irq_chip(wakeup_source[irq]);
		chip->set_wake = s3c_irq_wake;
	}
#endif
}
コード例 #2
0
void __init s5p_init_irq(u32 *vic, u32 num_vic)
{
	int irq;

	/* initialize the VICs */
	for (irq = 0; irq < num_vic; irq++)
		vic_init(VA_VIC(irq), VIC_BASE(irq), vic[irq], 0);

	s3c_init_vic_timer_irq(IRQ_TIMER0_VIC, IRQ_TIMER0);
	s3c_init_vic_timer_irq(IRQ_TIMER1_VIC, IRQ_TIMER1);
	s3c_init_vic_timer_irq(IRQ_TIMER2_VIC, IRQ_TIMER2);
	s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3);
	s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4);

	s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs));
}
コード例 #3
0
ファイル: irq.c プロジェクト: 0709oNEY/at100-kernel
void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
{
	printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);

	/* initialise the pair of VICs */
	vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, 0);
	vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, 0);

	/* add the timer sub-irqs */

	s3c_init_vic_timer_irq(IRQ_TIMER0_VIC, IRQ_TIMER0);
	s3c_init_vic_timer_irq(IRQ_TIMER1_VIC, IRQ_TIMER1);
	s3c_init_vic_timer_irq(IRQ_TIMER2_VIC, IRQ_TIMER2);
	s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3);
	s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4);

	s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs));
}
コード例 #4
0
void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
{
	printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);

	/* initialise the pair of VICs */
	vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME);
	vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME);

	/* add the timer sub-irqs */
	s3c_init_vic_timer_irq(5, IRQ_TIMER0);
}
コード例 #5
0
void __init s5p_init_irq(u32 *vic, u32 num_vic)
{
#ifdef CONFIG_ARM_VIC
	int irq;

	/* initialize the VICs */
	for (irq = 0; irq < num_vic; irq++)
		vic_init(VA_VIC(irq), VIC_BASE(irq), vic[irq], 0);
#endif

	s3c_init_vic_timer_irq(5, IRQ_TIMER0);
}
コード例 #6
0
void __init s5p_init_irq(u32 *vic, u32 num_vic)
{
	struct irq_chip *chip;
	int irq;

#ifdef CONFIG_ARM_VIC
	/* initialize the VICs */
	for (irq = 0; irq < num_vic; irq++)
		vic_init(VA_VIC(irq), VIC_BASE(irq), vic[irq], 0);
#endif

	s3c_init_vic_timer_irq(5, IRQ_TIMER0);

	s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs));

	/* Register wakeup source. */
	for (irq = 0; irq < ARRAY_SIZE(wakeup_source); irq++) {
		chip = irq_get_chip(wakeup_source[irq]);
		chip->irq_set_wake = s3c_irq_wake;
	}
}