static void __init graphicsmaster_init_irq(void) { int irq; /* First the standard SA1100 IRQs */ sa1100_init_irq(); /* disable all IRQs */ ADS_INT_EN1 = 0; ADS_INT_EN2 = 0; /* clear all IRQs */ ADS_INT_ST1 = 0xff; ADS_INT_ST2 = 0xff; for (irq = ADS_EXT_IRQ(0); irq <= ADS_EXT_IRQ(7); irq++) { irq_desc[irq].valid = 1; irq_desc[irq].probe_ok = 1; irq_desc[irq].mask_ack = ADS_mask_and_ack_irq0; irq_desc[irq].mask = ADS_mask_irq0; irq_desc[irq].unmask = ADS_unmask_irq0; } for (irq = ADS_EXT_IRQ(8); irq <= ADS_EXT_IRQ(15); irq++) { irq_desc[irq].valid = 1; irq_desc[irq].probe_ok = 1; irq_desc[irq].mask_ack = ADS_mask_and_ack_irq1; irq_desc[irq].mask = ADS_mask_irq1; irq_desc[irq].unmask = ADS_unmask_irq1; } set_GPIO_IRQ_edge(GPIO_GPIO0, GPIO_FALLING_EDGE); setup_arm_irq( IRQ_GPIO0, &ADS_ext_irq ); }
static void __init graphicsmaster_init_irq(void) { int irq; /* First the standard SA1100 IRQs */ sa1100_init_irq(); /* disable all IRQs */ ADS_INT_EN1 = 0; ADS_INT_EN2 = 0; /* clear all IRQs */ ADS_INT_ST1 = 0xff; ADS_INT_ST2 = 0xff; for (irq = IRQ_GRAPHICSMASTER_START; irq < IRQ_GRAPHICSMASTER_UCB1200; irq++) { irq_desc[irq].valid = 1; irq_desc[irq].probe_ok = 1; irq_desc[irq].mask_ack = ADS_mask_and_ack_irq0; irq_desc[irq].mask = ADS_mask_irq0; irq_desc[irq].unmask = ADS_unmask_irq0; } for (irq = IRQ_GRAPHICSMASTER_UCB1200; irq < IRQ_GRAPHICSMASTER_END; irq++) { irq_desc[irq].valid = 1; irq_desc[irq].probe_ok = 1; irq_desc[irq].mask_ack = ADS_mask_and_ack_irq1; irq_desc[irq].mask = ADS_mask_irq1; irq_desc[irq].unmask = ADS_unmask_irq1; } GPDR &= ~GPIO_GPIO0; set_GPIO_IRQ_edge(GPIO_GPIO0, GPIO_FALLING_EDGE); setup_arm_irq( IRQ_GPIO0, &ADS_ext_irq ); }
static void __init h3800_init_irq(void) { int i; /* Initialize standard IRQs */ sa1100_init_irq(); /* Disable all IRQs and set up clock */ H3800_ASIC2_KPIINTSTAT = 0; /* Disable all interrupts */ H3800_ASIC2_GPIINTSTAT = 0; H3800_ASIC2_KPIINTCLR = 0; /* Clear all KPIO interrupts */ H3800_ASIC2_GPIINTCLR = 0; /* Clear all GPIO interrupts */ // H3800_ASIC2_KPIINTCLR = 0xffff; /* Clear all KPIO interrupts */ // H3800_ASIC2_GPIINTCLR = 0xffff; /* Clear all GPIO interrupts */ H3800_ASIC2_CLOCK_Enable |= ASIC2_CLOCK_EX0; /* 32 kHZ crystal on */ H3800_ASIC2_INTR_ClockPrescale |= ASIC2_INTCPS_SET; H3800_ASIC2_INTR_ClockPrescale = ASIC2_INTCPS_CPS(0x0e) | ASIC2_INTCPS_SET; H3800_ASIC2_INTR_TimerSet = 1; #if 0 for (i = 0; i < H3800_KPIO_IRQ_COUNT; i++) { int irq = i + H3800_KPIO_IRQ_START; irq_desc[irq].valid = 1; irq_desc[irq].probe_ok = 1; set_irq_chip(irq, &h3800_kpio_irqchip); } for (i = 0; i < H3800_GPIO_IRQ_COUNT; i++) { int irq = i + H3800_GPIO_IRQ_START; irq_desc[irq].valid = 1; irq_desc[irq].probe_ok = 1; set_irq_chip(irq, &h3800_gpio_irqchip); } #endif set_irq_type(IRQ_GPIO_H3800_ASIC, IRQT_RISING); set_irq_chained_handler(IRQ_GPIO_H3800_ASIC, h3800_IRQ_demux); }
static void __init adsbitsy_init_irq(void) { /* First the standard SA1100 IRQs */ sa1100_init_irq(); }
static void __init cerf_init_irq(void) { sa1100_init_irq(); set_irq_type(CERF_ETH_IRQ, IRQ_TYPE_EDGE_RISING); }