void sb1250_time_init(void) { int cpu = smp_processor_id(); int irq = K_INT_TIMER_0+cpu; /* Only have 4 general purpose timers */ if (cpu > 3) { BUG(); } if (!cpu) { /* Use our own gettimeoffset() routine */ do_gettimeoffset = sb1250_gettimeoffset; } sb1250_mask_irq(cpu, irq); /* Map the timer interrupt to ip[4] of this cpu */ bus_writeq(IMR_IP4_VAL, IOADDR(A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) + (irq << 3))); /* the general purpose timer ticks at 1 Mhz independent if the rest of the system */ /* Disable the timer and set up the count */ bus_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); #ifdef CONFIG_SIMULATION bus_writeq(50000 / HZ, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT))); #else bus_writeq(1000000/HZ, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT))); #endif /* Set the timer running */ bus_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); sb1250_unmask_irq(cpu, irq); sb1250_steal_irq(irq); /* * This interrupt is "special" in that it doesn't use the request_irq * way to hook the irq line. The timer interrupt is initialized early * enough to make this a major pain, and it's also firing enough to * warrant a bit of special case code. sb1250_timer_interrupt is * called directly from irq_handler.S when IP[4] is set during an * interrupt */ }
void __init arch_init_irq(void) { unsigned int i; u64 tmp; unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 | STATUSF_IP1 | STATUSF_IP0; /* Default everything to IP2 */ for (i = 0; i < SB1250_NR_IRQS; i++) { /* was I0 */ __raw_writeq(IMR_IP2_VAL, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + (i << 3))); __raw_writeq(IMR_IP2_VAL, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) + (i << 3))); } init_sb1250_irqs(); /* * Map the high 16 bits of the mailbox registers to IP[3], for * inter-cpu messages */ /* Was I1 */ __raw_writeq(IMR_IP3_VAL, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + (K_INT_MBOX_0 << 3))); __raw_writeq(IMR_IP3_VAL, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) + (K_INT_MBOX_0 << 3))); /* Clear the mailboxes. The firmware may leave them dirty */ __raw_writeq(0xffffffffffffffffULL, IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU))); __raw_writeq(0xffffffffffffffffULL, IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU))); /* Mask everything except the mailbox registers for both cpus */ tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0); __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK))); __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK))); sb1250_steal_irq(K_INT_MBOX_0); /* * Note that the timer interrupts are also mapped, but this is * done in sb1250_time_init(). Also, the profiling driver * does its own management of IP7. */ #ifdef CONFIG_KGDB imask |= STATUSF_IP6; #endif /* Enable necessary IPs, disable the rest */ change_c0_status(ST0_IM, imask); #ifdef CONFIG_KGDB if (kgdb_flag) { kgdb_irq = K_INT_UART_0 + kgdb_port; #ifdef CONFIG_SIBYTE_SB1250_DUART sb1250_duart_present[kgdb_port] = 0; #endif /* Setup uart 1 settings, mapper */ __raw_writeq(M_DUART_IMR_BRK, IOADDR(A_DUART_IMRREG(kgdb_port))); sb1250_steal_irq(kgdb_irq); __raw_writeq(IMR_IP6_VAL, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + (kgdb_irq << 3))); sb1250_unmask_irq(0, kgdb_irq); } #endif }