static void c101_set_iface(port_t *port) { u8 rxs = port->rxs & CLK_BRG_MASK; u8 txs = port->txs & CLK_BRG_MASK; switch(port->settings.clock_type) { case CLOCK_INT: rxs |= CLK_BRG_RX; /* TX clock */ txs |= CLK_RXCLK_TX; /* BRG output */ break; case CLOCK_TXINT: rxs |= CLK_LINE_RX; /* RXC input */ txs |= CLK_BRG_TX; /* BRG output */ break; case CLOCK_TXFROMRX: rxs |= CLK_LINE_RX; /* RXC input */ txs |= CLK_RXCLK_TX; /* RX clock */ break; default: /* EXTernal clock */ rxs |= CLK_LINE_RX; /* RXC input */ txs |= CLK_LINE_TX; /* TXC input */ } port->rxs = rxs; port->txs = txs; sca_out(rxs, MSCI1_OFFSET + RXS, port); sca_out(txs, MSCI1_OFFSET + TXS, port); sca_set_port(port); }
static void pc300_set_iface(port_t *port) { card_t *card = port->card; u32 __iomem * init_ctrl = &card->plxbase->init_ctrl; u16 msci = get_msci(port); u8 rxs = port->rxs & CLK_BRG_MASK; u8 txs = port->txs & CLK_BRG_MASK; sca_out(EXS_TES1, (port->chan ? MSCI1_OFFSET : MSCI0_OFFSET) + EXS, port->card); switch(port->settings.clock_type) { case CLOCK_INT: rxs |= CLK_BRG; /* BRG output */ txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */ break; case CLOCK_TXINT: rxs |= CLK_LINE; /* RXC input */ txs |= CLK_PIN_OUT | CLK_BRG; /* BRG output */ break; case CLOCK_TXFROMRX: rxs |= CLK_LINE; /* RXC input */ txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */ break; default: /* EXTernal clock */ rxs |= CLK_LINE; /* RXC input */ txs |= CLK_PIN_OUT | CLK_LINE; /* TXC input */ break; } port->rxs = rxs; port->txs = txs; sca_out(rxs, msci + RXS, card); sca_out(txs, msci + TXS, card); sca_set_port(port); if (port->card->type == PC300_RSV) { if (port->iface == IF_IFACE_V35) writel(card->init_ctrl_value | PC300_CHMEDIA_MASK(port->chan), init_ctrl); else writel(card->init_ctrl_value & ~PC300_CHMEDIA_MASK(port->chan), init_ctrl); } }
static void n2_set_iface(port_t *port) { card_t *card = port->card; int io = card->io; u8 mcr = inb(io + N2_MCR); u8 msci = get_msci(port); u8 rxs = port->rxs & CLK_BRG_MASK; u8 txs = port->txs & CLK_BRG_MASK; switch(port->settings.clock_type) { case CLOCK_INT: mcr |= port->phy_node ? CLOCK_OUT_PORT1 : CLOCK_OUT_PORT0; rxs |= CLK_BRG_RX; /* BRG output */ txs |= CLK_RXCLK_TX; /* RX clock */ break; case CLOCK_TXINT: mcr |= port->phy_node ? CLOCK_OUT_PORT1 : CLOCK_OUT_PORT0; rxs |= CLK_LINE_RX; /* RXC input */ txs |= CLK_BRG_TX; /* BRG output */ break; case CLOCK_TXFROMRX: mcr |= port->phy_node ? CLOCK_OUT_PORT1 : CLOCK_OUT_PORT0; rxs |= CLK_LINE_RX; /* RXC input */ txs |= CLK_RXCLK_TX; /* RX clock */ break; default: /* Clock EXTernal */ mcr &= port->phy_node ? ~CLOCK_OUT_PORT1 : ~CLOCK_OUT_PORT0; rxs |= CLK_LINE_RX; /* RXC input */ txs |= CLK_LINE_TX; /* TXC input */ } outb(mcr, io + N2_MCR); port->rxs = rxs; port->txs = txs; sca_out(rxs, msci + RXS, card); sca_out(txs, msci + TXS, card); sca_set_port(port); }
static void pci200_set_iface(port_t *port) { card_t *card = port->card; u16 msci = get_msci(port); u8 rxs = port->rxs & CLK_BRG_MASK; u8 txs = port->txs & CLK_BRG_MASK; sca_out(EXS_TES1, (port->chan ? MSCI1_OFFSET : MSCI0_OFFSET) + EXS, port->card); switch(port->settings.clock_type) { case CLOCK_INT: rxs |= CLK_BRG; /* BRG output */ txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */ break; case CLOCK_TXINT: rxs |= CLK_LINE; /* RXC input */ txs |= CLK_PIN_OUT | CLK_BRG; /* BRG output */ break; case CLOCK_TXFROMRX: rxs |= CLK_LINE; /* RXC input */ txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */ break; default: /* EXTernal clock */ rxs |= CLK_LINE; /* RXC input */ txs |= CLK_PIN_OUT | CLK_LINE; /* TXC input */ break; } port->rxs = rxs; port->txs = txs; sca_out(rxs, msci + RXS, card); sca_out(txs, msci + TXS, card); sca_set_port(port); }