static void sdhci_iproc_writeb(struct sdhci_host *host, u8 val, int reg) { u32 oldval = sdhci_iproc_readl(host, (reg & ~3)); u32 byte_shift = REG_OFFSET_IN_BITS(reg); u32 mask = 0xff << byte_shift; u32 newval = (oldval & ~mask) | (val << byte_shift); sdhci_iproc_writel(host, newval, reg & ~3); }
/* * The Arasan has a bugette whereby it may lose the content of successive * writes to the same register that are within two SD-card clock cycles of * each other (a clock domain crossing problem). The data * register does not have this problem, which is just as well - otherwise we'd * have to nobble the DMA engine too. * * This wouldn't be a problem with the code except that we can only write the * controller with 32-bit writes. So two different 16-bit registers are * written back to back creates the problem. * * In reality, this only happens when SDHCI_BLOCK_SIZE and SDHCI_BLOCK_COUNT * are written followed by SDHCI_TRANSFER_MODE and SDHCI_COMMAND. * The BLOCK_SIZE and BLOCK_COUNT are meaningless until a command issued so * the work around can be further optimized. We can keep shadow values of * BLOCK_SIZE, BLOCK_COUNT, and TRANSFER_MODE until a COMMAND is issued. * Then, write the BLOCK_SIZE+BLOCK_COUNT in a single 32-bit write followed * by the TRANSFER+COMMAND in another 32-bit write. */ static void sdhci_iproc_writew(struct sdhci_host *host, u16 val, int reg) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_iproc_host *iproc_host = sdhci_pltfm_priv(pltfm_host); u32 word_shift = REG_OFFSET_IN_BITS(reg); u32 mask = 0xffff << word_shift; u32 oldval, newval; if (reg == SDHCI_COMMAND) { /* Write the block now as we are issuing a command */ if (iproc_host->is_blk_shadowed) { sdhci_iproc_writel(host, iproc_host->shadow_blk, SDHCI_BLOCK_SIZE); iproc_host->is_blk_shadowed = false; } oldval = iproc_host->shadow_cmd; iproc_host->is_cmd_shadowed = false; } else if ((reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) && iproc_host->is_blk_shadowed) { /* Block size and count are stored in shadow reg */ oldval = iproc_host->shadow_blk; } else { /* Read reg, all other registers are not shadowed */ oldval = sdhci_iproc_readl(host, (reg & ~3)); } newval = (oldval & ~mask) | (val << word_shift); if (reg == SDHCI_TRANSFER_MODE) { /* Save the transfer mode until the command is issued */ iproc_host->shadow_cmd = newval; iproc_host->is_cmd_shadowed = true; } else if (reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) { /* Save the block info until the command is issued */ iproc_host->shadow_blk = newval; iproc_host->is_blk_shadowed = true; } else { /* Command or other regular 32-bit write */ sdhci_iproc_writel(host, newval, reg & ~3); } }