static void sdramc_init(void) { struct sdramc_register sdramc_config; unsigned int reg; sdramc_config.cr = AT91C_SDRAMC_NC_9 | AT91C_SDRAMC_NR_13 | AT91C_SDRAMC_CAS_2 | AT91C_SDRAMC_NB_4_BANKS | AT91C_SDRAMC_DBW_32_BITS | AT91C_SDRAMC_TWR_2 | AT91C_SDRAMC_TRC_7 | AT91C_SDRAMC_TRP_2 | AT91C_SDRAMC_TRCD_2 | AT91C_SDRAMC_TRAS_5 | AT91C_SDRAMC_TXSR_8; sdramc_config.tr = (MASTER_CLOCK * 7) / 1000000; sdramc_config.mdr = AT91C_SDRAMC_MD_SDRAM; sdramc_hw_init(); /* Initialize the matrix (memory voltage = 3.3) */ reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA); reg |= AT91C_EBI_CS1A_SDRAMC; writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA); sdramc_initialize(&sdramc_config, AT91C_BASE_CS1); }
static void sdramc0_init(void) { unsigned int reg; struct sdramc_register sdramc_config; #ifdef CONFIG_SDRAM_16BIT sdramc_config.cr = AT91C_SDRAMC_NC_10 | AT91C_SDRAMC_NR_13 | AT91C_SDRAMC_CAS_2 | AT91C_SDRAMC_NB_4_BANKS | AT91C_SDRAMC_DBW_16_BITS | AT91C_SDRAMC_TWR_2 | AT91C_SDRAMC_TRC_7 | AT91C_SDRAMC_TRP_2 | AT91C_SDRAMC_TRCD_2 | AT91C_SDRAMC_TRAS_5 | AT91C_SDRAMC_TXSR_8; #else sdramc_config.cr = AT91C_SDRAMC_NC_9 | AT91C_SDRAMC_NR_13 | AT91C_SDRAMC_CAS_2 | AT91C_SDRAMC_NB_4_BANKS | AT91C_SDRAMC_DBW_32_BITS | AT91C_SDRAMC_TWR_2 | AT91C_SDRAMC_TRC_7 | AT91C_SDRAMC_TRP_2 | AT91C_SDRAMC_TRCD_2 | AT91C_SDRAMC_TRAS_5 | AT91C_SDRAMC_TXSR_8; #endif /* #ifdef CONFIG_SDRAM_16BIT */ sdramc_config.tr = (MASTER_CLOCK * 7) / 1000000; sdramc_config.mdr = AT91C_SDRAMC_MD_SDRAM; sdramc_hw_init(); reg = readl(AT91C_BASE_CCFG + CCFG_EBI0CSA); reg |= AT91C_VDDIOM_SEL_33V; reg |= AT91C_EBI_CS1A_SDRAMC; writel(reg, AT91C_BASE_CCFG + CCFG_EBI0CSA); sdramc_initialize(&sdramc_config, AT91C_BASE_EBI0_CS1); }
//*---------------------------------------------------------------------------- //* \fn sdram_init //* \brief Initialize the SDRAM Controller //*---------------------------------------------------------------------------- int sdram_init(unsigned int sdramc_cr, unsigned int sdramc_tr, unsigned char low_power) { volatile unsigned int i; /* Performs the hardware initialization */ sdramc_hw_init(); /* CFG Control Register */ write_sdramc(SDRAMC_CR, sdramc_cr); /* Set MDR Register */ write_sdramc(SDRAMC_MDR, (low_power & 0x01)); for (i =0; i< 1000;i++); write_sdramc(SDRAMC_MR, AT91C_SDRAMC_MODE_NOP_CMD); // Set NOP writel(0x00000000, AT91C_SDRAM); // Perform NOP write_sdramc(SDRAMC_MR, AT91C_SDRAMC_MODE_PRCGALL_CMD); // Set PRCHG AL writel(0x00000000, AT91C_SDRAM); // Perform PRCHG for (i =0; i< 10000;i++); write_sdramc(SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 1st CBR writel(0x00000001, AT91C_SDRAM+4); // Perform CBR write_sdramc(SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 2 CBR writel(0x00000002, AT91C_SDRAM+8); // Perform CBR write_sdramc(SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 3 CBR writel(0x00000003, AT91C_SDRAM+0xc); // Perform CBR write_sdramc(SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 4 CBR writel(0x00000004, AT91C_SDRAM+0x10); // Perform CBR write_sdramc(SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 5 CBR writel(0x00000005, AT91C_SDRAM+0x14); // Perform CBR write_sdramc(SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 6 CBR writel(0x00000006, AT91C_SDRAM+0x18); // Perform CBR write_sdramc(SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 7 CBR writel(0x00000007, AT91C_SDRAM+0x1C); // Perform CBR write_sdramc(SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 8 CBR writel(0x00000008, AT91C_SDRAM+0x20); // Perform CBR write_sdramc(SDRAMC_MR, AT91C_SDRAMC_MODE_LMR_CMD); // Set LMR operation writel(0xcafedede, AT91C_SDRAM+0x24); // Perform LMR burst=1, lat=2 write_sdramc(SDRAMC_TR, sdramc_tr); // Set Refresh Timer write_sdramc(SDRAMC_MR, AT91C_SDRAMC_MODE_NORMAL_CMD); // Set Normal mode writel(0x00000000, AT91C_SDRAM); // Perform Normal mode return 0; }
static void sdramc_init(void) { struct sdramc_register sdramc_config; sdramc_config.cr = AT91C_SDRAMC_NC_9 | AT91C_SDRAMC_NR_13 | AT91C_SDRAMC_CAS_3 | AT91C_SDRAMC_NB_4_BANKS | AT91C_SDRAMC_DBW_32_BITS | AT91C_SDRAMC_TWR_3 | AT91C_SDRAMC_TRC_9 | AT91C_SDRAMC_TRP_3 | AT91C_SDRAMC_TRCD_3 | AT91C_SDRAMC_TRAS_6 | AT91C_SDRAMC_TXSR_10; sdramc_config.tr = (MASTER_CLOCK * 7) / 1000000; sdramc_config.mdr = AT91C_SDRAMC_MD_SDRAM; sdramc_hw_init(); /* Initialize the matrix (memory voltage = 3.3) */ writel((readl(AT91C_BASE_CCFG + CCFG_EBICSA)) | AT91C_EBI_CS1A_SDRAMC | AT91C_VDDIOM_SEL_33V | (0x01 << 17), /* set I/O slew selection */ AT91C_BASE_CCFG + CCFG_EBICSA); sdramc_initialize(&sdramc_config, AT91C_BASE_CS1); }