inline void MOESI_protocol::do_cache_I (Mreq *request)
{
switch (request->msg)
{
// If we get a request from the processor we need to get the data
case LOAD:
/* Line up the GETS in the Bus' queue */
send_GETS(request->addr);
/* The IS state means that we have sent the GET message and we are now waiting
* on DATA
*/
state = MOESI_CACHE_IS;
/* This is a cache Miss */
Sim->cache_misses++;
break;
case STORE:
/* Line up the GETM in the Bus' queue */
send_GETM(request->addr);
/* The IM state means that we have sent the GET message and we are now waiting
* on DATA
*/
state = MOESI_CACHE_IM;
/* This is a cache Miss */
Sim->cache_misses++;
break;
default:
request->print_msg (my_table->moduleID, "ERROR");
fatal_error ("Client: I state shouldn't see this message\n");
}
}
inline void MOESIF_protocol::do_cache_I (Mreq *request)
{
switch (request->msg) {
/* In I, we simply initiate the transition to either S or M
*/
case LOAD:
send_GETS(request->addr);
state = MOESIF_CACHE_IS;
/* This is a cache miss */
Sim->cache_misses++;
break;
case STORE:
/* Line up the GETM in the Bus' queue */
send_GETM(request->addr);
/* The IM state means that we have sent the GET message and we are now waiting
* on DATA
*/
state = MOESIF_CACHE_IM;
/* This is a cache miss */
Sim->cache_misses++;
break;
default:
request->print_msg (my_table->moduleID, "ERROR");
fatal_error ("Client: I state shouldn't see this message\n");
}
}
inline void MSI_protocol::do_cache_I (Mreq *request){
switch (request->msg) {
case LOAD:
send_GETS(request->addr);
state = MSI_CACHE_IS;
Sim->cache_misses++; //ACTUAL CACHE MISSES
break;
case STORE:
send_GETM(request->addr);
state = MSI_CACHE_IM;
Sim->cache_misses++; //ACTUAL CACHE MISSES
break;
default:
request->print_msg (my_table->moduleID, "ERROR");
fatal_error ("Client: I state shouldn't see this message\n");
}
}
inline void MESI_protocol::do_cache_I (Mreq *request)
{
switch(request->msg) {
case LOAD:
// Go to the intermediate state, it's a miss
send_GETS(request->addr);
state = MESI_CACHE_IS;
Sim->cache_misses++;
break;
case STORE:
// Go to the intermediate state, it's a miss
send_GETM(request->addr);
state = MESI_CACHE_IM;
Sim->cache_misses++;
break;
default:
request->print_msg (my_table->moduleID, "ERROR");
fatal_error ("Client: CacheI state shouldn't see this message\n");
}
}
inline void MOESI_protocol::do_cache_I (Mreq *request)
{
switch (request->msg) {
case LOAD:
//this will lead to a cache miss
//get the data first from the memory with the intent to share
send_GETS(request->addr);
state = MOESI_CACHE_IS_Intermediate;
Sim->cache_misses++;
break;
case STORE:
//this will lead to a cache miss
//get the data first from the memory with the intent to modify
send_GETM(request->addr);
state = MOESI_CACHE_IM_Intermediate;
Sim->cache_misses++;
break;
default:
request->print_msg (my_table->moduleID, "ERROR");
fatal_error ("Client: I state shouldn't see this message\n");
}
}
inline void TYPE(_protocol)::do_cache_I (Mreq *request)
{
switch (request->msg) {
/*
No datas
*/
case LOAD:
send_GETS(request->addr);
state = TYPE(_CACHE_IE);
/* This is a cache miss */
Sim->cache_misses++;
break;
case STORE:
send_GETM(request->addr);
state = TYPE(_CACHE_IM);
/* This is a cache miss */
Sim->cache_misses++;
break;
default:
request->print_msg (my_table->moduleID, "ERROR");
fatal_error ("Client: I state shouldn't see this message\n");
}
}
