/**
* sendData
*
* Send data packet via RF
*
* 'packet' Packet to be transmitted
*
* Return:
* True if the transmission succeeds
* False otherwise
*/
boolean CC1101::sendData(CCPACKET packet)
{
// Enter RX state
setRxState();
// Check that the RX state has been entered
while (readStatusReg(CC1101_MARCSTATE) != 0x0D)
delay(1);
delayMicroseconds(500);
// Set data length at the first position of the TX FIFO
writeReg(CC1101_TXFIFO, packet.length);
// Write data into the TX FIFO
writeBurstReg(CC1101_TXFIFO, packet.data, packet.length);
// CCA enabled: will enter TX state only if the channel is clear
cmdStrobe(CC1101_STX);
// Check that TX state is being entered (state = RXTX_SETTLING)
if(readStatusReg(CC1101_MARCSTATE) != 0x15)
return false;
// Wait for the sync word to be transmitted
wait_GDO0_high();
// Wait until the end of the packet transmission
wait_GDO0_low();
// Flush TX FIFO. Don't uncomment
// cmdStrobe(CC1101_SFTX);
// Enter back into RX state
setRxState();
// Check that the TX FIFO is empty
if((readStatusReg(CC1101_TXBYTES) & 0x7F) == 0)
return true;
return false;
}
/**
* receiveData
*
* Read data packet from RX FIFO
*
* 'packet' Container for the packet received
*
* Return:
* Amount of bytes received
*/
byte CC1101::receiveData(CCPACKET * packet)
{
byte val;
byte rxBytes = readStatusReg(CC1101_RXBYTES);
// Any byte waiting to be read and no overflow?
if (rxBytes & 0x7F && !(rxBytes & 0x80))
{
// Read data length
packet->length = readConfigReg(CC1101_RXFIFO);
// If packet is too long
if (packet->length > CC1101_DATA_LEN)
packet->length = 0; // Discard packet
else
{
// Read data packet
readBurstReg(packet->data, CC1101_RXFIFO, packet->length);
// Read RSSI
packet->rssi = readConfigReg(CC1101_RXFIFO);
// Read LQI and CRC_OK
val = readConfigReg(CC1101_RXFIFO);
packet->lqi = val & 0x7F;
packet->crc_ok = bitRead(val, 7);
}
}
else
packet->length = 0;
setIdleState(); // Enter IDLE state
flushRxFifo(); // Flush Rx FIFO
//cmdStrobe(CC1101_SCAL);
// Back to RX state
setRxState();
return packet->length;
}
/**
* receiveData
*
* Read data packet from RX FIFO
*
* Return:
* Amount fo bytes received
* 'packet' Container for the packet received
*/
byte CC1101::receiveData(CCPACKET * packet)
{
byte val;
// Any byte waiting to be read?
if (readStatusReg(CC1101_RXBYTES) & 0x7F)
{
// Read data length
packet->length = readConfigReg(CC1101_RXFIFO);
// If packewt is too long
if (packet->length > CC1101_DATA_LEN)
packet->length = 0; // Discard packet
else
{
// Read data packet
readBurstReg(packet->data, CC1101_RXFIFO, packet->length);
// Read RSSI
packet->rssi = readConfigReg(CC1101_RXFIFO);
// Read LQI and CRC_OK
val = readConfigReg(CC1101_RXFIFO);
packet->lqi = val & 0x7F;
packet->crc_ok = bitRead(val, 7);
}
}
else
packet->length = 0;
// Flush RX FIFO. Don't uncomment
//cmdStrobe(CC1101_SFRX);
// Enter back into RX state
setRxState();
return packet->length;
}
/**
* sendData
*
* Send data packet via RF
*
* 'packet' Packet to be transmitted. First byte is the destination address
*
* Return:
* True if the transmission succeeds
* False otherwise
*/
boolean CC1101::sendData(CCPACKET packet)
{
byte marcState;
bool res = false;
// Declare to be in Tx state. This will avoid receiving packets whilst
// transmitting
rfState = RFSTATE_TX;
// Enter RX state
setRxState();
// Check that the RX state has been entered
while (((marcState = readStatusReg(CC1101_MARCSTATE)) & 0x1F) != 0x0D)
{
if (marcState == 0x11) // RX_OVERFLOW
flushRxFifo(); // flush receive queue
}
delayMicroseconds(500);
// Set data length at the first position of the TX FIFO
writeReg(CC1101_TXFIFO, packet.length);
// Write data into the TX FIFO
writeBurstReg(CC1101_TXFIFO, packet.data, packet.length);
// CCA enabled: will enter TX state only if the channel is clear
setTxState();
// Check that TX state is being entered (state = RXTX_SETTLING)
marcState = readStatusReg(CC1101_MARCSTATE) & 0x1F;
if((marcState != 0x13) && (marcState != 0x14) && (marcState != 0x15))
{
setIdleState(); // Enter IDLE state
flushTxFifo(); // Flush Tx FIFO
setRxState(); // Back to RX state
// Declare to be in Rx state
rfState = RFSTATE_RX;
return false;
}
// Wait for the sync word to be transmitted
wait_GDO0_high();
// Wait until the end of the packet transmission
wait_GDO0_low();
// Check that the TX FIFO is empty
if((readStatusReg(CC1101_TXBYTES) & 0x7F) == 0)
res = true;
setIdleState(); // Enter IDLE state
flushTxFifo(); // Flush Tx FIFO
// Enter back into RX state
setRxState();
// Declare to be in Rx state
rfState = RFSTATE_RX;
return res;
}
