void tms5501_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
{
switch (id)
{
case TIMER_1:
set_interrupt(IRQ_TMR1);
break;
case TIMER_2:
set_interrupt(IRQ_TMR2);
break;
case TIMER_3:
set_interrupt(IRQ_TMR3);
break;
case TIMER_4:
set_interrupt(IRQ_TMR4);
break;
case TIMER_5:
if (!(m_cmd & CMD_XI7))
{
set_interrupt(IRQ_TMR5);
}
break;
default:
break;
}
}
void ESP_DMA_CTRL_Write(void) {
Log_Printf(LOG_ESPDMA_LEVEL,"ESP DMA control write at $%08x val=$%02x PC=$%08x\n", IoAccessCurrentAddress, IoMem[IoAccessCurrentAddress & IO_SEG_MASK], m68k_getpc());
esp_dma.control = IoMem[IoAccessCurrentAddress & IO_SEG_MASK];
if (esp_dma.control&ESPCTRL_FLUSH) {
Log_Printf(LOG_ESPDMA_LEVEL, "flush DMA buffer\n");
if (ConfigureParams.System.bTurbo) {
tdma_flush_buffer(0);
} else {
dma_esp_flush_buffer();
}
}
if (esp_dma.control&ESPCTRL_CHIP_TYPE) {
Log_Printf(LOG_ESPDMA_LEVEL, "SCSI controller is WD33C92\n");
} else {
Log_Printf(LOG_ESPDMA_LEVEL, "SCSI controller is NCR53C90\n");
}
if (esp_dma.control&ESPCTRL_RESET) {
Log_Printf(LOG_ESPDMA_LEVEL, "reset SCSI controller\n");
esp_reset_hard();
}
if (esp_dma.control&ESPCTRL_DMA_READ) {
Log_Printf(LOG_ESPDMA_LEVEL, "DMA from SCSI to mem\n");
} else {
Log_Printf(LOG_ESPDMA_LEVEL, "DMA from mem to SCSI\n");
}
if (esp_dma.control&ESPCTRL_MODE_DMA) {
Log_Printf(LOG_ESPDMA_LEVEL, "mode DMA\n");
} else {
Log_Printf(LOG_ESPDMA_LEVEL, "mode PIO\n");
}
if (esp_dma.control&ESPCTRL_ENABLE_INT) {
Log_Printf(LOG_ESPDMA_LEVEL, "Enable ESP interrupt");
if (status&STAT_INT) {
set_interrupt(INT_SCSI, SET_INT);
}
} else {
Log_Printf(LOG_ESPDMA_LEVEL, "Block ESP interrupt");
set_interrupt(INT_SCSI, RELEASE_INT);
}
switch (esp_dma.control&ESPCTRL_CLKMASK) {
case ESPCTRL_CLK10MHz:
Log_Printf(LOG_ESPDMA_LEVEL, "10 MHz clock\n");
break;
case ESPCTRL_CLK12MHz:
Log_Printf(LOG_ESPDMA_LEVEL, "12.5 MHz clock\n");
break;
case ESPCTRL_CLK16MHz:
Log_Printf(LOG_ESPDMA_LEVEL, "16.6 MHz clock\n");
break;
case ESPCTRL_CLK20MHz:
Log_Printf(LOG_ESPDMA_LEVEL, "20 MHz clock\n");
break;
default:
break;
}
}
bool AsyncResult::execute()
{
bool should_call = false;
{
Lock::scoped_lock locker(lock_);
if (status_ == WAIT) {
should_call = true;
status_ = RUNNING;
}
}
if (should_call) {
try {
task_(*this);
set_success();
} catch (AvalonException& err) {
set_error(&err);
} catch (boost::thread_interrupted) {
set_interrupt();
throw;
} catch (...) {
set_error();
}
}
return should_call;
}
void tmc_vir_write0(Uint8 val) {
tmc.video_intr = val;
if (tmc.video_intr&TMC_VI_INTERRUPT) {
tmc.video_intr &= ~TMC_VI_INTERRUPT;
set_interrupt(INT_DISK, RELEASE_INT);
}
}
void upd3301_device::device_reset()
{
set_interrupt(0);
set_drq(0);
recompute_parameters();
}
void upd3301_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
{
switch (id)
{
case TIMER_HRTC:
if (LOG) logerror("UPD3301 '%s' HRTC: %u\n", tag(), param);
m_out_hrtc_func(param);
m_hrtc = param;
update_hrtc_timer(param);
break;
case TIMER_VRTC:
if (LOG) logerror("UPD3301 '%s' VRTC: %u\n", tag(), param);
m_out_vrtc_func(param);
m_vrtc = param;
if (param && !m_me)
{
m_status |= STATUS_E;
set_interrupt(1);
}
update_vrtc_timer(param);
break;
case TIMER_DRQ:
break;
}
}
void sc499_device::set_tc_state(int state)
{
LOG2(("set_tc_state: block=%d state=%x", m_tape_pos-1, state));
if (state == 0)
{
m_status |= SC499_STAT_DON; // 37ec
set_dma_drq(CLEAR_LINE);
switch (m_current_command & SC499_CMD_TYPE_MASK)
{
case SC499_CMD_READ_DATA:
m_read_block_pending = 0;
break;
case SC499_CMD_WRITE_DATA:
m_status &= ~SC499_STAT_RDY;
if ((m_control & SC499_CTR_IEN) && (m_control & SC499_CTR_DNI))
{
set_interrupt(ASSERT_LINE);
m_status |= SC499_STAT_IRQ;
}
break;
}
}
}
/*
* STUB: once register_interrupt_handler() is called, this routine
* gets called each time SIG_TYPE is sent to this process
*/
static void
interrupt_handler(int sig, siginfo_t * sip, void *contextVP)
{
ucontext_t *context = (ucontext_t *) contextVP;
/* check that SIG_TYPE is blocked on entry */
assert(!interrupts_enabled());
if (loud) {
int ret;
ret = gettimeofday(&end, NULL);
assert(!ret);
if (first) {
first = 0;
} else {
timersub(&end, &start, &diff);
}
start = end;
printf("%s: context at %10p, time diff = %ld us\n",
__FUNCTION__, context,
diff.tv_sec * 1000000 + diff.tv_usec);
}
set_interrupt();
/* implement preemptive threading by calling thread_yield */
thread_yield(THREAD_ANY);
}
void threecom3c505_device::do_receive_command()
{
// receive pending and no other command is pending
if (m_rx_pending > 0 && !m_command_pending)
{
if (m_rx_data_buffer.get_length() == 0 && !m_rx_fifo.is_empty())
{
m_rx_fifo.get(&m_rx_data_buffer);
}
// receive data available ?
if (m_rx_data_buffer.get_length() > 0)
{
LOG2(("do_receive_command - data_length=%x rx_pending=%d",
m_rx_data_buffer.get_length(), m_rx_pending));
m_rx_pending--;
set_command_pending(1);
// preset receive response PCB
memcpy(&m_response, &m_rcv_response, sizeof(m_rcv_response));
// m_response.command = CMD_RECEIVE_PACKET_COMPLETE; // 0x38
// m_response.length = 16;
// m_response.data.rcv_resp.buf_ofs = htole16(0);
// m_response.data.rcv_resp.buf_seg = htole16(0);
// m_response.data.rcv_resp.buf_len = htole16(buf_len);
// htole16 and friends are not portable beyond Linux. It's named differently on *BSD and differently again on OS X. Avoid!
m_response.data.rcv_resp.pkt_len = uint16_to_le(m_rx_data_buffer.get_length());
m_response.data.rcv_resp.timeout = 0; // successful completion
m_response.data.rcv_resp.status = uint16_to_le(m_rx_data_buffer.get_length() > 0 ? 0 : 0xffff);
m_response.data.rcv_resp.timetag = 0; // TODO: time tag
// compute and check no of bytes to be DMA'ed (must be even)
UINT16 buf_len = uint16_from_le(m_response.data.rcv_resp.buf_len) & ~1;
if (m_rx_data_buffer.get_length() > buf_len)
{
LOG1(("do_receive_command !!! buffer size too small (%d < %d)", buf_len, m_rx_data_buffer.get_length()));
m_response.data.rcv_resp.pkt_len = uint16_to_le(buf_len);
m_response.data.rcv_resp.status = 0xffff;
}
else
{
buf_len = (m_rx_data_buffer.get_length() + 1) & ~1;
m_response.data.rcv_resp.buf_len = uint16_to_le(buf_len);
}
m_response_length = m_response.length + 2;
m_response_index = 0;
m_status |= ACRF; /* set adapter command register full */
if (m_control & CMDE)
{
set_interrupt(ASSERT_LINE);
}
}
}
}
void EN_RX_Mask_Write(void) {
enet.rx_mask=IoMem[IoAccessCurrentAddress & IO_SEG_MASK];
Log_Printf(LOG_EN_REG_LEVEL,"[EN] Receiver masks write at $%08x val=$%02x PC=$%08x\n", IoAccessCurrentAddress, IoMem[IoAccessCurrentAddress & IO_SEG_MASK], m68k_getpc());
if ((enet.rx_status&enet.rx_mask&0x8F)==0) {
set_interrupt(INT_EN_RX, RELEASE_INT);
}
}
void EN_TX_Mask_Write(void) {
enet.tx_mask=IoMem[IoAccessCurrentAddress & IO_SEG_MASK];
Log_Printf(LOG_EN_REG_LEVEL,"[EN] Transmitter masks write at $%08x val=$%02x PC=$%08x\n", IoAccessCurrentAddress, IoMem[IoAccessCurrentAddress & IO_SEG_MASK], m68k_getpc());
if ((enet.tx_status&enet.tx_mask&0x0F)==0 || (enet.tx_status&enet.tx_mask&0x0F)==TXSTAT_READY) {
set_interrupt(INT_EN_TX, RELEASE_INT);
}
}
/* This is the function called when the Guest's timer expires. */
static enum hrtimer_restart clockdev_fn(struct hrtimer *timer)
{
struct lg_cpu *cpu = container_of(timer, struct lg_cpu, hrt);
/* Remember the first interrupt is the timer interrupt. */
set_interrupt(cpu, 0);
return HRTIMER_NORESTART;
}
void m68307_cpu_device::licr2_interrupt()
{
int prioritylevel = (m68307SIM->m_licr2 & 0x0007)>>0;
int vector = (m68307SIM->m_pivr & 0x00f0) | 0x9;
m68307SIM->m_licr2 |= 0x8;
set_interrupt(prioritylevel, vector);
}
void tms5501_device::tra_complete()
{
if (!(m_sta & STA_XBE))
{
transmit_register_setup(m_tb);
m_sta |= STA_XBE;
set_interrupt(IRQ_TB);
}
}
int MDTRA_WaitDialog::qt_metacall(QMetaObject::Call _c, int _id, void **_a)
{
_id = QDialog::qt_metacall(_c, _id, _a);
if (_id < 0)
return _id;
if (_c == QMetaObject::InvokeMetaMethod) {
switch (_id) {
case 0: set_interrupt(); break;
default: ;
}
_id -= 1;
}
return _id;
}
void z80sio_device::sio_channel::change_input_line(int line, int state)
{
VPRINTF(("sio_change_input_line(%c, %s) = %d\n", 'A' + m_index, (line == SIO_RR0_CTS) ? "CTS" : "DCD", state));
// remember the old value
UINT8 old = m_status[0];
// set the bit in the status register
m_status[0] &= ~line;
if (state)
m_status[0] |= line;
// if state change interrupts are enabled, signal
if (((old ^ m_status[0]) & line) && (m_regs[1] & SIO_WR1_STATUSINT_ENABLE))
set_interrupt(INT_STATUS);
}
void v1050_state::scan_keyboard()
{
static const char *const keynames[] = { "ROW0", "ROW1", "ROW2", "ROW3", "ROW4", "ROW5", "ROW6", "ROW7", "ROW8", "ROW9", "ROW10", "ROW11" };
int table = 0, row, col;
int keydata = 0xff;
UINT8 line_mod = ioport("ROW12")->read();
if((line_mod & 0x07) && (line_mod & 0x18))
{
table = 3; // shift & control
}
else if (line_mod & 0x07)
{
table = 1; // shifted
}
else if (line_mod & 0x18)
{
table = 2; // ctrl
}
// scan keyboard
for (row = 0; row < 12; row++)
{
UINT8 data = ioport(keynames[row])->read();
for (col = 0; col < 8; col++)
{
if (!BIT(data, col))
{
// latch key data
keydata = V1050_KEYCODES[table][row][col];
if (m_keydata != keydata)
{
m_keydata = keydata;
m_keyavail = 1;
set_interrupt(INT_KEYBOARD, 1);
return;
}
}
}
}
m_keydata = keydata;
}
UINT8 sc499_device::read_status_port()
{
static UINT8 m_last_status = 0xff;
// omit excessive logging
if (m_last_status != m_status)
{
LOG2(("read_status_port: %02x", m_status));
m_last_status = m_status;
}
// reset pending interrupts
set_interrupt(CLEAR_LINE);
m_status &= ~SC499_STAT_IRQ;
return m_last_status;
}
UINT8 sc499_device::read_data_port()
{
static UINT8 m_last_data = 0xff;
// omit excessive logging
if (m_last_data != m_data)
{
LOG2(("read_data_port: %02x", m_data));
m_last_data = m_data;
}
if (m_control & SC499_CTR_IEN)
{
set_interrupt(CLEAR_LINE);
m_status &= ~SC499_STAT_IRQ;
}
return m_data;
}
//READ8_DEVICE_HANDLER( threecom3c505_r )
UINT8 threecom3c505_device::read_port(offs_t offset)
{
// data to omit excessive logging
static UINT8 last_data = 0xff;
static UINT32 last_pc = 0;
UINT8 data = m_reg[offset & 0x0f];
switch (offset)
{
case PORT_COMMAND: /* 0x00 read/write, 8-bit */
data = read_command_port();
break;
case PORT_STATUS: /* 0x02 read only, 8-bit */
data=read_status_port();
set_interrupt(CLEAR_LINE);
// omit excessive logging
if (data == last_data)
{
UINT32 pc = machine().device(MAINCPU)->safe_pcbase();
if (pc == last_pc) {
return data;
}
last_pc = pc;
}
last_data = data;
break;
case PORT_DATA: /* 0x04 read/write, 16-bit */
case PORT_DATA + 1: /* 0x04 read/write, 16-bit */
data = read_data_port();
break;
case PORT_CONTROL: /* 0x06 read/write, 8-bit */
// just return current value
break;
default:
break;
}
LOG2(("reading 3C505 Register at offset %02x = %02x", offset, data));
return data;
}
int *ezpstart()
{
register int i, *adr;
int *save_globl();
setup_page();
setup_strings();
liney = (SYSDOM*)scrsave;
staffy = (int*)&liney[MAXLIN];
measnum = &staffy[MAXSYS];
systems = (SYSDOM*)&measnum[MAXSYS];
brackets = (LBRACK*)&systems[MAXSYS];
braces = (LBRACE*)&brackets[MAXCON];
for (i = 0; i < MAXCON; i++) {
braces[i].top = 0;
braces[i].psym = (PSYM*)0L;
braces[i].size = 0;
brackets[i].top = 0;
brackets[i].size = 0;
}
abortp = voff = FALSE;
init_symb_structs();
adr = (int*)&braces[MAXCON];
s_image = (short*)save_globl( adr );
calc_bufsize();
graf_mouse( ARROW );
wind_get( DESKTOP, WF_WORKXYWH, &desk.g_x, &desk.g_y, &desk.g_w,
&desk.g_h );
prinaddr->ob_x = (desk.g_x + desk.g_w - prinaddr->ob_width) >> 1;
prinaddr->ob_y = (desk.g_y + desk.g_h - prinaddr->ob_height) >> 1;
((TEDINFO*)(prinaddr[PRNTYPE].ob_spec))->te_ptext = prname;
objc_draw( prinaddr, ROOT, MAX_DEPTH, prinaddr->ob_x - 3,
prinaddr->ob_y - 3, prinaddr->ob_width + 6, prinaddr->ob_height + 6 );
objc_offset( prinaddr, ABORT, &abort.g_x, &abort.g_y );
abort.g_w = prinaddr[ABORT].ob_width;
abort.g_h = prinaddr[ABORT].ob_height;
set_interrupt();
return adr;
}
t_stat lpt_devio(uint32 dev, uint64 *data) {
UNIT *uptr = &lpt_unit;
switch(dev & 3) {
case CONI:
*data = uptr->STATUS;
if ((uptr->flags & UNIT_UC) == 0)
*data |= C96;
if ((uptr->flags & UNIT_ATT) == 0)
*data |= ERR_FLG;
sim_debug(DEBUG_CONI, &lpt_dev, "LP CONI %012llo PC=%06o\n", *data, PC);
break;
case CONO:
clr_interrupt(dev);
sim_debug(DEBUG_CONO, &lpt_dev, "LP CONO %012llo PC=%06o\n", *data, PC);
uptr->STATUS = ((PI_DONE|PI_ERROR|DONE_FLG|BUSY_FLG) & *data);
if (*data & CLR_LPT) {
uptr->CHR = 0;
uptr->CHL = 0;
uptr->STATUS |= BUSY_FLG;
sim_activate (&lpt_unit, lpt_unit.wait);
}
if ((uptr->flags & UNIT_ATT) == 0) {
set_interrupt(dev, (uptr->STATUS >> 3));
}
if (uptr->STATUS & DONE_FLG)
set_interrupt(dev, uptr->STATUS);
break;
case DATAO:
if ((uptr->STATUS & BUSY_FLG) == 0) {
uptr->CHL = (int32)(*data >> 15);
uptr->CHR = (*data >> 1) & 0037777;
uptr->STATUS |= BUSY_FLG;
uptr->STATUS &= ~DONE_FLG;
clr_interrupt(dev);
sim_activate (&lpt_unit, lpt_unit.wait);
}
static void
do_event(void *data)
{
ide_controller *controller = data;
device *me = controller->me;
controller->event_tag = 0;
switch (controller->state) {
case busy_loaded_state:
case busy_drained_state:
if (controller->current_transfer > 0) {
controller->state = (controller->state == busy_loaded_state
? loading_state : draining_state);
}
else {
controller->state = idle_state;
}
set_interrupt(me, controller);
break;
default:
device_error(me, "controller %d - unexpected event", controller->nr);
break;
}
}
void tms5501_device::rcv_complete()
{
receive_register_extract();
m_rb = get_received_char();
if (is_receive_framing_error())
{
m_sta |= STA_FE;
}
else
{
m_sta &= ~STA_FE;
}
if (m_sta & STA_RBL)
{
m_sta |= STA_OE;
}
m_sta |= (STA_RBL | STA_SR);
m_sta &= ~(STA_SBD | STA_FBD);
set_interrupt(IRQ_RB);
}
void sc499_device::do_reset()
{
LOG1(("do_reset: Reset controller microprocessor"));
m_data = 0;
m_command = SC499_CMD_NO_COMMAND;
m_current_command = m_command;
m_status = ~(SC499_STAT_DIR | SC499_STAT_EXC);
m_control = 0;
if (m_has_cartridge)
{
tape_status_set(SC499_ST1_POR | SC499_ST1_BOM);
}
m_tape_pos = 0;
m_data_error_counter = 0;
m_underrun_counter = 0;
set_interrupt(CLEAR_LINE);
set_dma_drq(CLEAR_LINE);
m_timer1->adjust( attotime::never, SC499_TIMER_6, attotime::never);
}
/* Should be called when you initialize threads package. Many of the calls won't
* make sense at first -- study the man pages! */
void
register_interrupt_handler(int verbose)
{
struct sigaction action;
int error;
static int init = 0;
assert(!init); /* should only register once */
init = 1;
loud = verbose;
action.sa_handler = NULL;
action.sa_sigaction = interrupt_handler;
/* SIG_TYPE will be blocked while interrupt_handler() is running. */
error = sigemptyset(&action.sa_mask);
assert(!error);
/* use sa_sigaction as handler instead of sa_handler */
action.sa_flags = SA_SIGINFO;
if (sigaction(SIG_TYPE, &action, NULL)) {
perror("Setting up signal handler");
assert(0);
}
set_interrupt();
}
void z80sio_device::sio_channel::serial_callback()
{
int data = -1;
// first perform any outstanding transmits
if (m_outbuf != -1)
{
VPRINTF(("serial_callback(%c): Transmitting %02x\n", 'A' + m_index, m_outbuf));
// actually transmit the character
if (m_device->m_transmit_cb != NULL)
(*m_device->m_transmit_cb)(m_device, m_index, m_outbuf);
// update the status register
m_status[0] |= SIO_RR0_TX_BUFFER_EMPTY;
// set the transmit buffer empty interrupt if enabled
if (m_regs[1] & SIO_WR1_TXINT_ENABLE)
set_interrupt(INT_TRANSMIT);
// reset the output buffer
m_outbuf = -1;
}
// ask the polling callback if there is data to receive
if (m_device->m_receive_poll_cb != NULL)
data = (*m_device->m_receive_poll_cb)(m_device, m_index);
// if we have buffered data, pull it
if (m_receive_inptr != m_receive_outptr)
{
data = m_receive_buffer[m_receive_outptr];
m_receive_outptr = (m_receive_outptr + 1) % ARRAY_LENGTH(m_receive_buffer);
}
// if we have data, receive it
if (data != -1)
{
VPRINTF(("serial_callback(%c): Receiving %02x\n", 'A' + m_index, data));
// if rx not enabled, just ignore it
if (!(m_regs[3] & SIO_WR3_RX_ENABLE))
{
VPRINTF((" (ignored because receive is disabled)\n"));
return;
}
// stash the data and update the status
m_inbuf = data;
m_status[0] |= SIO_RR0_RX_CHAR_AVAILABLE;
// update our interrupt state
switch (m_regs[1] & SIO_WR1_RXINT_MASK)
{
case SIO_WR1_RXINT_FIRST:
if (!m_int_on_next_rx)
break;
case SIO_WR1_RXINT_ALL_NOPARITY:
case SIO_WR1_RXINT_ALL_PARITY:
set_interrupt(INT_RECEIVE);
break;
}
m_int_on_next_rx = false;
}
}
inline void upd3301_device::reset_counters()
{
set_interrupt(0);
set_drq(0);
}
void omti8621_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
{
set_interrupt(ASSERT_LINE);
}
void omti8621_device::do_command(const UINT8 cdb[], const UINT16 cdb_length)
{
UINT8 lun = get_lun(cdb);
omti_disk_image_device *disk = our_disks[lun];
int command_duration = 0; // ms
log_command( cdb, cdb_length);
// default to read status and status is successful completion
omti_state = OMTI_STATE_STATUS;
status_port |= OMTI_STATUS_IO | OMTI_STATUS_CD;
command_status = lun ? OMTI_COMMAND_STATUS_LUN : 0;
if (mask_port & OMTI_MASK_INTE) {
set_interrupt(CLEAR_LINE);
}
if (!disk->m_image->exists()) {
command_status |= OMTI_COMMAND_STATUS_ERROR; // no such drive
}
switch (cdb[0]) {
case OMTI_CMD_TEST_DRIVE_READY: // 0x00
if (!disk->m_image->exists())
{
set_sense_data(OMTI_SENSE_CODE_DRIVE_NOT_READY, cdb);
}
break;
case OMTI_CMD_RECALIBRATE: // 0x01
break;
case OMTI_CMD_REQUEST_SENSE: // 0x03
set_data_transfer(sense_data, sizeof(sense_data));
break;
case OMTI_CMD_READ_VERIFY: // 0x05
check_disk_address(cdb);
break;
case OMTI_CMD_FORMAT_TRACK: // 0x06
format_track(cdb);
break;
case OMTI_CMD_FORMAT_BAD_TRACK: // 0x07
diskaddr_format_bad_track = get_disk_address(cdb);
break;
case OMTI_CMD_READ: // 0x08
if (check_disk_address(cdb)) {
// read data from controller
read_sectors_from_disk(get_disk_address(cdb), cdb[4], lun);
set_data_transfer(§or_buffer[0], OMTI_DISK_SECTOR_SIZE*cdb[4]);
}
break;
case OMTI_CMD_WRITE: // 0x0A
log_data();
if (check_disk_address(cdb)) {
write_sectors_to_disk(get_disk_address(cdb), cdb[4], lun);
}
break;
case OMTI_CMD_SEEK: // 0x0B
check_disk_address(cdb);
break;
case OMTI_CMD_READ_SECTOR_BUFFER: // 0x0E
set_data_transfer(§or_buffer[0], OMTI_DISK_SECTOR_SIZE*cdb[4]);
break;
case OMTI_CMD_WRITE_SECTOR_BUFFER: // 0x0F
log_data();
break;
case OMTI_CMD_COPY: // 0x20
if (check_disk_address(cdb) && check_disk_address(cdb+4)) {
// copy sectors
copy_sectors (get_disk_address(cdb+4), get_disk_address(cdb), cdb[4], lun);
}
break;
case OMTI_CMD_READ_ESDI_DEFECT_LIST: // 0x37
set_esdi_defect_list(get_lun(cdb), cdb[1] & 0x1f);
set_data_transfer(disk->m_esdi_defect_list, sizeof(disk->m_esdi_defect_list));
break;
#if 0 // this command seems unused by Domain/OS, and it's unclear what the intent of the code is (it makes some versions of GCC quite unhappy)
case OMTI_CMD_ASSIGN_ALTERNATE_TRACK: // 0x11
log_data();
alternate_track_address[0] = get_disk_track(cdb);
alternate_track_address[1] = get_disk_track(alternate_track_buffer-1);
break;
#endif
case OMTI_CMD_READ_DATA_TO_BUFFER: // 0x1E
if (check_disk_address(cdb)) {
// read data from controller
read_sectors_from_disk (get_disk_address(cdb), cdb[4], lun);
// Domain/OS doesn't expect zero access time
command_duration += 1; // 1 ms is enough, average time would be 30 ms)
}
break;
case OMTI_CMD_WRITE_DATA_FROM_BUFFER: // 0x1F
log_data();
if (check_disk_address(cdb)) {
write_sectors_to_disk(get_disk_address(cdb), cdb[4], lun);
}
break;
case OMTI_CMD_RAM_DIAGNOSTICS: // 0xE0
break;
case OMTI_CMD_CONTROLLER_INT_DIAGNOSTIC: // 0xE4
break;
case OMTI_CMD_READ_LONG: // 0xE5
if (check_disk_address(cdb)) {
// read data from controller
read_sectors_from_disk(get_disk_address(cdb), cdb[4], lun);
set_data_transfer(§or_buffer[0], OMTI_DISK_SECTOR_SIZE+6);
}
break;
case OMTI_CMD_WRITE_LONG: // 0xE6
log_data();
if (check_disk_address(cdb)) {
UINT32 diskaddr = get_disk_address(cdb);
write_sectors_to_disk(diskaddr, cdb[4], lun);
// this will spoil the ECC code
diskaddr_ecc_error = diskaddr;
}
break;
case OMTI_CMD_READ_CONFIGURATION: // 0xEC
set_configuration_data(get_lun(cdb));
set_data_transfer(disk->m_config_data, sizeof(disk->m_config_data));
break;
case OMTI_CMD_INVALID_COMMAND: // 0xFF
set_sense_data(OMTI_SENSE_CODE_INVALID_COMMAND, cdb);
command_status |= OMTI_COMMAND_STATUS_ERROR;
break;
default:
LOG(("do_command: UNEXPECTED command %02x",cdb[0]));
set_sense_data(OMTI_SENSE_CODE_INVALID_COMMAND, cdb);
command_status |= OMTI_COMMAND_STATUS_ERROR;
break;
}
if (mask_port & OMTI_MASK_INTE) {
// if (omti_state != OMTI_STATE_STATUS) {
// LOG(("do_command: UNEXPECTED omti_state %02x",omti_state));
// }
status_port |= OMTI_STATUS_IREQ;
if (command_duration == 0)
{
set_interrupt(ASSERT_LINE);
}
else
{
// FIXME: should delay omti_state and status_port as well
m_timer->adjust(attotime::from_msec(command_duration), 0);
}
}
}
