static void set_pc_bit(const device_config *device, int bit, int state)
{
i8255a_t *i8255a = get_safe_token(device);
/* set output latch bit */
i8255a->output[PORT_C] &= ~(1 << bit);
i8255a->output[PORT_C] |= state << bit;
switch (group_mode(i8255a, GROUP_A))
{
case MODE_1:
if (port_mode(i8255a, PORT_A) == MODE_OUTPUT)
{
switch (bit)
{
case 3: set_intr(i8255a, PORT_A, state); break;
case 6: set_inte(i8255a, PORT_A, state); break;
case 7: set_obf(i8255a, PORT_A, state); break;
}
}
else
{
switch (bit)
{
case 3: set_intr(i8255a, PORT_A, state); break;
case 4: set_inte(i8255a, PORT_A, state); break;
case 5: set_ibf(i8255a, PORT_A, state); break;
}
}
break;
case MODE_2:
switch (bit)
{
case 3: set_intr(i8255a, PORT_A, state); break;
case 4: set_inte2(i8255a, state); break;
case 5: set_ibf(i8255a, PORT_A, state); break;
case 6: set_inte1(i8255a, state); break;
case 7: set_obf(i8255a, PORT_A, state); break;
}
break;
}
if (group_mode(i8255a, GROUP_B) == MODE_1)
{
switch (bit)
{
case 0: set_intr(i8255a, PORT_B, state); break;
case 1:
if (port_mode(i8255a, PORT_B) == MODE_OUTPUT)
set_obf(i8255a, PORT_B, state);
else
set_ibf(i8255a, PORT_B, state);
break;
case 2: set_inte(i8255a, PORT_B, state); break;
}
}
output_pc(i8255a);
}
void init_idt()
{
int i;
for (i = 0;i < NR_IRQ;i ++)
{
set_trap(idt + i, SEG_KERNEL_CODE, (uint32_t)irq_empty, DPL_KERNEL);
}
set_trap(idt + 0, SEG_KERNEL_CODE, (uint32_t)vec0, DPL_KERNEL);
set_trap(idt + 1, SEG_KERNEL_CODE, (uint32_t)vec1, DPL_KERNEL);
set_trap(idt + 2, SEG_KERNEL_CODE, (uint32_t)vec2, DPL_KERNEL);
set_trap(idt + 3, SEG_KERNEL_CODE, (uint32_t)vec3, DPL_KERNEL);
set_trap(idt + 4, SEG_KERNEL_CODE, (uint32_t)vec4, DPL_KERNEL);
set_trap(idt + 5, SEG_KERNEL_CODE, (uint32_t)vec5, DPL_KERNEL);
set_trap(idt + 6, SEG_KERNEL_CODE, (uint32_t)vec6, DPL_KERNEL);
set_trap(idt + 7, SEG_KERNEL_CODE, (uint32_t)vec7, DPL_KERNEL);
set_trap(idt + 8, SEG_KERNEL_CODE, (uint32_t)vec8, DPL_KERNEL);
set_trap(idt + 9, SEG_KERNEL_CODE, (uint32_t)vec9, DPL_KERNEL);
set_trap(idt + 10, SEG_KERNEL_CODE, (uint32_t)vec10, DPL_KERNEL);
set_trap(idt + 11, SEG_KERNEL_CODE, (uint32_t)vec11, DPL_KERNEL);
set_trap(idt + 12, SEG_KERNEL_CODE, (uint32_t)vec12, DPL_KERNEL);
set_trap(idt + 13, SEG_KERNEL_CODE, (uint32_t)vec13, DPL_KERNEL);
set_trap(idt + 14, SEG_KERNEL_CODE, (uint32_t)vec14, DPL_KERNEL);
set_trap(idt + 0x80, SEG_KERNEL_CODE, (uint32_t)vecsys, DPL_USER);
set_intr(idt + 32, SEG_KERNEL_CODE, (uint32_t)irq0, DPL_KERNEL);
set_intr(idt + 32 + 1, SEG_KERNEL_CODE, (uint32_t)irq1, DPL_KERNEL);
set_intr(idt + 32 + 14, SEG_KERNEL_CODE, (uint32_t)irq14, DPL_KERNEL);
save_idt(idt, sizeof(idt));
}
void init_idt() {
int i;
for (i = 0; i < NR_IRQ; i ++) {
set_trap(idt + i, SEG_KERNEL_CODE << 3, (uint32_t)irq_empty, DPL_KERNEL);
}
set_trap(idt + 0, SEG_KERNEL_CODE << 3, (uint32_t)vec0, DPL_KERNEL);
set_trap(idt + 1, SEG_KERNEL_CODE << 3, (uint32_t)vec1, DPL_KERNEL);
set_trap(idt + 2, SEG_KERNEL_CODE << 3, (uint32_t)vec2, DPL_KERNEL);
set_trap(idt + 3, SEG_KERNEL_CODE << 3, (uint32_t)vec3, DPL_KERNEL);
set_trap(idt + 4, SEG_KERNEL_CODE << 3, (uint32_t)vec4, DPL_KERNEL);
set_trap(idt + 5, SEG_KERNEL_CODE << 3, (uint32_t)vec5, DPL_KERNEL);
set_trap(idt + 6, SEG_KERNEL_CODE << 3, (uint32_t)vec6, DPL_KERNEL);
set_trap(idt + 7, SEG_KERNEL_CODE << 3, (uint32_t)vec7, DPL_KERNEL);
set_trap(idt + 8, SEG_KERNEL_CODE << 3, (uint32_t)vec8, DPL_KERNEL);
set_trap(idt + 9, SEG_KERNEL_CODE << 3, (uint32_t)vec9, DPL_KERNEL);
set_trap(idt + 10, SEG_KERNEL_CODE << 3, (uint32_t)vec10, DPL_KERNEL);
set_trap(idt + 11, SEG_KERNEL_CODE << 3, (uint32_t)vec11, DPL_KERNEL);
set_trap(idt + 12, SEG_KERNEL_CODE << 3, (uint32_t)vec12, DPL_KERNEL);
set_trap(idt + 13, SEG_KERNEL_CODE << 3, (uint32_t)vec13, DPL_KERNEL);
set_trap(idt + 14, SEG_KERNEL_CODE << 3, (uint32_t)vec14, DPL_KERNEL);
/* the system call 0x80 */
set_trap(idt + 0x80, SEG_KERNEL_CODE << 3, (uint32_t)vecsys, DPL_USER);
set_intr(idt+32 + 0, SEG_KERNEL_CODE << 3, (uint32_t)irq0, DPL_KERNEL);
set_intr(idt+32 + 1, SEG_KERNEL_CODE << 3, (uint32_t)irq1, DPL_KERNEL); // keyboard
set_intr(idt+32 + 14, SEG_KERNEL_CODE << 3, (uint32_t)irq14, DPL_KERNEL);
/* the ``idt'' is its virtual address */
write_idtr(idt, sizeof(idt));
}
void init_idt() {
int i;
/* 为了防止系统异常终止，所有irq都有处理函数(irq_empty)。 */
for (i = 0; i < NR_IRQ; i ++) {
set_trap(idt + i, SEG_KERNEL_CODE, (uint32_t)irq_empty, DPL_KERNEL);
}
/* 设置异常的中断处理 */
set_trap(idt + 0, SEG_KERNEL_CODE, (uint32_t)vec0, DPL_KERNEL);
set_trap(idt + 1, SEG_KERNEL_CODE, (uint32_t)vec1, DPL_KERNEL);
set_trap(idt + 2, SEG_KERNEL_CODE, (uint32_t)vec2, DPL_KERNEL);
set_trap(idt + 3, SEG_KERNEL_CODE, (uint32_t)vec3, DPL_KERNEL);
set_trap(idt + 4, SEG_KERNEL_CODE, (uint32_t)vec4, DPL_KERNEL);
set_trap(idt + 5, SEG_KERNEL_CODE, (uint32_t)vec5, DPL_KERNEL);
set_trap(idt + 6, SEG_KERNEL_CODE, (uint32_t)vec6, DPL_KERNEL);
set_trap(idt + 7, SEG_KERNEL_CODE, (uint32_t)vec7, DPL_KERNEL);
set_trap(idt + 8, SEG_KERNEL_CODE, (uint32_t)vec8, DPL_KERNEL);
set_trap(idt + 9, SEG_KERNEL_CODE, (uint32_t)vec9, DPL_KERNEL);
set_trap(idt + 10, SEG_KERNEL_CODE, (uint32_t)vec10, DPL_KERNEL);
set_trap(idt + 11, SEG_KERNEL_CODE, (uint32_t)vec11, DPL_KERNEL);
set_trap(idt + 12, SEG_KERNEL_CODE, (uint32_t)vec12, DPL_KERNEL);
set_trap(idt + 13, SEG_KERNEL_CODE, (uint32_t)vec13, DPL_KERNEL);
/* 设置外部中断的处理 */
set_intr(idt + 32, SEG_KERNEL_CODE, (uint32_t)irq0, DPL_KERNEL);
set_intr(idt + 33, SEG_KERNEL_CODE, (uint32_t)irq1, DPL_KERNEL);
/* 写入IDT */
save_idt(idt, sizeof(idt));
}
void
macebusattach(struct device *parent, struct device *self, void *aux)
{
u_int32_t creg;
uint i;
/*
* Map and setup CRIME control registers.
*/
if (bus_space_map(&crimebus_tag, 0x00000000, 0x400, 0, &crime_h)) {
printf(": can't map CRIME control registers\n");
return;
}
creg = bus_space_read_8(&crimebus_tag, crime_h, CRIME_REVISION);
printf(": crime rev %d.%d\n", (creg & 0xf0) >> 4, creg & 0xf);
bus_space_write_8(&crimebus_tag, crime_h, CRIME_CPU_ERROR_STAT, 0);
bus_space_write_8(&crimebus_tag, crime_h, CRIME_MEM_ERROR_STAT, 0);
bus_space_write_8(&crimebus_tag, crime_h, CRIME_INT_MASK, 0);
bus_space_write_8(&crimebus_tag, crime_h, CRIME_INT_SOFT, 0);
bus_space_write_8(&crimebus_tag, crime_h, CRIME_INT_HARD, 0);
bus_space_write_8(&crimebus_tag, crime_h, CRIME_INT_STAT, 0);
/*
* Map and setup MACE ISA control registers.
*/
if (bus_space_map(&macebus_tag, MACE_ISA_OFFS, 0x400, 0, &mace_h)) {
printf("%s: can't map MACE control registers\n",
self->dv_xname);
return;
}
bus_space_write_8(&macebus_tag, mace_h, MACE_ISA_INT_MASK, 0);
bus_space_write_8(&macebus_tag, mace_h, MACE_ISA_INT_STAT, 0);
/*
* On O2 systems all interrupts are handled by the macebus interrupt
* handler. Register all except clock.
*/
set_intr(INTPRI_MACEIO, CR_INT_0, macebus_iointr);
register_splx_handler(macebus_splx);
/* Set up a handler called when clock interrupts go off. */
set_intr(INTPRI_MACEAUX, CR_INT_5, macebus_aux);
/*
* Attach subdevices.
*/
for (i = 0; i < nitems(macebus_children); i++)
config_found_sm(self, macebus_children + i,
macebusprint, macebussubmatch);
}
uint8_t i8255_device::read_mode1(int port)
{
uint8_t data;
if (port_mode(port) == MODE_OUTPUT)
{
// read data from output latch
data = m_output[port];
}
else
{
// read data from input latch
data = m_input[port];
// clear input buffer full flag
set_ibf(port, 0);
// clear interrupt
set_intr(port, 0);
// clear input latch
m_input[port] = 0;
}
return data;
}
void
clockattach(struct device *parent, struct device *self, void *aux)
{
struct clock_softc *sc;
md_clk_attach(parent, self, aux);
sc = (struct clock_softc *)self;
switch (sys_config.system_type) {
case ALGOR_P4032:
case ALGOR_P5064:
case MOMENTUM_CP7000:
case MOMENTUM_CP7000G:
case MOMENTUM_JAGUAR:
case GALILEO_EV64240:
case SGI_INDY:
case SGI_O2:
case SGI_O200:
printf(" ticker on int5 using count register");
set_intr(INTPRI_CLOCK, CR_INT_5, clock_int5);
ticktime = sys_config.cpu[0].clock / 2000;
break;
default:
panic("clockattach: it didn't get here. really.");
}
printf("\n");
}
void
obioattach(struct device *parent, struct device *self, void *aux)
{
uint i;
/*
* Map and setup CRIME control registers.
*/
if (bus_space_map(&obio_tag, OCTEON_CIU_BASE, OCTEON_CIU_SIZE, 0,
&obio_h)) {
printf(": can't map CIU control registers\n");
return;
}
printf("\n");
obio_intr_init();
set_intr(INTPRI_CIU_0, CR_INT_0, obio_iointr);
register_splx_handler(obio_splx);
/*
* Attach subdevices.
*/
for (i = 0; i < nitems(obio_children); i++)
config_found_sm(self, obio_children + i,
obioprint, obiosubmatch);
}
int raise_intr(int intr_num) {
pthread_mutex_lock(&intr_line.intr_mutex);
if (irq_masked(intr_num));
return -1;
if (intr_num < 64) {
set_intr(intr_num, &intr_line.intr[0]);
} else if (intr_num >= 64 && intr_num < 128) {
set_intr(intr_num%64, &intr_line.intr[1]);
} else if (intr_num >= 128 && intr_num < 192) {
set_intr(intr_num%128, &intr_line.intr[2]);
} else {
set_intr(intr_num%192, &intr_line.intr[3]);
}
pthread_mutex_unlock(&intr_line.intr_mutex);
return 0;
}
void
lemote_isa_attach_hook(struct device *parent, struct device *self,
struct isabus_attach_args *iba)
{
set_intr(INTPRI_ISA, CR_INT_0, lemote_isa_intr);
/* disable all isa interrupt sources */
REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + 1) = 0xff;
REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + 2) = 0xff;
loongson_generic_isa_attach_hook(parent, self, iba);
}
inline void i8255_device::check_interrupt(int port)
{
switch (group_mode(port))
{
case MODE_1:
switch (port_mode(port))
{
case MODE_INPUT:
set_intr(port, (m_inte[port] && m_ibf[port]));
break;
case MODE_OUTPUT:
set_intr(port, (m_inte[port] && m_obf[port]));
break;
}
break;
case MODE_2:
set_intr(port, ((m_inte1 && m_obf[port]) || (m_inte2 && m_ibf[port])));
break;
}
}
void i8255_device::write_mode2(UINT8 data)
{
// latch output data
m_output[PORT_A] = data;
// write data to port
m_out_port_func[PORT_A](0, data);
// set output buffer full flag
set_obf(PORT_A, 0);
// clear interrupt
set_intr(PORT_A, 0);
}
void i8255_device::write_mode2(uint8_t data)
{
// latch output data
m_output[PORT_A] = data;
// write data to port
m_out_pa_cb((offs_t)0, data);
// set output buffer full flag
set_obf(PORT_A, 0);
// clear interrupt
set_intr(PORT_A, 0);
}
static void write_mode2(i8255a_t *i8255a, UINT8 data)
{
/* latch output data */
i8255a->output[PORT_A] = data;
/* write data to port */
devcb_call_write8(&i8255a->out_port_func[PORT_A], 0, data);
/* set output buffer full flag */
set_obf(i8255a, PORT_A, 0);
/* clear interrupt */
set_intr(i8255a, PORT_A, 0);
}
static UINT8 read_mode2(i8255a_t *i8255a)
{
UINT8 data = 0;
/* read data from input latch */
data = i8255a->input[PORT_A];
/* clear input buffer full flag */
set_ibf(i8255a, PORT_A, 0);
/* clear interrupt */
set_intr(i8255a, PORT_A, 0);
return data;
}
void init_idt()
{
int i;
for(i = 0; i < NR_IRQ; i++)
{
set_trap(idt + i, (uint32_t)irq_empty, SEG_KERNEL_CODE, DPL_KERNEL);
}
set_trap(idt + 0, (uint32_t)vec0, SEG_KERNEL_CODE, DPL_KERNEL);
set_trap(idt + 1, (uint32_t)vec1, SEG_KERNEL_CODE, DPL_KERNEL);
set_trap(idt + 2, (uint32_t)vec2, SEG_KERNEL_CODE, DPL_KERNEL);
set_trap(idt + 3, (uint32_t)vec3, SEG_KERNEL_CODE, DPL_USER);
set_trap(idt + 4, (uint32_t)vec4, SEG_KERNEL_CODE, DPL_USER);
set_trap(idt + 5, (uint32_t)vec5, SEG_KERNEL_CODE, DPL_KERNEL);
set_trap(idt + 6, (uint32_t)vec6, SEG_KERNEL_CODE, DPL_KERNEL);
set_trap(idt + 7, (uint32_t)vec7, SEG_KERNEL_CODE, DPL_KERNEL);
set_trap(idt + 8, (uint32_t)vec8, SEG_KERNEL_CODE, DPL_KERNEL);
set_trap(idt + 9, (uint32_t)vec9, SEG_KERNEL_CODE, DPL_KERNEL);
set_trap(idt + 10, (uint32_t)vec10, SEG_KERNEL_CODE, DPL_KERNEL);
set_trap(idt + 11, (uint32_t)vec11, SEG_KERNEL_CODE, DPL_KERNEL);
set_trap(idt + 12, (uint32_t)vec12, SEG_KERNEL_CODE, DPL_KERNEL);
set_trap(idt + 13, (uint32_t)vec13, SEG_KERNEL_CODE, DPL_KERNEL);
set_trap(idt + 14, (uint32_t)vec14, SEG_KERNEL_CODE, DPL_KERNEL);
set_intr(idt + 0x80, (uint32_t)vecsys, SEG_KERNEL_CODE, DPL_USER);
set_intr(idt + 32 + 0, (uint32_t)irq0, SEG_KERNEL_CODE, DPL_KERNEL);
set_intr(idt + 32 + 1, (uint32_t)irq1, SEG_KERNEL_CODE, DPL_KERNEL);
set_intr(idt + 32 + 14, (uint32_t)irq14, SEG_KERNEL_CODE, DPL_KERNEL);
uint16_t volatile data[3];
data[0] = sizeof(idt) - 1;
data[1] = (uint32_t)idt;
data[2] = ((uint32_t)idt) >> 16;
asm volatile("lidt (%0)"::"r"(data));
}
static void write_mode1(i8255a_t *i8255a, int port, UINT8 data)
{
if (port_mode(i8255a, port) == MODE_OUTPUT)
{
/* latch output data */
i8255a->output[port] = data;
/* write data to port */
devcb_call_write8(&i8255a->out_port_func[port], 0, data);
/* set output buffer full flag */
set_obf(i8255a, port, 0);
/* clear interrupt */
set_intr(i8255a, port, 0);
}
}
void
clockattach(struct device *parent, struct device *self, void *aux)
{
printf(": int 5\n");
/*
* We need to register the interrupt now, for idle_mask to
* be computed correctly.
*/
set_intr(INTPRI_CLOCK, CR_INT_5, cp0_int5);
evcount_attach(&cp0_clock_count, "clock", &cp0_clock_irq);
/* try to avoid getting clock interrupts early */
cp0_set_compare(cp0_get_count() - 1);
md_startclock = cp0_startclock;
}
void i8255_device::write_mode1(int port, UINT8 data)
{
if (port_mode(port) == MODE_OUTPUT)
{
// latch output data
m_output[port] = data;
// write data to port
m_out_port_func[port](0, data);
// set output buffer full flag
set_obf(port, 0);
// clear interrupt
set_intr(port, 0);
}
}
uint8_t i8255_device::read_mode2()
{
uint8_t data;
// read data from input latch
data = m_input[PORT_A];
// clear input buffer full flag
set_ibf(PORT_A, 0);
// clear interrupt
set_intr(PORT_A, 0);
// clear input latch
m_input[PORT_A] = 0;
return data;
}
void
tcc_attach(struct device *parent, struct device *self, void *aux)
{
uint32_t ctrl, rev;
ctrl = (uint32_t)tcc_read(TCC_GCACHE_CTRL);
rev = (ctrl & TCC_GCACHE_REV_MASK) >> TCC_GCACHE_REV_SHIFT;
printf(": streaming cache revision %d\n", rev);
tcc_bus_reset();
/* Enable bus error and machine check interrupts. */
set_intr(INTPRI_BUSERR_TCC, CR_INT_4, tcc_bus_error);
tcc_write(TCC_INTR, TCC_INTR_MCHECK_ENAB | TCC_INTR_BERR_ENAB);
/* Enable all cache sets. */
tcc_write(TCC_GCACHE_CTRL, (ctrl | TCC_GCACHE_SET_ALL) &
~TCC_GCACHE_DISABLE_WB);
/* Enable prefetching. */
tcc_prefetch_enable();
}
void i8255_device::write_mode1(int port, uint8_t data)
{
if (port_mode(port) == MODE_OUTPUT)
{
// latch output data
m_output[port] = data;
// write data to port
if (port == PORT_A)
m_out_pa_cb((offs_t)0, m_output[port]);
else if (port == PORT_B)
m_out_pb_cb((offs_t)0, m_output[port]);
else
m_out_pc_cb((offs_t)0, m_output[port]);
// set output buffer full flag
set_obf(port, 0);
// clear interrupt
set_intr(port, 0);
}
}
static UINT8 read_mode1(i8255a_t *i8255a, int port)
{
UINT8 data = 0;
if (port_mode(i8255a, port) == MODE_OUTPUT)
{
/* read data from output latch */
data = i8255a->output[port];
}
else
{
/* read data from input latch */
data = i8255a->input[port];
/* clear input buffer full flag */
set_ibf(i8255a, port, 0);
/* clear interrupt */
set_intr(i8255a, port, 0);
}
return data;
}
void
imc_attach(struct device *parent, struct device *self, void *aux)
{
struct imc_attach_args iaa;
#if NEISA > 0
struct eisabus_attach_args eba;
#endif
uint32_t reg, lastreg;
uint32_t id, rev;
int have_eisa;
id = imc_read(IMC_SYSID);
rev = id & IMC_SYSID_REVMASK;
/* EISA exists on Indigo2 only */
if (sys_config.system_type != SGI_IP20 &&
sys_config.system_subtype == IP22_INDIGO2)
have_eisa = (id & IMC_SYSID_HAVEISA) != 0;
else
have_eisa = 0;
printf(": revision %d\n", rev);
/* Clear CPU/GIO error status registers to clear any leftover bits. */
imc_bus_reset();
/* Disable watchdog if leftover from previous reboot */
imc_watchdog_cb(self, 0);
/* Hook the bus error handler into the ISR */
set_intr(INTPRI_BUSERR, CR_INT_4, imc_bus_error);
/*
* Enable parity reporting on GIO/main memory transactions, except
* on systems with the ECC memory controller, where enabling parity
* interferes with regular operation and causes sticky false errors.
*
* Disable parity checking on CPU bus transactions (as turning
* it on seems to cause spurious bus errors), but enable parity
* checking on CPU reads from main memory (note that this bit
* has the opposite sense... Turning it on turns the checks off!).
*
* Finally, turn on interrupt writes to the CPU from the MC.
*/
reg = imc_read(IMC_CPUCTRL0);
if (ip22_ecc)
reg &= ~(IMC_CPUCTRL0_GPR | IMC_CPUCTRL0_MPR);
else
reg |= IMC_CPUCTRL0_GPR | IMC_CPUCTRL0_MPR;
reg &= ~IMC_CPUCTRL0_NCHKMEMPAR;
reg |= IMC_CPUCTRL0_INTENA;
imc_write(IMC_CPUCTRL0, reg);
/* Setup the MC write buffer depth */
/*
* XXX This hardcoded value is not documented anywhere, and can be
* XXX traced back to DaveM's internship at SGI in 1996, so it can
* XXX be considered correct at least for IP24 (and, to a lesser
* XXX extent, IP22). IP20 and IP28 systems seem to run happy with
* XXX this value as well.
*/
reg = imc_read(IMC_CPUCTRL1);
reg = (reg & ~IMC_CPUCTRL1_MCHWMSK) | 13;
/*
* Force endianness on the onboard HPC and both slots.
* This should be safe for Fullhouse, but leave it conditional
* for now.
*/
switch (sys_config.system_type) {
case SGI_IP22:
if (sys_config.system_subtype == IP22_INDIGO2)
break;
/* FALLTHROUGH */
case SGI_IP20:
reg |= IMC_CPUCTRL1_HPCFX;
reg |= IMC_CPUCTRL1_EXP0FX;
reg |= IMC_CPUCTRL1_EXP1FX;
reg &= ~IMC_CPUCTRL1_HPCLITTLE;
reg &= ~IMC_CPUCTRL1_EXP0LITTLE;
reg &= ~IMC_CPUCTRL1_EXP1LITTLE;
break;
}
imc_write(IMC_CPUCTRL1, reg);
/*
* Try and read the GIO64 arbitrator configuration register value.
* See comments above the declaration of imc_arb_value for why we
* are doing this.
*/
reg = 0; lastreg = ~reg;
while (reg != lastreg || (reg & ~0xffff) != 0) {
lastreg = reg;
reg = imc_read(IMC_GIO64ARB);
/* read another harmless register */
(void)imc_read(IMC_CPUCTRL0);
}
/*
* Set GIO64 arbitrator configuration register:
*
* Preserve PROM-set graphics-related bits, as they seem to depend
* on the graphics variant present and I'm not sure how to figure
* that out or 100% sure what the correct settings are for each.
*/
reg &= (IMC_GIO64ARB_GRX64 | IMC_GIO64ARB_GRXRT | IMC_GIO64ARB_GRXMST);
/*
* Rest of settings are machine/board dependent
*/
switch (sys_config.system_type) {
case SGI_IP20:
reg |= IMC_GIO64ARB_ONEGIO;
reg |= IMC_GIO64ARB_EXP0RT | IMC_GIO64ARB_EXP1RT;
reg |= IMC_GIO64ARB_EXP0MST | IMC_GIO64ARB_EXP1MST;
reg &= ~(IMC_GIO64ARB_HPC64 |
IMC_GIO64ARB_HPCEXP64 | IMC_GIO64ARB_EISA64 |
IMC_GIO64ARB_EXP064 | IMC_GIO64ARB_EXP164 |
IMC_GIO64ARB_EXP0PIPE | IMC_GIO64ARB_EXP1PIPE);
break;
default:
/*
* GIO64 invariant for all IP22 platforms: one GIO bus,
* HPC1 @ 64
*/
reg |= IMC_GIO64ARB_ONEGIO | IMC_GIO64ARB_HPC64;
switch (sys_config.system_subtype) {
default:
case IP22_INDY:
case IP22_CHALLS:
/* XXX is MST mutually exclusive? */
reg |= IMC_GIO64ARB_EXP0RT | IMC_GIO64ARB_EXP1RT;
reg |= IMC_GIO64ARB_EXP0MST | IMC_GIO64ARB_EXP1MST;
/* EISA (VINO, really) can bus-master, is 64-bit */
reg |= IMC_GIO64ARB_EISAMST | IMC_GIO64ARB_EISA64;
break;
case IP22_INDIGO2:
/*
* All Fullhouse boards have a 64-bit HPC2 and pipelined
* EXP0 slot.
*/
reg |= IMC_GIO64ARB_HPCEXP64 | IMC_GIO64ARB_EXP0PIPE;
/*
* The EISA bus is the real thing, and is a 32-bit bus.
*/
reg &= ~IMC_GIO64ARB_EISA64;
if (rev < 2) {
/* EXP0 realtime, EXP1 can master */
reg |= IMC_GIO64ARB_EXP0RT |
IMC_GIO64ARB_EXP1MST;
} else {
/* EXP1 pipelined as well, EISA masters */
reg |= IMC_GIO64ARB_EXP1PIPE |
IMC_GIO64ARB_EISAMST;
}
break;
}
}
imc_write(IMC_GIO64ARB, reg);
imc_arb_value = reg;
memset(&iaa, 0, sizeof(iaa));
iaa.iaa_name = "gio";
iaa.iaa_st = &imcbus_tag;
iaa.iaa_dmat = &imc_bus_dma_tag;
config_found(self, &iaa, imc_print);
#if NEISA > 0
if (have_eisa) {
memset(&eba, 0, sizeof(eba));
eba.eba_busname = "eisa";
eba.eba_iot = &imcbus_eisa_io_tag;
eba.eba_memt = &imcbus_eisa_mem_tag;
eba.eba_dmat = &imc_bus_dma_tag;
eba.eba_ec = NULL;
config_found(self, &eba, imc_print);
}
#endif
/* Register watchdog */
wdog_register(imc_watchdog_cb, self);
}
void i8255_device::set_pc_bit(int bit, int state)
{
// set output latch bit
m_output[PORT_C] &= ~(1 << bit);
m_output[PORT_C] |= state << bit;
switch (group_mode(GROUP_A))
{
case MODE_1:
if (port_mode(PORT_A) == MODE_OUTPUT)
{
switch (bit)
{
case 3: set_intr(PORT_A, state); break;
case 6: set_inte(PORT_A, state); break;
case 7: set_obf(PORT_A, state); break;
default: break;
}
}
else
{
switch (bit)
{
case 3: set_intr(PORT_A, state); break;
case 4: set_inte(PORT_A, state); break;
case 5: set_ibf(PORT_A, state); break;
default: break;
}
}
break;
case MODE_2:
switch (bit)
{
case 3: set_intr(PORT_A, state); break;
case 4: set_inte2(state); break;
case 5: set_ibf(PORT_A, state); break;
case 6: set_inte1(state); break;
case 7: set_obf(PORT_A, state); break;
default: break;
}
break;
}
if (group_mode(GROUP_B) == MODE_1)
{
switch (bit)
{
case 0: set_intr(PORT_B, state); break;
case 1:
if (port_mode(PORT_B) == MODE_OUTPUT)
set_obf(PORT_B, state);
else
set_ibf(PORT_B, state);
break;
case 2: set_inte(PORT_B, state); break;
default: break;
}
}
output_pc();
}
