static CPU_SET_INFO( t11 )
{
t11_state *cpustate = get_safe_token(device);
switch (state)
{
/* --- the following bits of info are set as 64-bit signed integers --- */
case CPUINFO_INT_INPUT_STATE + T11_IRQ0: set_irq_line(cpustate, T11_IRQ0, info->i); break;
case CPUINFO_INT_INPUT_STATE + T11_IRQ1: set_irq_line(cpustate, T11_IRQ1, info->i); break;
case CPUINFO_INT_INPUT_STATE + T11_IRQ2: set_irq_line(cpustate, T11_IRQ2, info->i); break;
case CPUINFO_INT_INPUT_STATE + T11_IRQ3: set_irq_line(cpustate, T11_IRQ3, info->i); break;
case CPUINFO_INT_PC:
case CPUINFO_INT_REGISTER + T11_PC: cpustate->PC = info->i; break;
case CPUINFO_INT_SP:
case CPUINFO_INT_REGISTER + T11_SP: cpustate->SP = info->i; break;
case CPUINFO_INT_REGISTER + T11_PSW: cpustate->PSW = info->i; break;
case CPUINFO_INT_REGISTER + T11_R0: cpustate->REGW(0) = info->i; break;
case CPUINFO_INT_REGISTER + T11_R1: cpustate->REGW(1) = info->i; break;
case CPUINFO_INT_REGISTER + T11_R2: cpustate->REGW(2) = info->i; break;
case CPUINFO_INT_REGISTER + T11_R3: cpustate->REGW(3) = info->i; break;
case CPUINFO_INT_REGISTER + T11_R4: cpustate->REGW(4) = info->i; break;
case CPUINFO_INT_REGISTER + T11_R5: cpustate->REGW(5) = info->i; break;
}
}
static void konami_set_info(UINT32 state, cpuinfo *info)
{
switch (state)
{
/* --- the following bits of info are set as 64-bit signed integers --- */
case CPUINFO_INT_INPUT_STATE + KONAMI_IRQ_LINE: set_irq_line(KONAMI_IRQ_LINE, info->i); break;
case CPUINFO_INT_INPUT_STATE + KONAMI_FIRQ_LINE:set_irq_line(KONAMI_FIRQ_LINE, info->i); break;
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: set_irq_line(INPUT_LINE_NMI, info->i); break;
case CPUINFO_INT_PC:
case CPUINFO_INT_REGISTER + KONAMI_PC: PC = info->i; change_pc(PC); break;
case CPUINFO_INT_SP:
case CPUINFO_INT_REGISTER + KONAMI_S: S = info->i; break;
case CPUINFO_INT_REGISTER + KONAMI_CC: CC = info->i; CHECK_IRQ_LINES; break;
case CPUINFO_INT_REGISTER + KONAMI_U: U = info->i; break;
case CPUINFO_INT_REGISTER + KONAMI_A: A = info->i; break;
case CPUINFO_INT_REGISTER + KONAMI_B: B = info->i; break;
case CPUINFO_INT_REGISTER + KONAMI_X: X = info->i; break;
case CPUINFO_INT_REGISTER + KONAMI_Y: Y = info->i; break;
case CPUINFO_INT_REGISTER + KONAMI_DP: DP = info->i; break;
/* --- the following bits of info are set as pointers to data or functions --- */
case CPUINFO_PTR_KONAMI_SETLINES_CALLBACK: konami.setlines_callback = (void (*)(int))info->f; break;
}
}
static void hd6309_set_info(UINT32 state, cpuinfo *info)
{
switch (state)
{
/* --- the following bits of info are set as 64-bit signed integers --- */
case CPUINFO_INT_INPUT_STATE + HD6309_IRQ_LINE: set_irq_line(HD6309_IRQ_LINE, info->i); break;
case CPUINFO_INT_INPUT_STATE + HD6309_FIRQ_LINE:set_irq_line(HD6309_FIRQ_LINE, info->i); break;
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: set_irq_line(INPUT_LINE_NMI, info->i); break;
case CPUINFO_INT_PC:
case CPUINFO_INT_REGISTER + HD6309_PC: PC = info->i; CHANGE_PC; break;
case CPUINFO_INT_SP:
case CPUINFO_INT_REGISTER + HD6309_S: S = info->i; break;
case CPUINFO_INT_REGISTER + HD6309_CC: CC = info->i; CHECK_IRQ_LINES(); break;
case CPUINFO_INT_REGISTER + HD6309_MD: MD = info->i; UpdateState(); break;
case CPUINFO_INT_REGISTER + HD6309_U: U = info->i; break;
case CPUINFO_INT_REGISTER + HD6309_A: A = info->i; break;
case CPUINFO_INT_REGISTER + HD6309_B: B = info->i; break;
case CPUINFO_INT_REGISTER + HD6309_E: E = info->i; break;
case CPUINFO_INT_REGISTER + HD6309_F: F = info->i; break;
case CPUINFO_INT_REGISTER + HD6309_X: X = info->i; break;
case CPUINFO_INT_REGISTER + HD6309_Y: Y = info->i; break;
case CPUINFO_INT_REGISTER + HD6309_V: V = info->i; break;
case CPUINFO_INT_REGISTER + HD6309_DP: DP = info->i; break;
}
}
static CPU_SET_INFO( nec )
{
nec_state_t *nec_state = get_safe_token(device);
switch (state)
{
/* --- the following bits of info are set as 64-bit signed integers --- */
case CPUINFO_INT_INPUT_STATE + 0: set_irq_line(nec_state, 0, info->i); break;
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: set_irq_line(nec_state, INPUT_LINE_NMI, info->i); break;
case CPUINFO_INT_INPUT_STATE + NEC_INPUT_LINE_POLL: set_irq_line(nec_state, NEC_INPUT_LINE_POLL, info->i); break;
case CPUINFO_INT_PC:
case CPUINFO_INT_REGISTER + NEC_PC:
if( info->i - (Sreg(PS)<<4) < 0x10000 )
{
nec_state->ip = info->i - (Sreg(PS)<<4);
}
else
{
Sreg(PS) = info->i >> 4;
nec_state->ip = info->i & 0x0000f;
}
break;
case CPUINFO_INT_REGISTER + NEC_IP: nec_state->ip = info->i; break;
case CPUINFO_INT_SP:
if( info->i - (Sreg(SS)<<4) < 0x10000 )
{
Wreg(SP) = info->i - (Sreg(SS)<<4);
}
else
{
Sreg(SS) = info->i >> 4;
Wreg(SP) = info->i & 0x0000f;
}
break;
case CPUINFO_INT_REGISTER + NEC_SP: Wreg(SP) = info->i; break;
case CPUINFO_INT_REGISTER + NEC_FLAGS: ExpandFlags(info->i); break;
case CPUINFO_INT_REGISTER + NEC_AW: Wreg(AW) = info->i; break;
case CPUINFO_INT_REGISTER + NEC_CW: Wreg(CW) = info->i; break;
case CPUINFO_INT_REGISTER + NEC_DW: Wreg(DW) = info->i; break;
case CPUINFO_INT_REGISTER + NEC_BW: Wreg(BW) = info->i; break;
case CPUINFO_INT_REGISTER + NEC_BP: Wreg(BP) = info->i; break;
case CPUINFO_INT_REGISTER + NEC_IX: Wreg(IX) = info->i; break;
case CPUINFO_INT_REGISTER + NEC_IY: Wreg(IY) = info->i; break;
case CPUINFO_INT_REGISTER + NEC_ES: Sreg(DS1) = info->i; break;
case CPUINFO_INT_REGISTER + NEC_CS: Sreg(PS) = info->i; break;
case CPUINFO_INT_REGISTER + NEC_SS: Sreg(SS) = info->i; break;
case CPUINFO_INT_REGISTER + NEC_DS: Sreg(DS0) = info->i; break;
}
}
static CPU_SET_INFO( m6809 )
{
m68_state_t *m68_state = get_safe_token(device);
switch (state)
{
/* --- the following bits of info are set as 64-bit signed integers --- */
case CPUINFO_INT_INPUT_STATE + M6809_IRQ_LINE:
set_irq_line(m68_state, M6809_IRQ_LINE, info->i);
break;
case CPUINFO_INT_INPUT_STATE + M6809_FIRQ_LINE:
set_irq_line(m68_state, M6809_FIRQ_LINE, info->i);
break;
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI:
set_irq_line(m68_state, INPUT_LINE_NMI, info->i);
break;
case CPUINFO_INT_PC:
case CPUINFO_INT_REGISTER + M6809_PC:
PC = info->i;
break;
case CPUINFO_INT_SP:
case CPUINFO_INT_REGISTER + M6809_S:
S = info->i;
break;
case CPUINFO_INT_REGISTER + M6809_CC:
CC = info->i;
check_irq_lines(m68_state);
break;
case CPUINFO_INT_REGISTER + M6809_U:
U = info->i;
break;
case CPUINFO_INT_REGISTER + M6809_A:
A = info->i;
break;
case CPUINFO_INT_REGISTER + M6809_B:
B = info->i;
break;
case CPUINFO_INT_REGISTER + M6809_X:
X = info->i;
break;
case CPUINFO_INT_REGISTER + M6809_Y:
Y = info->i;
break;
case CPUINFO_INT_REGISTER + M6809_DP:
DP = info->i;
break;
}
}
void nes_h3001_device::write_h(offs_t offset, uint8_t data)
{
LOG_MMC(("h3001 write_h, offset %04x, data: %02x\n", offset, data));
switch (offset & 0x7fff)
{
case 0x0000:
prg8_89(data);
break;
case 0x1001:
set_nt_mirroring(BIT(data, 7) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
break;
case 0x1003:
m_irq_enable = data & 0x80;
set_irq_line(CLEAR_LINE);
break;
case 0x1004:
m_irq_count = m_irq_count_latch;
set_irq_line(CLEAR_LINE);
break;
case 0x1005:
m_irq_count_latch = (m_irq_count_latch & 0x00ff) | (data << 8);
break;
case 0x1006:
m_irq_count_latch = (m_irq_count_latch & 0xff00) | data;
break;
case 0x2000:
prg8_ab(data);
break;
case 0x3000: case 0x3001: case 0x3002: case 0x3003:
case 0x3004: case 0x3005: case 0x3006: case 0x3007:
chr1_x(offset & 0x07, data, CHRROM);
break;
case 0x4000:
prg8_cd(data);
break;
default:
break;
}
}
void m6809_base_device::execute_set_input(int inputnum, int state)
{
switch(inputnum)
{
case M6809_FIRQ_LINE:
set_irq_line(M6809_FIRQ_LINE, state);
break;
case M6809_IRQ_LINE:
set_irq_line(M6809_IRQ_LINE, state);
break;
case INPUT_LINE_NMI:
set_irq_line(INPUT_LINE_NMI, state);
break;
}
}
/***************************************************************************
pcfx.c
Driver file to handle emulation of the NEC PC-FX.
***************************************************************************/
#include "emu.h"
#include "cpu/v810/v810.h"
#include "video/huc6261.h"
#include "video/huc6270.h"
#include "video/huc6272.h"
struct pcfx_pad_t
{
UINT8 ctrl[2];
UINT8 status[2];
UINT32 latch[2];
};
class pcfx_state : public driver_device
{
public:
enum
{
TIMER_PAD_FUNC
};
pcfx_state(const machine_config &mconfig, device_type type, std::string tag)
: driver_device(mconfig, type, tag),
m_maincpu(*this, "maincpu"),
m_huc6261(*this, "huc6261") { }
required_device<cpu_device> m_maincpu;
required_device<huc6261_device> m_huc6261;
virtual void machine_reset() override;
UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
// Interrupt controller (component unknown)
UINT16 m_irq_mask;
UINT16 m_irq_pending;
UINT8 m_irq_priority[8];
pcfx_pad_t m_pad;
DECLARE_READ16_MEMBER( irq_read );
DECLARE_WRITE16_MEMBER( irq_write );
DECLARE_READ16_MEMBER( pad_r );
DECLARE_WRITE16_MEMBER( pad_w );
DECLARE_READ8_MEMBER( extio_r );
DECLARE_WRITE8_MEMBER( extio_w );
inline void check_irqs();
inline void set_irq_line(int line, int state);
DECLARE_WRITE_LINE_MEMBER( irq8_w );
DECLARE_WRITE_LINE_MEMBER( irq9_w );
DECLARE_WRITE_LINE_MEMBER( irq10_w );
DECLARE_WRITE_LINE_MEMBER( irq11_w );
DECLARE_WRITE_LINE_MEMBER( irq12_w );
DECLARE_WRITE_LINE_MEMBER( irq13_w );
DECLARE_WRITE_LINE_MEMBER( irq14_w );
DECLARE_WRITE_LINE_MEMBER( irq15_w );
TIMER_CALLBACK_MEMBER(pad_func);
protected:
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) override;
};
READ8_MEMBER(pcfx_state::extio_r)
{
address_space &io_space = m_maincpu->space(AS_IO);
return io_space.read_byte(offset);
}
WRITE8_MEMBER(pcfx_state::extio_w)
{
address_space &io_space = m_maincpu->space(AS_IO);
io_space.write_byte(offset, data);
}
static ADDRESS_MAP_START( pcfx_mem, AS_PROGRAM, 32, pcfx_state )
AM_RANGE( 0x00000000, 0x001FFFFF ) AM_RAM /* RAM */
// AM_RANGE( 0x80000000, 0x807FFFFF ) AM_READWRITE8(extio_r,extio_w,0xffffffff) /* EXTIO */
AM_RANGE( 0xE0000000, 0xE7FFFFFF ) AM_NOP /* BackUp RAM */
AM_RANGE( 0xE8000000, 0xE9FFFFFF ) AM_NOP /* Extended BackUp RAM */
AM_RANGE( 0xF8000000, 0xF8000007 ) AM_NOP /* PIO */
AM_RANGE( 0xFFF00000, 0xFFFFFFFF ) AM_ROMBANK("bank1") /* ROM */
ADDRESS_MAP_END
READ16_MEMBER( pcfx_state::pad_r )
{
UINT16 res;
UINT8 port_type = ((offset<<1) & 0x80) >> 7;
if(((offset<<1) & 0x40) == 0)
{
// status
/*
---- x---
---- ---x incoming data state (0=available)
*/
res = m_pad.status[port_type];
//printf("STATUS %d\n",port_type);
}
else
{
// received data
//printf("RX %d\n",port_type);
res = m_pad.latch[port_type] >> (((offset<<1) & 2) ? 16 : 0);
if(((offset<<1) & 0x02) == 0)
{
m_pad.status[port_type] &= ~8; // clear latch on LSB read according to docs
set_irq_line(11, 0);
}
}
return res;
}
void hd64610_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
{
switch (id)
{
case TIMER_UPDATE_COUNTER:
if(m_hline_state || (m_regs[REG_CRB] & CRB_S))
{
m_regs[REG_64HZ]++;
if (m_regs[REG_64HZ] & 0x80)
{
// update seconds
advance_seconds();
// set carry flag
m_regs[REG_CRA] |= CRA_CF;
m_regs[REG_64HZ] &= 0x7f;
}
// update 1Hz out
m_out_1hz_func(BIT(m_regs[REG_64HZ], 6));
// update IRQ
check_alarm();
set_irq_line();
}
break;
}
}
void HUC6280::write_signal(int id, uint32_t data, uint32_t mask)
{
if(id == SIG_CPU_BUSREQ) {
busreq = ((data & mask) != 0);
} else {
h6280_Regs *cpustate = (h6280_Regs *)opaque;
set_irq_line(cpustate, id, data);
}
}
static void aica_irq(int irq)
{
if (irq > 0)
{
#if DK_CORE
ARM7_SetFIQ(TRUE);
#else
set_irq_line(ARM7_FIRQ_LINE, 1);
#endif
}
else
{
#if DK_CORE
ARM7_SetFIQ(FALSE);
#else
set_irq_line(ARM7_FIRQ_LINE, 0);
#endif
}
}
void hd64610_device::rtc_clock_updated(int year, int month, int day, int day_of_week, int hour, int minute, int second)
{
write_counter(REG_SECOND, second);
write_counter(REG_MINUTE, minute);
write_counter(REG_HOUR, hour);
write_counter(REG_DAY, day);
write_counter(REG_MONTH, month);
write_counter(REG_YEAR, year);
m_regs[REG_DAY_OF_THE_WEEK] = day_of_week;
check_alarm();
set_irq_line();
}
void via6522_device::set_int(int data)
{
m_ifr |= data;
if (TRACE_VIA)
{
logerror("%s:6522VIA chip %s: IFR = %02X\n", machine().describe_context(), tag(), m_ifr);
}
if (m_ier & m_ifr)
{
m_ifr |= INT_ANY;
set_irq_line(ASSERT_LINE);
}
}
static void t11_set_info(UINT32 state, cpuinfo *info)
{
switch (state)
{
/* --- the following bits of info are set as 64-bit signed integers --- */
case CPUINFO_INT_INPUT_STATE + T11_IRQ0: set_irq_line(T11_IRQ0, info->i); break;
case CPUINFO_INT_INPUT_STATE + T11_IRQ1: set_irq_line(T11_IRQ1, info->i); break;
case CPUINFO_INT_INPUT_STATE + T11_IRQ2: set_irq_line(T11_IRQ2, info->i); break;
case CPUINFO_INT_INPUT_STATE + T11_IRQ3: set_irq_line(T11_IRQ3, info->i); break;
case CPUINFO_INT_PC:
case CPUINFO_INT_REGISTER + T11_PC: PC = info->i; change_pc(PC); break;
case CPUINFO_INT_SP:
case CPUINFO_INT_REGISTER + T11_SP: SP = info->i; break;
case CPUINFO_INT_REGISTER + T11_PSW: PSW = info->i; break;
case CPUINFO_INT_REGISTER + T11_R0: REGW(0) = info->i; break;
case CPUINFO_INT_REGISTER + T11_R1: REGW(1) = info->i; break;
case CPUINFO_INT_REGISTER + T11_R2: REGW(2) = info->i; break;
case CPUINFO_INT_REGISTER + T11_R3: REGW(3) = info->i; break;
case CPUINFO_INT_REGISTER + T11_R4: REGW(4) = info->i; break;
case CPUINFO_INT_REGISTER + T11_R5: REGW(5) = info->i; break;
}
}
void nes_tc0190fmc_pal16r4_device::hblank_irq( int scanline, int vblank, int blanked )
{
if (scanline < ppu2c0x_device::BOTTOM_VISIBLE_SCANLINE)
{
int prior_count = m_irq_count;
if (m_irq_count == 0)
m_irq_count = m_irq_count_latch;
else
m_irq_count--;
if (m_irq_enable && !blanked && (m_irq_count == 0) && prior_count)
set_irq_line(ASSERT_LINE);
}
}
static CPU_SET_INFO( konami )
{
konami_state *cpustate = get_safe_token(device);
switch (state)
{
/* --- the following bits of info are set as 64-bit signed integers --- */
case CPUINFO_INT_INPUT_STATE + KONAMI_IRQ_LINE: set_irq_line(cpustate, KONAMI_IRQ_LINE, info->i); break;
case CPUINFO_INT_INPUT_STATE + KONAMI_FIRQ_LINE:set_irq_line(cpustate, KONAMI_FIRQ_LINE, info->i); break;
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: set_irq_line(cpustate, INPUT_LINE_NMI, info->i); break;
case CPUINFO_INT_PC:
case CPUINFO_INT_REGISTER + KONAMI_PC: PC = info->i; break;
case CPUINFO_INT_SP:
case CPUINFO_INT_REGISTER + KONAMI_S: S = info->i; break;
case CPUINFO_INT_REGISTER + KONAMI_CC: CC = info->i; break;
case CPUINFO_INT_REGISTER + KONAMI_U: U = info->i; break;
case CPUINFO_INT_REGISTER + KONAMI_A: A = info->i; break;
case CPUINFO_INT_REGISTER + KONAMI_B: B = info->i; break;
case CPUINFO_INT_REGISTER + KONAMI_X: X = info->i; break;
case CPUINFO_INT_REGISTER + KONAMI_Y: Y = info->i; break;
case CPUINFO_INT_REGISTER + KONAMI_DP: DP = info->i; break;
}
}
static CPU_SET_INFO( lh5801 )
{
lh5801_state *cpustate = get_safe_token(device);
switch (state)
{
/* --- the following bits of info are set as 64-bit signed integers --- */
case CPUINFO_INT_INPUT_STATE + LH5801_LINE_MI: set_irq_line(cpustate, LH5801_LINE_MI, info->i); break;
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: set_irq_line(cpustate, INPUT_LINE_NMI, info->i); break;
case CPUINFO_INT_PC:
case CPUINFO_INT_REGISTER + LH5801_P: P = info->i; break;
case CPUINFO_INT_SP:
case CPUINFO_INT_REGISTER + LH5801_S: S = info->i; break;
case CPUINFO_INT_REGISTER + LH5801_U: U = info->i; break;
case CPUINFO_INT_REGISTER + LH5801_X: X = info->i; break;
case CPUINFO_INT_REGISTER + LH5801_Y: Y = info->i; break;
case CPUINFO_INT_REGISTER + LH5801_T: cpustate->t = info->i; break;
case CPUINFO_INT_REGISTER + LH5801_TM: cpustate->tm = info->i; break;
case CPUINFO_INT_REGISTER + LH5801_BF: cpustate->bf = info->i; break;
case CPUINFO_INT_REGISTER + LH5801_PV: cpustate->pv = info->i; break;
case CPUINFO_INT_REGISTER + LH5801_PU: cpustate->pu = info->i; break;
case CPUINFO_INT_REGISTER + LH5801_DP: cpustate->dp = info->i; break;
}
}
static void m6805_set_info(UINT32 state, cpuinfo *info)
{
switch (state)
{
/* --- the following bits of info are set as 64-bit signed integers --- */
case CPUINFO_INT_INPUT_STATE + M6805_IRQ_LINE: set_irq_line(M6805_IRQ_LINE, info->i); break;
case CPUINFO_INT_REGISTER + M6805_A: A = info->i; break;
case CPUINFO_INT_PC:
case CPUINFO_INT_REGISTER + M6805_PC: PC = info->i; change_pc(PC); break;
case CPUINFO_INT_SP:
case CPUINFO_INT_REGISTER + M6805_S: S = SP_ADJUST(info->i); break;
case CPUINFO_INT_REGISTER + M6805_X: X = info->i; break;
case CPUINFO_INT_REGISTER + M6805_CC: CC = info->i; break;
}
}
static CPU_EXECUTE( h6280 )
{
int in;
h6280_Regs* cpustate = get_safe_token(device);
if ( cpustate->irq_pending == 2 ) {
cpustate->irq_pending--;
}
/* Execute instructions */
do
{
cpustate->ppc = cpustate->pc;
debugger_instruction_hook(device, PCW);
/* Execute 1 instruction */
in=RDOP();
PCW++;
insnh6280[in](cpustate);
if ( cpustate->irq_pending ) {
if ( cpustate->irq_pending == 1 ) {
if ( !(P & _fI) ) {
cpustate->irq_pending--;
CHECK_AND_TAKE_IRQ_LINES;
}
} else {
cpustate->irq_pending--;
}
}
/* Check internal timer */
if(cpustate->timer_status)
{
if(cpustate->timer_value<=0)
{
if ( ! cpustate->irq_pending )
cpustate->irq_pending = 1;
while( cpustate->timer_value <= 0 )
cpustate->timer_value += cpustate->timer_load;
set_irq_line(cpustate, 2,ASSERT_LINE);
}
}
} while (cpustate->ICount > 0);
}
void via6522_device::clear_int(int data)
{
m_ifr = (m_ifr & ~data) & 0x7f;
if (TRACE_VIA)
{
logerror("%s:6522VIA chip %s: IFR = %02X\n", machine().describe_context(), tag(), m_ifr);
}
if (m_ifr & m_ier)
{
m_ifr |= INT_ANY;
}
else
{
set_irq_line(CLEAR_LINE);
}
}
static CPU_SET_INFO( m6805 )
{
m6805_Regs *cpustate = get_safe_token(device);
switch (state)
{
/* --- the following bits of info are set as 64-bit signed integers --- */
case CPUINFO_INT_INPUT_STATE + M6805_IRQ_LINE: set_irq_line(cpustate, M6805_IRQ_LINE, info->i); break;
case CPUINFO_INT_REGISTER + M6805_A: A = info->i; break;
case CPUINFO_INT_PC:
case CPUINFO_INT_REGISTER + M6805_PC: PC = info->i; break;
case CPUINFO_INT_SP:
case CPUINFO_INT_REGISTER + M6805_S: S = SP_ADJUST(info->i); break;
case CPUINFO_INT_REGISTER + M6805_X: X = info->i; break;
case CPUINFO_INT_REGISTER + M6805_CC: CC = info->i; break;
}
}
void nes_h3001_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
{
if (id == TIMER_IRQ)
{
if (m_irq_enable)
{
// 16bit counter, IRQ fired when the counter reaches 0
// after firing, the counter is *not* reloaded and does not wrap
if (m_irq_count > 0)
m_irq_count--;
if (!m_irq_count)
{
set_irq_line(ASSERT_LINE);
m_irq_enable = 0;
}
}
}
}
static void m6805_set_info(UINT32 state, union cpuinfo *info)
{
switch (state)
{
/* --- the following bits of info are set as 64-bit signed integers --- */
case CPUINFO_INT_INPUT_STATE + M6805_IRQ_LINE: set_irq_line(M6805_IRQ_LINE, info->i); break;
case CPUINFO_INT_REGISTER + M6805_A: A = info->i; break;
case CPUINFO_INT_PC:
case CPUINFO_INT_REGISTER + M6805_PC: PC = info->i; change_pc(PC); break;
case CPUINFO_INT_SP:
case CPUINFO_INT_REGISTER + M6805_S: S = SP_ADJUST(info->i); break;
case CPUINFO_INT_REGISTER + M6805_X: X = info->i; break;
case CPUINFO_INT_REGISTER + M6805_CC: CC = info->i; break;
/* --- the following bits of info are set as pointers to data or functions --- */
case CPUINFO_PTR_IRQ_CALLBACK: m6805.irq_callback = info->irqcallback; break;
}
}
uint8 APU::read(uint16 addr) {
if(addr == 0x4015) {
uint8 result = 0x00;
result |= pulse[0].length_counter ? 0x01 : 0;
result |= pulse[1].length_counter ? 0x02 : 0;
result |= triangle.length_counter ? 0x04 : 0;
result |= noise.length_counter ? 0x08 : 0;
result |= dmc.length_counter ? 0x10 : 0;
result |= frame.irq_pending ? 0x40 : 0;
result |= dmc.irq_pending ? 0x80 : 0;
frame.irq_pending = false;
set_irq_line();
return result;
}
return cpu.mdr();
}
void APU::reset() {
Processor::create(APU::Main, 21477272);
pulse[0].reset();
pulse[1].reset();
triangle.reset();
noise.reset();
dmc.reset();
frame.irq_pending = 0;
frame.mode = 0;
frame.counter = 0;
frame.divider = 1;
enabled_channels = 0;
cartridge_sample = 0;
set_irq_line();
}
static void h6280_set_info(UINT32 state, union cpuinfo *info)
{
switch (state)
{
/* --- the following bits of info are set as 64-bit signed integers --- */
case CPUINFO_INT_INPUT_STATE + 0: set_irq_line(0, info->i); break;
case CPUINFO_INT_INPUT_STATE + 1: set_irq_line(1, info->i); break;
case CPUINFO_INT_INPUT_STATE + 2: set_irq_line(2, info->i); break;
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI:set_irq_line(INPUT_LINE_NMI, info->i); break;
case CPUINFO_INT_PC:
case CPUINFO_INT_REGISTER + H6280_PC: PCW = info->i; break;
case CPUINFO_INT_SP:
case CPUINFO_INT_REGISTER + H6280_S: S = info->i; break;
case CPUINFO_INT_REGISTER + H6280_P: P = info->i; break;
case CPUINFO_INT_REGISTER + H6280_A: A = info->i; break;
case CPUINFO_INT_REGISTER + H6280_X: X = info->i; break;
case CPUINFO_INT_REGISTER + H6280_Y: Y = info->i; break;
case CPUINFO_INT_REGISTER + H6280_IRQ_MASK: h6280.irq_mask = info->i; CHECK_IRQ_LINES; break;
case CPUINFO_INT_REGISTER + H6280_TIMER_STATE: h6280.timer_status = info->i; break;
case CPUINFO_INT_REGISTER + H6280_NMI_STATE: set_irq_line( INPUT_LINE_NMI, info->i ); break;
case CPUINFO_INT_REGISTER + H6280_IRQ1_STATE: set_irq_line( 0, info->i ); break;
case CPUINFO_INT_REGISTER + H6280_IRQ2_STATE: set_irq_line( 1, info->i ); break;
case CPUINFO_INT_REGISTER + H6280_IRQT_STATE: set_irq_line( 2, info->i ); break;
#ifdef MAME_DEBUG
case CPUINFO_INT_REGISTER + H6280_M1: h6280.mmr[0] = info->i; break;
case CPUINFO_INT_REGISTER + H6280_M2: h6280.mmr[1] = info->i; break;
case CPUINFO_INT_REGISTER + H6280_M3: h6280.mmr[2] = info->i; break;
case CPUINFO_INT_REGISTER + H6280_M4: h6280.mmr[3] = info->i; break;
case CPUINFO_INT_REGISTER + H6280_M5: h6280.mmr[4] = info->i; break;
case CPUINFO_INT_REGISTER + H6280_M6: h6280.mmr[5] = info->i; break;
case CPUINFO_INT_REGISTER + H6280_M7: h6280.mmr[6] = info->i; break;
case CPUINFO_INT_REGISTER + H6280_M8: h6280.mmr[7] = info->i; break;
#endif
/* --- the following bits of info are set as pointers to data or functions --- */
case CPUINFO_PTR_IRQ_CALLBACK: h6280.irq_callback = info->irqcallback; break;
}
}
static CPU_SET_INFO( h6280 )
{
h6280_Regs* cpustate = get_safe_token(device);
switch (state)
{
/* --- the following bits of info are set as 64-bit signed integers --- */
case CPUINFO_INT_INPUT_STATE + 0: set_irq_line(cpustate, 0, info->i); break;
case CPUINFO_INT_INPUT_STATE + 1: set_irq_line(cpustate, 1, info->i); break;
case CPUINFO_INT_INPUT_STATE + 2: set_irq_line(cpustate, 2, info->i); break;
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: set_irq_line(cpustate, INPUT_LINE_NMI, info->i); break;
case CPUINFO_INT_PC:
case CPUINFO_INT_REGISTER + H6280_PC: PCW = info->i; break;
case CPUINFO_INT_SP:
case CPUINFO_INT_REGISTER + H6280_S: S = info->i; break;
case CPUINFO_INT_REGISTER + H6280_P: P = info->i; break;
case CPUINFO_INT_REGISTER + H6280_A: A = info->i; break;
case CPUINFO_INT_REGISTER + H6280_X: X = info->i; break;
case CPUINFO_INT_REGISTER + H6280_Y: Y = info->i; break;
case CPUINFO_INT_REGISTER + H6280_IRQ_MASK: cpustate->irq_mask = info->i; CHECK_IRQ_LINES; break;
case CPUINFO_INT_REGISTER + H6280_TIMER_STATE: cpustate->timer_status = info->i; break;
case CPUINFO_INT_REGISTER + H6280_NMI_STATE: set_irq_line( cpustate, INPUT_LINE_NMI, info->i ); break;
case CPUINFO_INT_REGISTER + H6280_IRQ1_STATE: set_irq_line( cpustate, 0, info->i ); break;
case CPUINFO_INT_REGISTER + H6280_IRQ2_STATE: set_irq_line( cpustate, 1, info->i ); break;
case CPUINFO_INT_REGISTER + H6280_IRQT_STATE: set_irq_line( cpustate, 2, info->i ); break;
case CPUINFO_INT_REGISTER + H6280_M1: cpustate->mmr[0] = info->i; break;
case CPUINFO_INT_REGISTER + H6280_M2: cpustate->mmr[1] = info->i; break;
case CPUINFO_INT_REGISTER + H6280_M3: cpustate->mmr[2] = info->i; break;
case CPUINFO_INT_REGISTER + H6280_M4: cpustate->mmr[3] = info->i; break;
case CPUINFO_INT_REGISTER + H6280_M5: cpustate->mmr[4] = info->i; break;
case CPUINFO_INT_REGISTER + H6280_M6: cpustate->mmr[5] = info->i; break;
case CPUINFO_INT_REGISTER + H6280_M7: cpustate->mmr[6] = info->i; break;
case CPUINFO_INT_REGISTER + H6280_M8: cpustate->mmr[7] = info->i; break;
}
}
void HUC6280::write_signal(int id, uint32 data, uint32 mask)
{
h6280_Regs *cpustate = (h6280_Regs *)opaque;
set_irq_line(cpustate, id, data);
}
static void arm7_set_info(UINT32 state, cpuinfo *info)
{
switch (state)
{
/* --- the following bits of info are set as 64-bit signed integers --- */
/* interrupt lines/exceptions */
case CPUINFO_INT_INPUT_STATE + ARM7_IRQ_LINE: set_irq_line(ARM7_IRQ_LINE, info->i); break;
case CPUINFO_INT_INPUT_STATE + ARM7_FIRQ_LINE: set_irq_line(ARM7_FIRQ_LINE, info->i); break;
case CPUINFO_INT_INPUT_STATE + ARM7_ABORT_EXCEPTION: set_irq_line(ARM7_ABORT_EXCEPTION, info->i); break;
case CPUINFO_INT_INPUT_STATE + ARM7_ABORT_PREFETCH_EXCEPTION: set_irq_line(ARM7_ABORT_PREFETCH_EXCEPTION, info->i); break;
case CPUINFO_INT_INPUT_STATE + ARM7_UNDEFINE_EXCEPTION: set_irq_line(ARM7_UNDEFINE_EXCEPTION, info->i); break;
/* registers shared by all operating modes */
case CPUINFO_INT_REGISTER + ARM7_R0: ARM7REG( 0) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_R1: ARM7REG( 1) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_R2: ARM7REG( 2) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_R3: ARM7REG( 3) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_R4: ARM7REG( 4) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_R5: ARM7REG( 5) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_R6: ARM7REG( 6) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_R7: ARM7REG( 7) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_R8: ARM7REG( 8) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_R9: ARM7REG( 9) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_R10: ARM7REG(10) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_R11: ARM7REG(11) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_R12: ARM7REG(12) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_R13: ARM7REG(13) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_R14: ARM7REG(14) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_R15: ARM7REG(15) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_CPSR: SET_CPSR(info->i); break;
case CPUINFO_INT_PC:
case CPUINFO_INT_REGISTER + ARM7_PC: R15 = info->i; break;
case CPUINFO_INT_SP: SetRegister(13,info->i); break;
/* FIRQ Mode Shadowed Registers */
case CPUINFO_INT_REGISTER + ARM7_FR8: ARM7REG(eR8_FIQ) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_FR9: ARM7REG(eR9_FIQ) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_FR10: ARM7REG(eR10_FIQ) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_FR11: ARM7REG(eR11_FIQ) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_FR12: ARM7REG(eR12_FIQ) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_FR13: ARM7REG(eR13_FIQ) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_FR14: ARM7REG(eR14_FIQ) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_FSPSR: ARM7REG(eSPSR_FIQ) = info->i; break;
/* IRQ Mode Shadowed Registers */
case CPUINFO_INT_REGISTER + ARM7_IR13: ARM7REG(eR13_IRQ) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_IR14: ARM7REG(eR14_IRQ) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_ISPSR: ARM7REG(eSPSR_IRQ) = info->i; break;
/* Supervisor Mode Shadowed Registers */
case CPUINFO_INT_REGISTER + ARM7_SR13: ARM7REG(eR13_SVC) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_SR14: ARM7REG(eR14_SVC) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_SSPSR: ARM7REG(eSPSR_SVC) = info->i; break;
/* Abort Mode Shadowed Registers */
case CPUINFO_INT_REGISTER + ARM7_AR13: ARM7REG(eR13_ABT) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_AR14: ARM7REG(eR14_ABT) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_ASPSR: ARM7REG(eSPSR_ABT) = info->i; break;
/* Undefined Mode Shadowed Registers */
case CPUINFO_INT_REGISTER + ARM7_UR13: ARM7REG(eR13_UND) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_UR14: ARM7REG(eR14_UND) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_USPSR: ARM7REG(eSPSR_UND) = info->i; break;
}
}
static int h6280_execute(int cycles)
{
int in,lastcycle,deltacycle;
h6280_ICount = cycles;
/* Subtract cycles used for taking an interrupt */
h6280_ICount -= h6280.extra_cycles;
h6280.extra_cycles = 0;
lastcycle = h6280_ICount;
/* Execute instructions */
do
{
h6280.ppc = h6280.pc;
#ifdef MAME_DEBUG
{
if (mame_debug)
{
/* Copy the segmentation registers for debugger to use */
int i;
for (i=0; i<8; i++)
H6280_debug_mmr[i]=h6280.mmr[i];
MAME_Debug();
}
}
#endif
/* Execute 1 instruction */
in=RDOP();
PCW++;
insnh6280[in]();
/* Check internal timer */
if(h6280.timer_status)
{
deltacycle = lastcycle - h6280_ICount;
h6280.timer_value -= deltacycle;
if(h6280.timer_value<=0 && h6280.timer_ack==1)
{
h6280.timer_ack=h6280.timer_status=0;
set_irq_line(2,ASSERT_LINE);
}
}
lastcycle = h6280_ICount;
/* If PC has not changed we are stuck in a tight loop, may as well finish */
if( h6280.pc.d == h6280.ppc.d )
{
if (h6280_ICount > 0) h6280_ICount=0;
h6280.extra_cycles = 0;
return cycles;
}
} while (h6280_ICount > 0);
/* Subtract cycles used for taking an interrupt */
h6280_ICount -= h6280.extra_cycles;
h6280.extra_cycles = 0;
return cycles - h6280_ICount;
}
