/** * wsa_request_irq() - to request/register an interrupt * @wsa_res: pointer to wsa_resource. * @irq: interrupt number. * @handler: interrupt handler function pointer. * @name: interrupt name. * @data: device info. * * Convert physical irq to virtual irq and then * reguest for threaded handler. * * Return: Retuns success/failure. */ int wsa_request_irq(struct wsa_resource *wsa_res, int irq, irq_handler_t handler, const char *name, void *data) { int virq; if (wsa_res == NULL) { pr_err("%s: wsa_res is NULL\n", __func__); return -EINVAL; } virq = phyirq_to_virq(wsa_res, irq); /* * ARM needs us to explicitly flag the IRQ as valid * and will set them noprobe when we do so. */ #if defined(CONFIG_ARM) || defined(CONFIG_ARM64) set_irq_flags(virq, IRQF_VALID); #else set_irq_noprobe(virq); #endif return request_threaded_irq(virq, NULL, handler, IRQF_TRIGGER_RISING, name, data); }
static int __init xen_hvc_init(void) { struct hvc_struct *hp; struct hv_ops *ops; if (!xen_pv_domain()) return -ENODEV; if (xen_initial_domain()) { ops = &dom0_hvc_ops; xencons_irq = bind_virq_to_irq(VIRQ_CONSOLE, 0); } else { if (!xen_start_info->console.domU.evtchn) return -ENODEV; ops = &domU_hvc_ops; xencons_irq = bind_evtchn_to_irq(xen_start_info->console.domU.evtchn); } if (xencons_irq < 0) xencons_irq = 0; /* NO_IRQ */ else set_irq_noprobe(xencons_irq); hp = hvc_alloc(HVC_COOKIE, xencons_irq, ops, 256); if (IS_ERR(hp)) return PTR_ERR(hp); hvc = hp; console_pfn = mfn_to_pfn(xen_start_info->console.domU.mfn); return 0; }
static int pca953x_irq_setup(struct pca953x_chip *chip, const struct i2c_device_id *id) { struct i2c_client *client = chip->client; struct pca953x_platform_data *pdata = client->dev.platform_data; int ret; if (pdata->irq_base && (id->driver_data & PCA953X_INT)) { int lvl; ret = pca953x_read_reg(chip, PCA953X_INPUT, &chip->irq_stat); if (ret) goto out_failed; /* * There is no way to know which GPIO line generated the * interrupt. We have to rely on the previous read for * this purpose. */ chip->irq_stat &= chip->reg_direction; chip->irq_base = pdata->irq_base; mutex_init(&chip->irq_lock); for (lvl = 0; lvl < chip->gpio_chip.ngpio; lvl++) { int irq = lvl + chip->irq_base; set_irq_chip_data(irq, chip); set_irq_chip_and_handler(irq, &pca953x_irq_chip, handle_edge_irq); set_irq_nested_thread(irq, 1); #ifdef CONFIG_ARM set_irq_flags(irq, IRQF_VALID); #else set_irq_noprobe(irq); #endif } ret = request_threaded_irq(client->irq, NULL, pca953x_irq_handler, IRQF_TRIGGER_FALLING | IRQF_ONESHOT, dev_name(&client->dev), chip); if (ret) { dev_err(&client->dev, "failed to request irq %d\n", client->irq); goto out_failed; } chip->gpio_chip.to_irq = pca953x_gpio_to_irq; } return 0; out_failed: chip->irq_base = 0; return ret; }
static inline void activate_irq(int irq) { #ifdef CONFIG_ARM /* ARM requires an extra step to clear IRQ_NOREQUEST, which it * sets on behalf of every irq_chip. Also sets IRQ_NOPROBE. */ set_irq_flags(irq, IRQF_VALID); #else /* same effect on other architectures */ set_irq_noprobe(irq); #endif }
static int max732x_irq_setup(struct max732x_chip *chip, const struct i2c_device_id *id) { struct i2c_client *client = chip->client; struct max732x_platform_data *pdata = client->dev.platform_data; int has_irq = max732x_features[id->driver_data] >> 32; int ret; if (pdata->irq_base && has_irq != INT_NONE) { int lvl; chip->irq_base = pdata->irq_base; chip->irq_features = has_irq; mutex_init(&chip->irq_lock); for (lvl = 0; lvl < chip->gpio_chip.ngpio; lvl++) { int irq = lvl + chip->irq_base; if (!(chip->dir_input & (1 << lvl))) continue; set_irq_chip_data(irq, chip); set_irq_chip_and_handler(irq, &max732x_irq_chip, handle_edge_irq); set_irq_nested_thread(irq, 1); #ifdef CONFIG_ARM set_irq_flags(irq, IRQF_VALID); #else set_irq_noprobe(irq); #endif } ret = request_threaded_irq(client->irq, NULL, max732x_irq_handler, IRQF_TRIGGER_FALLING | IRQF_ONESHOT, dev_name(&client->dev), chip); if (ret) { dev_err(&client->dev, "failed to request irq %d\n", client->irq); goto out_failed; } chip->gpio_chip.to_irq = max732x_gpio_to_irq; } return 0; out_failed: chip->irq_base = 0; return ret; }
static int adp5588_irq_setup(struct adp5588_gpio *dev) { struct i2c_client *client = dev->client; struct adp5588_gpio_platform_data *pdata = client->dev.platform_data; unsigned gpio; int ret; adp5588_gpio_write(client, CFG, ADP5588_AUTO_INC); adp5588_gpio_write(client, INT_STAT, -1); /* status is W1C */ adp5588_gpio_read_intstat(client, dev->irq_stat); /* read to clear */ dev->irq_base = pdata->irq_base; mutex_init(&dev->irq_lock); for (gpio = 0; gpio < dev->gpio_chip.ngpio; gpio++) { int irq = gpio + dev->irq_base; set_irq_chip_data(irq, dev); set_irq_chip_and_handler(irq, &adp5588_irq_chip, handle_level_irq); set_irq_nested_thread(irq, 1); #ifdef CONFIG_ARM /* * ARM needs us to explicitly flag the IRQ as VALID, * once we do so, it will also set the noprobe. */ set_irq_flags(irq, IRQF_VALID); #else set_irq_noprobe(irq); #endif } ret = request_threaded_irq(client->irq, NULL, adp5588_irq_handler, IRQF_TRIGGER_FALLING | IRQF_ONESHOT, dev_name(&client->dev), dev); if (ret) { dev_err(&client->dev, "failed to request irq %d\n", client->irq); goto out; } dev->gpio_chip.to_irq = adp5588_gpio_to_irq; adp5588_gpio_write(client, CFG, ADP5588_AUTO_INC | ADP5588_INT_CFG | ADP5588_GPI_INT); return 0; out: dev->irq_base = 0; return ret; }
int wcd9xxx_request_irq(struct wcd9xxx_core_resource *wcd9xxx_res, int irq, irq_handler_t handler, const char *name, void *data) { int virq; virq = phyirq_to_virq(wcd9xxx_res, irq); #ifdef CONFIG_ARM set_irq_flags(virq, IRQF_VALID); #else set_irq_noprobe(virq); #endif return request_threaded_irq(virq, NULL, handler, IRQF_TRIGGER_RISING, name, data); }
static int tc3589x_irq_init(struct tc3589x *tc3589x) { int base = tc3589x->irq_base; int irq; for (irq = base; irq < base + TC3589x_NR_INTERNAL_IRQS; irq++) { set_irq_chip_data(irq, tc3589x); set_irq_chip_and_handler(irq, &dummy_irq_chip, handle_edge_irq); set_irq_nested_thread(irq, 1); #ifdef CONFIG_ARM set_irq_flags(irq, IRQF_VALID); #else set_irq_noprobe(irq); #endif } return 0; }
void __init init_IRQ(void) { int i; #ifdef CONFIG_KGDB if (kgdb_early_setup) return; #endif for (i = 0; i < NR_IRQS; i++) set_irq_noprobe(i); arch_init_irq(); #ifdef CONFIG_KGDB if (!kgdb_early_setup) kgdb_early_setup = 1; #endif }
int wcd9xxx_request_irq(struct wcd9xxx *wcd9xxx, int irq, irq_handler_t handler, const char *name, void *data) { int virq; virq = phyirq_to_virq(wcd9xxx, irq); /* * ARM needs us to explicitly flag the IRQ as valid * and will set them noprobe when we do so. */ #ifdef CONFIG_ARM set_irq_flags(virq, IRQF_VALID); #else set_irq_noprobe(virq); #endif return request_threaded_irq(virq, NULL, handler, IRQF_TRIGGER_RISING, name, data); }
static int __devinit ezx_pcap_probe(struct spi_device *spi) { struct pcap_platform_data *pdata = spi->dev.platform_data; struct pcap_chip *pcap; int i, adc_irq; int ret = -ENODEV; /* platform data is required */ if (!pdata) goto ret; pcap = kzalloc(sizeof(*pcap), GFP_KERNEL); if (!pcap) { ret = -ENOMEM; goto ret; } mutex_init(&pcap->io_mutex); mutex_init(&pcap->adc_mutex); INIT_WORK(&pcap->isr_work, pcap_isr_work); INIT_WORK(&pcap->msr_work, pcap_msr_work); dev_set_drvdata(&spi->dev, pcap); /* setup spi */ spi->bits_per_word = 32; spi->mode = SPI_MODE_0 | (pdata->config & PCAP_CS_AH ? SPI_CS_HIGH : 0); ret = spi_setup(spi); if (ret) goto free_pcap; pcap->spi = spi; /* setup irq */ pcap->irq_base = pdata->irq_base; pcap->workqueue = create_singlethread_workqueue("pcapd"); if (!pcap->workqueue) { dev_err(&spi->dev, "cant create pcap thread\n"); goto free_pcap; } /* redirect interrupts to AP, except adcdone2 */ if (!(pdata->config & PCAP_SECOND_PORT)) ezx_pcap_write(pcap, PCAP_REG_INT_SEL, (1 << PCAP_IRQ_ADCDONE2)); /* setup irq chip */ for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++) { set_irq_chip_and_handler(i, &pcap_irq_chip, handle_simple_irq); set_irq_chip_data(i, pcap); #ifdef CONFIG_ARM set_irq_flags(i, IRQF_VALID); #else set_irq_noprobe(i); #endif } /* mask/ack all PCAP interrupts */ ezx_pcap_write(pcap, PCAP_REG_MSR, PCAP_MASK_ALL_INTERRUPT); ezx_pcap_write(pcap, PCAP_REG_ISR, PCAP_CLEAR_INTERRUPT_REGISTER); pcap->msr = PCAP_MASK_ALL_INTERRUPT; set_irq_type(spi->irq, IRQ_TYPE_EDGE_RISING); set_irq_data(spi->irq, pcap); set_irq_chained_handler(spi->irq, pcap_irq_handler); set_irq_wake(spi->irq, 1); /* ADC */ adc_irq = pcap_to_irq(pcap, (pdata->config & PCAP_SECOND_PORT) ? PCAP_IRQ_ADCDONE2 : PCAP_IRQ_ADCDONE); ret = request_irq(adc_irq, pcap_adc_irq, 0, "ADC", pcap); if (ret) goto free_irqchip; /* setup subdevs */ for (i = 0; i < pdata->num_subdevs; i++) { ret = pcap_add_subdev(pcap, &pdata->subdevs[i]); if (ret) goto remove_subdevs; } /* board specific quirks */ if (pdata->init) pdata->init(pcap); return 0; remove_subdevs: device_for_each_child(&spi->dev, NULL, pcap_remove_subdev); /* free_adc: */ free_irq(adc_irq, pcap); free_irqchip: for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++) set_irq_chip_and_handler(i, NULL, NULL); /* destroy_workqueue: */ destroy_workqueue(pcap->workqueue); free_pcap: kfree(pcap); ret: return ret; }