static void mali_plat_preheat(void)
{
u32 pre_fs;
u32 clk, pp;
if (get_mali_schel_mode() != MALI_PP_FS_SCALING)
return;
get_mali_rt_clkpp(&clk, &pp);
pre_fs = mali_plat_data.def_clock + 1;
if (clk < pre_fs)
clk = pre_fs;
if (pp < mali_plat_data.sc_mpp)
pp = mali_plat_data.sc_mpp;
set_mali_rt_clkpp(clk, pp, 1);
}
static u32 enable_max_num_cores(void)
{
return set_mali_rt_clkpp(currentStep, pmali_plat->scale_info.maxpp, 0);
}
static u32 enable_pp_cores(u32 val)
{
scalingdbg(2, "meson: enable %d pp cores\n", val);
return set_mali_rt_clkpp(currentStep, val, 0);
}
static u32 disable_one_core(void)
{
scalingdbg(2, "meson: disable one pp, current has %d pp cores\n", num_cores_enabled - 1);
return set_mali_rt_clkpp(currentStep, num_cores_enabled - 1, 0);
}
void revise_mali_rt(void)
{
#ifndef CONFIG_MALI_DVFS
set_mali_rt_clkpp(currentStep, num_cores_enabled, 1);
#endif
}
static u32 enable_pp_cores(u32 val)
{
return set_mali_rt_clkpp(currentStep, val, 0);
}
static u32 disable_one_core(void)
{
return set_mali_rt_clkpp(currentStep, num_cores_enabled - 1, 0);
}
void revise_mali_rt(void)
{
set_mali_rt_clkpp(currentStep, num_cores_enabled, 1);
}