/*
************************************************************************************************************
*
* function
*
* name :
*
* parmeters :
*
* return :
*
* note :
*
*
************************************************************************************************************
*/
int main(void)
{
__s32 dram_size=0;
timer_init();
//serial init
sunxi_serial_init(fes1_head.prvt_head.uart_port, (void *)fes1_head.prvt_head.uart_ctrl, 2);
set_pll();
//enable gpio gate
set_gpio_gate();
//dram init
printf("beign to init dram\n");
#ifdef FPGA_PLATFORM
dram_size = mctl_init((void *)fes1_head.prvt_head.dram_para);
#else
dram_size = init_DRAM(0, (void *)fes1_head.prvt_head.dram_para);
#endif
if (dram_size)
{
note_dram_log(1);
printf("init dram ok\n");
}
else
{
note_dram_log(0);
printf("init dram fail\n");
}
__msdelay(10);
return dram_size;
}
/*
************************************************************************************************************
*
* function
*
* name :
*
* parmeters :
*
* return :
*
* note :
*
*
************************************************************************************************************
*/
int main(void)
{
__s32 dram_size=0;
timer_init();
#ifdef CONFIG_ARCH_SUN9IW1P1
if(readl(CCM_PLL1_C0_CTRL))
{
set_pll();
}
#elif defined(CONFIG_ARCH_SUN8IW6P1)
if(readl(CCMU_PLL_C0CPUX_CTRL_REG))
{
set_pll();
}
#else
set_pll();
#endif
//serial init
sunxi_serial_init(fes1_head.prvt_head.uart_port, (void *)fes1_head.prvt_head.uart_ctrl, 2);
//enable gpio gate
set_gpio_gate();
//dram init
printf("beign to init dram\n");
dram_size = init_DRAM(0, (void *)fes1_head.prvt_head.dram_para);
if (dram_size)
{
note_dram_log(1);
printf("init dram ok\n");
}
else
{
note_dram_log(0);
printf("init dram fail\n");
}
__msdelay(10);
return dram_size;
}
int do_armclk_alter(int argc, char *argv[])
{
int armclk, ret=0;
u32 mdiv, pdiv, sdiv;
armclk = simple_strtoul(argv[1], NULL, 10);
printf("armclk : %dMHz\n", armclk);
if(armclk == 833) {
CLK_DIV0_REG &= ~CLK_DIV0_MASK;
CLK_DIV0_REG = ((1<<APLL_RATIO)|(0<<ARM_RATIO)|(4<<D0_BUS_RATIO)|(1<<PCLKD0_RATIO)|(1<<SECSS_RATIO));
// APLL_CON_REG = set_pll( s5p_apll_table[0] [2], s5p_apll_table[0] [1], s5p_apll_table[0] [3]);
} else {
// CLK_DIV0_REG &= ~CLK_DIV0_MASK;
// CLK_DIV0_REG = ((1<<APLL_RATIO)|(0<<ARM_RATIO)|(3<<D0_BUS_RATIO)|(1<<PCLKD0_RATIO)|(1<<SECSS_RATIO));
APLL_CON_REG = set_pll( s5p_apll_table[1] [2], s5p_apll_table[1] [1], s5p_apll_table[1] [3]);
}
return ret;
}
void system_clock_init(struct mem_timings *mem,
struct arm_clk_ratios *arm_clk_ratio)
{
u32 val, tmp;
/* Turn on the MCT as early as possible. */
exynos_mct->g_tcon |= (1 << 8);
clrbits_le32(&exynos_clock->src_cpu, MUX_APLL_SEL_MASK);
do {
val = readl(&exynos_clock->mux_stat_cpu);
} while ((val | MUX_APLL_SEL_MASK) != val);
clrbits_le32(&exynos_clock->src_core1, MUX_MPLL_SEL_MASK);
do {
val = readl(&exynos_clock->mux_stat_core1);
} while ((val | MUX_MPLL_SEL_MASK) != val);
clrbits_le32(&exynos_clock->src_top2, MUX_CPLL_SEL_MASK);
clrbits_le32(&exynos_clock->src_top2, MUX_EPLL_SEL_MASK);
clrbits_le32(&exynos_clock->src_top2, MUX_VPLL_SEL_MASK);
clrbits_le32(&exynos_clock->src_top2, MUX_GPLL_SEL_MASK);
tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK
| MUX_GPLL_SEL_MASK;
do {
val = readl(&exynos_clock->mux_stat_top2);
} while ((val | tmp) != val);
clrbits_le32(&exynos_clock->src_cdrex, MUX_BPLL_SEL_MASK);
do {
val = readl(&exynos_clock->mux_stat_cdrex);
} while ((val | MUX_BPLL_SEL_MASK) != val);
/* PLL locktime */
writel(APLL_LOCK_VAL, &exynos_clock->apll_lock);
writel(MPLL_LOCK_VAL, &exynos_clock->mpll_lock);
writel(BPLL_LOCK_VAL, &exynos_clock->bpll_lock);
writel(CPLL_LOCK_VAL, &exynos_clock->cpll_lock);
writel(GPLL_LOCK_VAL, &exynos_clock->gpll_lock);
writel(EPLL_LOCK_VAL, &exynos_clock->epll_lock);
writel(VPLL_LOCK_VAL, &exynos_clock->vpll_lock);
writel(CLK_REG_DISABLE, &exynos_clock->pll_div2_sel);
writel(MUX_HPM_SEL_MASK, &exynos_clock->src_cpu);
do {
val = readl(&exynos_clock->mux_stat_cpu);
} while ((val | HPM_SEL_SCLK_MPLL) != val);
val = arm_clk_ratio->arm2_ratio << 28
| arm_clk_ratio->apll_ratio << 24
| arm_clk_ratio->pclk_dbg_ratio << 20
| arm_clk_ratio->atb_ratio << 16
| arm_clk_ratio->periph_ratio << 12
| arm_clk_ratio->acp_ratio << 8
| arm_clk_ratio->cpud_ratio << 4
| arm_clk_ratio->arm_ratio;
writel(val, &exynos_clock->div_cpu0);
do {
val = readl(&exynos_clock->div_stat_cpu0);
} while (0 != val);
writel(CLK_DIV_CPU1_VAL, &exynos_clock->div_cpu1);
do {
val = readl(&exynos_clock->div_stat_cpu1);
} while (0 != val);
/* switch A15 clock source to OSC clock before changing APLL */
clrbits_le32(&exynos_clock->src_cpu, APLL_FOUT);
/* Set APLL */
writel(APLL_CON1_VAL, &exynos_clock->apll_con1);
val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv,
arm_clk_ratio->apll_sdiv);
writel(val, &exynos_clock->apll_con0);
while ((readl(&exynos_clock->apll_con0) & APLL_CON0_LOCKED) == 0)
;
/* now it is safe to switch to APLL */
setbits_le32(&exynos_clock->src_cpu, APLL_FOUT);
/* Set MPLL */
writel(MPLL_CON1_VAL, &exynos_clock->mpll_con1);
val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv);
writel(val, &exynos_clock->mpll_con0);
while ((readl(&exynos_clock->mpll_con0) & MPLL_CON0_LOCKED) == 0)
;
/*
* Configure MUX_MPLL_FOUT to choose the direct clock source
* path and avoid the fixed DIV/2 block to save power
*/
setbits_le32(&exynos_clock->pll_div2_sel, MUX_MPLL_FOUT_SEL);
/* Set BPLL */
if (mem->use_bpll) {
writel(BPLL_CON1_VAL, &exynos_clock->bpll_con1);
val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv);
writel(val, &exynos_clock->bpll_con0);
while ((readl(&exynos_clock->bpll_con0) & BPLL_CON0_LOCKED) == 0)
;
setbits_le32(&exynos_clock->pll_div2_sel, MUX_BPLL_FOUT_SEL);
}
/* Set CPLL */
writel(CPLL_CON1_VAL, &exynos_clock->cpll_con1);
val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv);
writel(val, &exynos_clock->cpll_con0);
while ((readl(&exynos_clock->cpll_con0) & CPLL_CON0_LOCKED) == 0)
;
/* Set GPLL */
writel(GPLL_CON1_VAL, &exynos_clock->gpll_con1);
val = set_pll(mem->gpll_mdiv, mem->gpll_pdiv, mem->gpll_sdiv);
writel(val, &exynos_clock->gpll_con0);
while ((readl(&exynos_clock->gpll_con0) & GPLL_CON0_LOCKED) == 0)
;
/* Set EPLL */
writel(EPLL_CON2_VAL, &exynos_clock->epll_con2);
writel(EPLL_CON1_VAL, &exynos_clock->epll_con1);
val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv);
writel(val, &exynos_clock->epll_con0);
while ((readl(&exynos_clock->epll_con0) & EPLL_CON0_LOCKED) == 0)
;
/* Set VPLL */
writel(VPLL_CON2_VAL, &exynos_clock->vpll_con2);
writel(VPLL_CON1_VAL, &exynos_clock->vpll_con1);
val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv);
writel(val, &exynos_clock->vpll_con0);
while ((readl(&exynos_clock->vpll_con0) & VPLL_CON0_LOCKED) == 0)
;
writel(CLK_SRC_CORE0_VAL, &exynos_clock->src_core0);
writel(CLK_DIV_CORE0_VAL, &exynos_clock->div_core0);
while (readl(&exynos_clock->div_stat_core0) != 0)
;
writel(CLK_DIV_CORE1_VAL, &exynos_clock->div_core1);
while (readl(&exynos_clock->div_stat_core1) != 0)
;
writel(CLK_DIV_SYSRGT_VAL, &exynos_clock->div_sysrgt);
while (readl(&exynos_clock->div_stat_sysrgt) != 0)
;
writel(CLK_DIV_ACP_VAL, &exynos_clock->div_acp);
while (readl(&exynos_clock->div_stat_acp) != 0)
;
writel(CLK_DIV_SYSLFT_VAL, &exynos_clock->div_syslft);
while (readl(&exynos_clock->div_stat_syslft) != 0)
;
writel(CLK_SRC_TOP0_VAL, &exynos_clock->src_top0);
writel(CLK_SRC_TOP1_VAL, &exynos_clock->src_top1);
writel(TOP2_VAL, &exynos_clock->src_top2);
writel(CLK_SRC_TOP3_VAL, &exynos_clock->src_top3);
writel(CLK_DIV_TOP0_VAL, &exynos_clock->div_top0);
while (readl(&exynos_clock->div_stat_top0))
;
writel(CLK_DIV_TOP1_VAL, &exynos_clock->div_top1);
while (readl(&exynos_clock->div_stat_top1))
;
writel(CLK_SRC_LEX_VAL, &exynos_clock->src_lex);
while (1) {
val = readl(&exynos_clock->mux_stat_lex);
if (val == (val | 1))
break;
}
writel(CLK_DIV_LEX_VAL, &exynos_clock->div_lex);
while (readl(&exynos_clock->div_stat_lex))
;
writel(CLK_DIV_R0X_VAL, &exynos_clock->div_r0x);
while (readl(&exynos_clock->div_stat_r0x))
;
writel(CLK_DIV_R0X_VAL, &exynos_clock->div_r0x);
while (readl(&exynos_clock->div_stat_r0x))
;
writel(CLK_DIV_R1X_VAL, &exynos_clock->div_r1x);
while (readl(&exynos_clock->div_stat_r1x))
;
if (mem->use_bpll) {
writel(MUX_BPLL_SEL_MASK | MUX_MCLK_CDREX_SEL |
MUX_MCLK_DPHY_SEL, &exynos_clock->src_cdrex);
} else {
writel(CLK_REG_DISABLE, &exynos_clock->src_cdrex);
}
writel(CLK_DIV_CDREX_VAL, &exynos_clock->div_cdrex);
while (readl(&exynos_clock->div_stat_cdrex))
;
val = readl(&exynos_clock->src_cpu);
val |= CLK_SRC_CPU_VAL;
writel(val, &exynos_clock->src_cpu);
val = readl(&exynos_clock->src_top2);
val |= CLK_SRC_TOP2_VAL;
writel(val, &exynos_clock->src_top2);
val = readl(&exynos_clock->src_core1);
val |= CLK_SRC_CORE1_VAL;
writel(val, &exynos_clock->src_core1);
writel(CLK_SRC_FSYS0_VAL, &exynos_clock->src_fsys);
writel(CLK_DIV_FSYS0_VAL, &exynos_clock->div_fsys0);
while (readl(&exynos_clock->div_stat_fsys0))
;
writel(CLK_REG_DISABLE, &exynos_clock->clkout_cmu_cpu);
writel(CLK_REG_DISABLE, &exynos_clock->clkout_cmu_core);
writel(CLK_REG_DISABLE, &exynos_clock->clkout_cmu_acp);
writel(CLK_REG_DISABLE, &exynos_clock->clkout_cmu_top);
writel(CLK_REG_DISABLE, &exynos_clock->clkout_cmu_lex);
writel(CLK_REG_DISABLE, &exynos_clock->clkout_cmu_r0x);
writel(CLK_REG_DISABLE, &exynos_clock->clkout_cmu_r1x);
writel(CLK_REG_DISABLE, &exynos_clock->clkout_cmu_cdrex);
writel(CLK_SRC_PERIC0_VAL, &exynos_clock->src_peric0);
writel(CLK_DIV_PERIC0_VAL, &exynos_clock->div_peric0);
writel(CLK_SRC_PERIC1_VAL, &exynos_clock->src_peric1);
writel(CLK_DIV_PERIC1_VAL, &exynos_clock->div_peric1);
writel(CLK_DIV_PERIC2_VAL, &exynos_clock->div_peric2);
writel(SCLK_SRC_ISP_VAL, &exynos_clock->sclk_src_isp);
writel(SCLK_DIV_ISP_VAL, &exynos_clock->sclk_div_isp);
writel(CLK_DIV_ISP0_VAL, &exynos_clock->div_isp0);
writel(CLK_DIV_ISP1_VAL, &exynos_clock->div_isp1);
writel(CLK_DIV_ISP2_VAL, &exynos_clock->div_isp2);
/* FIMD1 SRC CLK SELECTION */
writel(CLK_SRC_DISP1_0_VAL, &exynos_clock->src_disp1_0);
val = MMC2_PRE_RATIO_VAL << MMC2_PRE_RATIO_OFFSET
| MMC2_RATIO_VAL << MMC2_RATIO_OFFSET
| MMC3_PRE_RATIO_VAL << MMC3_PRE_RATIO_OFFSET
| MMC3_RATIO_VAL << MMC3_RATIO_OFFSET;
writel(val, &exynos_clock->div_fsys2);
}
void system_clock_init()
{
struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
struct mem_timings *mem;
struct arm_clk_ratios *arm_clk_ratio;
u32 val, tmp;
mem = clock_get_mem_timings();
arm_clk_ratio = get_arm_ratios();
clrbits_le32(&clk->src_cpu, MUX_APLL_SEL_MASK);
do {
val = readl(&clk->mux_stat_cpu);
} while ((val | MUX_APLL_SEL_MASK) != val);
clrbits_le32(&clk->src_core1, MUX_MPLL_SEL_MASK);
do {
val = readl(&clk->mux_stat_core1);
} while ((val | MUX_MPLL_SEL_MASK) != val);
clrbits_le32(&clk->src_core1, MUX_CPLL_SEL_MASK);
clrbits_le32(&clk->src_core1, MUX_EPLL_SEL_MASK);
clrbits_le32(&clk->src_core1, MUX_VPLL_SEL_MASK);
clrbits_le32(&clk->src_core1, MUX_GPLL_SEL_MASK);
tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK
| MUX_GPLL_SEL_MASK;
do {
val = readl(&clk->mux_stat_top2);
} while ((val | tmp) != val);
clrbits_le32(&clk->src_cdrex, MUX_BPLL_SEL_MASK);
do {
val = readl(&clk->mux_stat_cdrex);
} while ((val | MUX_BPLL_SEL_MASK) != val);
/* PLL locktime */
writel(APLL_LOCK_VAL, &clk->apll_lock);
writel(MPLL_LOCK_VAL, &clk->mpll_lock);
writel(BPLL_LOCK_VAL, &clk->bpll_lock);
writel(CPLL_LOCK_VAL, &clk->cpll_lock);
writel(GPLL_LOCK_VAL, &clk->gpll_lock);
writel(EPLL_LOCK_VAL, &clk->epll_lock);
writel(VPLL_LOCK_VAL, &clk->vpll_lock);
writel(CLK_REG_DISABLE, &clk->pll_div2_sel);
writel(MUX_HPM_SEL_MASK, &clk->src_cpu);
do {
val = readl(&clk->mux_stat_cpu);
} while ((val | HPM_SEL_SCLK_MPLL) != val);
val = arm_clk_ratio->arm2_ratio << 28
| arm_clk_ratio->apll_ratio << 24
| arm_clk_ratio->pclk_dbg_ratio << 20
| arm_clk_ratio->atb_ratio << 16
| arm_clk_ratio->periph_ratio << 12
| arm_clk_ratio->acp_ratio << 8
| arm_clk_ratio->cpud_ratio << 4
| arm_clk_ratio->arm_ratio;
writel(val, &clk->div_cpu0);
do {
val = readl(&clk->div_stat_cpu0);
} while (0 != val);
writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1);
do {
val = readl(&clk->div_stat_cpu1);
} while (0 != val);
/* Set APLL */
writel(APLL_CON1_VAL, &clk->apll_con1);
val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv,
arm_clk_ratio->apll_sdiv);
writel(val, &clk->apll_con0);
while (readl(&clk->apll_con0) & APLL_CON0_LOCKED)
;
/* Set MPLL */
writel(MPLL_CON1_VAL, &clk->mpll_con1);
val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv);
writel(val, &clk->mpll_con0);
while (readl(&clk->mpll_con0) & MPLL_CON0_LOCKED)
;
/* Set BPLL */
writel(BPLL_CON1_VAL, &clk->bpll_con1);
val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv);
writel(val, &clk->bpll_con0);
while (readl(&clk->bpll_con0) & BPLL_CON0_LOCKED)
;
/* Set CPLL */
writel(CPLL_CON1_VAL, &clk->cpll_con1);
val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv);
writel(val, &clk->cpll_con0);
while (readl(&clk->cpll_con0) & CPLL_CON0_LOCKED)
;
/* Set GPLL */
writel(GPLL_CON1_VAL, &clk->gpll_con1);
val = set_pll(mem->gpll_mdiv, mem->gpll_pdiv, mem->gpll_sdiv);
writel(val, &clk->gpll_con0);
while (readl(&clk->gpll_con0) & GPLL_CON0_LOCKED)
;
/* Set EPLL */
writel(EPLL_CON2_VAL, &clk->epll_con2);
writel(EPLL_CON1_VAL, &clk->epll_con1);
val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv);
writel(val, &clk->epll_con0);
while (readl(&clk->epll_con0) & EPLL_CON0_LOCKED)
;
/* Set VPLL */
writel(VPLL_CON2_VAL, &clk->vpll_con2);
writel(VPLL_CON1_VAL, &clk->vpll_con1);
val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv);
writel(val, &clk->vpll_con0);
while (readl(&clk->vpll_con0) & VPLL_CON0_LOCKED)
;
writel(CLK_SRC_CORE0_VAL, &clk->src_core0);
writel(CLK_DIV_CORE0_VAL, &clk->div_core0);
while (readl(&clk->div_stat_core0) != 0)
;
writel(CLK_DIV_CORE1_VAL, &clk->div_core1);
while (readl(&clk->div_stat_core1) != 0)
;
writel(CLK_DIV_SYSRGT_VAL, &clk->div_sysrgt);
while (readl(&clk->div_stat_sysrgt) != 0)
;
writel(CLK_DIV_ACP_VAL, &clk->div_acp);
while (readl(&clk->div_stat_acp) != 0)
;
writel(CLK_DIV_SYSLFT_VAL, &clk->div_syslft);
while (readl(&clk->div_stat_syslft) != 0)
;
writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
writel(TOP2_VAL, &clk->src_top2);
writel(CLK_SRC_TOP3_VAL, &clk->src_top3);
writel(CLK_DIV_TOP0_VAL, &clk->div_top0);
while (readl(&clk->div_stat_top0))
;
writel(CLK_DIV_TOP1_VAL, &clk->div_top1);
while (readl(&clk->div_stat_top1))
;
writel(CLK_SRC_LEX_VAL, &clk->src_lex);
while (1) {
val = readl(&clk->mux_stat_lex);
if (val == (val | 1))
break;
}
writel(CLK_DIV_LEX_VAL, &clk->div_lex);
while (readl(&clk->div_stat_lex))
;
writel(CLK_DIV_R0X_VAL, &clk->div_r0x);
while (readl(&clk->div_stat_r0x))
;
writel(CLK_DIV_R0X_VAL, &clk->div_r0x);
while (readl(&clk->div_stat_r0x))
;
writel(CLK_DIV_R1X_VAL, &clk->div_r1x);
while (readl(&clk->div_stat_r1x))
;
writel(CLK_REG_DISABLE, &clk->src_cdrex);
writel(CLK_DIV_CDREX_VAL, &clk->div_cdrex);
while (readl(&clk->div_stat_cdrex))
;
val = readl(&clk->src_cpu);
val |= CLK_SRC_CPU_VAL;
writel(val, &clk->src_cpu);
val = readl(&clk->src_top2);
val |= CLK_SRC_TOP2_VAL;
writel(val, &clk->src_top2);
val = readl(&clk->src_core1);
val |= CLK_SRC_CORE1_VAL;
writel(val, &clk->src_core1);
writel(CLK_SRC_FSYS0_VAL, &clk->src_fsys);
writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0);
while (readl(&clk->div_stat_fsys0))
;
writel(CLK_REG_DISABLE, &clk->clkout_cmu_cpu);
writel(CLK_REG_DISABLE, &clk->clkout_cmu_core);
writel(CLK_REG_DISABLE, &clk->clkout_cmu_acp);
writel(CLK_REG_DISABLE, &clk->clkout_cmu_top);
writel(CLK_REG_DISABLE, &clk->clkout_cmu_lex);
writel(CLK_REG_DISABLE, &clk->clkout_cmu_r0x);
writel(CLK_REG_DISABLE, &clk->clkout_cmu_r1x);
writel(CLK_REG_DISABLE, &clk->clkout_cmu_cdrex);
writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0);
writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0);
writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1);
writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1);
writel(CLK_DIV_PERIC2_VAL, &clk->div_peric2);
writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3);
writel(SCLK_SRC_ISP_VAL, &clk->sclk_src_isp);
writel(SCLK_DIV_ISP_VAL, &clk->sclk_div_isp);
writel(CLK_DIV_ISP0_VAL, &clk->div_isp0);
writel(CLK_DIV_ISP1_VAL, &clk->div_isp1);
writel(CLK_DIV_ISP2_VAL, &clk->div_isp2);
/* FIMD1 SRC CLK SELECTION */
writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp1_0);
val = MMC2_PRE_RATIO_VAL << MMC2_PRE_RATIO_OFFSET
| MMC2_RATIO_VAL << MMC2_RATIO_OFFSET
| MMC3_PRE_RATIO_VAL << MMC3_PRE_RATIO_OFFSET
| MMC3_RATIO_VAL << MMC3_RATIO_OFFSET;
writel(val, &clk->div_fsys2);
}
void sbromsw_entry(void)
{
toc0_private_head_t *toc0 = (toc0_private_head_t *)CONFIG_SBROMSW_BASE;
uint dram_size;
int ret, flag;
timer_init();
set_pll();
sunxi_serial_init(toc0_config->uart_port, toc0_config->uart_ctrl, 2);
printf("try to probe rtc region\n");
flag = rtc_region_probe_fel_flag();
printf("flag=0x%x\n", flag);
if(flag == SUNXI_RUN_EFEX_FLAG)
{
printf("sbromsw_entry sbromsw_probe_fel_flag\n");
rtc_region_clear_fel_flag();
goto __sbromsw_entry_err0;
}
#ifdef CONFIG_BOOT_A15
// printf("toc0_config->boot_cpu=0x%x\n", toc0_config->boot_cpu);
// if(toc0_config->boot_cpu)
// {
// flag = BOOT_A7_FLAG;
// }
// else
// {
// flag = BOOT_A15_FLAG;
// }
/*
boot_cpu 含义
bit0~7 bit8~15
0:不需要保存标志位 1:当前应该切换a15启动
1:通知u-boot保存 0:当前应该切换a7启动
每次从brom读取的boot_cpu只能是0x100或者0
*/
if(flag == BOOT_A15_FLAG)
{
rtc_region_clear_fel_flag();
if(toc0_config->boot_cpu == 0x00)
toc0_config->boot_cpu = 0x101; //a15启动，需要保存标志位
switch_to_a15(toc0_config->pwr_en);
}
else if(flag == BOOT_A7_FLAG)
{
rtc_region_clear_fel_flag();
if(toc0_config->boot_cpu == 0x100) //如果原本是a15启动
toc0_config->boot_cpu = 0x01; //a7启动，需要保存标志位
}
else
{
if(toc0_config->boot_cpu == 0x100)
{
switch_to_a15(toc0_config->pwr_en); //a15启动，不需要保存标志位
}
else
{
toc0_config->boot_cpu = 0x0; //a7启动，不需要保存标志位
}
}
//printf("toc0_config->boot_cpu=0x%x\n", toc0_config->boot_cpu);
#endif
printf("try to setup mmu\n");
//mmu init
mmu_setup();
printf("mmu setup ok\n");
//dram init
printf("try to init dram\n");
dram_size = init_DRAM(0, (void *)toc0_config->dram_para);
if (dram_size)
{
printf("init dram ok, size=%dM\n", dram_size);
}
else
{
printf("init dram fail\n");
goto __sbromsw_entry_err;
}
printf("init heap\n");
create_heap(CONFIG_HEAP_BASE, CONFIG_HEAP_SIZE);
printf("init gic\n");
gic_init();
printf("init flash\n");
ret = sunxi_flash_init(toc0->platform[0] & 0x0f); //初始化外部介质，准备读取TOC1数据
if(ret)
{
printf("sbromsw_entry sunxi_flash_init failed\n");
goto __sbromsw_entry_err;
}
ret = toc1_init(); //TOC1初始化，判断TOC1的头部是否合格
if(ret)
{
printf("sbromsw_entry toc1_init failed\n");
goto __sbromsw_entry_err;
}
ret = sbromsw_toc1_traverse();
if(ret)
{
printf("sbromsw_entry sbromsw_toc1_traverse failed\n");
goto __sbromsw_entry_err;
}
__sbromsw_entry_err:
#ifdef CONFIG_BOOT_A15
if(!(toc0_config->boot_cpu & 0xff00))
{
sbromsw_clear_env();
boot0_jump(SUNXI_FEL_ADDR_IN_SECURE);
}
else
{
rtc_region_set_flag(SUNXI_RUN_EFEX_FLAG);
sbromsw_clear_env();
watchdog_enable();
}
#endif
__sbromsw_entry_err0:
sbromsw_clear_env();
boot0_jump(SUNXI_FEL_ADDR_IN_SECURE);
}
boot2()
{
set_pll();
// pio_op_for_lcd();
arm_setup();
powerdown_usb0(CCMU_REGS_BASE);
cli();
pic_startup0(INTC_REGS_BASE);
// sti();
int i;
printk("boot2 starting.... & hello world :-)\r\n");
// __sclk_coreclk_freq_cfg(CCMU_REGS_BASE, 192000000);
printk("initialize uart module: %d\n",kmsg_uart_setup0(UART0_REGS_BASE));
// kmsg_80020000h_setup();
ccmu_info();
gpio_twi0();
powerup_twi0(CCMU_REGS_BASE);
printk("twic_startup: %d\n", twic_startup(TWIC0_REGS_BASE));
twic_clk_cfg(TWIC0_REGS_BASE, 0, __sclk_apbclk_freq(CCMU_REGS_BASE)); // standard clk mode
printk("axp182: supply_status = %02xh\n", axp182_query_status());
axp182_lcd_open();
// i = nand_startup0();
// if (i) printk("nands are connected, the number of chips(CEs#) = %d.\n", i);
// else printk("cannot detect nand flash chip, error?\n");
DE_LCDC_Init();
printk("disp module startup : %d \n",disp_startup());
kmsg_disp_setup0(0x80030000,0, 1);
key_startup();
i=0;
// while(i<1000) printk("%d\n", i++);
// boo21();
// while(1);
int ret;
__asm__ volatile("swi #7; mov %0, r0":"=r"(ret)::"r0","lr");
printk("syscall: %08x\n",ret);
// 不恢复原状态关闭模块
sti();
extern volatile unsigned keycount;
while(keycount<1000);
// powerdown_lcd(CCMU_REGS_BASE);
kmsg_uart_pulldown0();
powerdown_usb0(CCMU_REGS_BASE);
nand_shutdown0();
pic_shutdown0();
arm_pulldown0();
// 因为usb驱动(和其他东西)已被我们关闭，所以只能这样回fel
gotofel();
return 0;
}
int main(void)
{
int disk;
int stage2ImageNumber;
int status;
/* remove the pending reset again */
writel(0xFFFFFFFF, GPIO_B_CLR_OE);
writel((readl(SYS_CTRL_GPIO_TERSEL_CTRL1) & ~0x4),
SYS_CTRL_GPIO_TERSEL_CTRL1);
writel((readl(SYS_CTRL_GPIO_SECSEL_CTRL1) & ~0x4),
SYS_CTRL_GPIO_SECSEL_CTRL1);
writel((readl(SYS_CTRL_GPIO_PRIMSEL_CTRL1) & ~0x4),
SYS_CTRL_GPIO_PRIMSEL_CTRL1);
ddr_control = 0;
stage2_size = 120000;
stage2ImageNumber = 0;
stage2_ram_addr = 0x48d00000;
header_length = (u32 *) (stage2_ram_addr - 8);
header_crc = (u32 *) (stage2_ram_addr - 4);
// Base the UART divider on the system clock
int baud_divisor_x16 = NOMINAL_SYSCLK / 115200;
if (readl(CONFIG_REGISTER) != readl(START_OF_ROM)) {
/* use FPGA system clock speed. */
baud_divisor_x16 = FPGA_CLK / 115200;
} else {
/* use ASIC nominal system clock. */
baud_divisor_x16 = NOMINAL_SYSCLK / 115200;
}
start_timer();
set_pll();
// Initialise the UART to be used by the CoPro for debug messages
debug_uart = (NS16550_t) UART_2_BASE;
init_NS16550(debug_uart, baud_divisor_x16);
putc_NS16550(debug_uart, 'N');
init_ddr();
putc_NS16550(debug_uart, 'A');
test_memory(stage2_ram_addr); /* sends 'S' after writing */
putc_NS16550(debug_uart, 'O');
/* no need to re-initialise SATA controller just load details. */
if ((readl(BOOT_STATUS0) == 0x01)
|| (readl(BOOT_VERSION) == 0x36303030ul)) {
disk = 0;
} else {
disk = 1;
}
do {
init_sata_hw();
status =
run_sata(stage2_disk_sector[stage2ImageNumber], stage2_size,
(u32 *) header_length, disk);
if (status == 0) {
putstr(debug_uart, "X");
} else {
putstr(debug_uart, "x");
}
if (stage2ImageNumber > 0) {
putstr(debug_uart, "R");
} else {
putstr(debug_uart, "_");
}
putc_NS16550(debug_uart, (char) ('0' + (char) disk));
/* try the backup stage2 on this disk first (first tim round, at least we know
it is working to some extent, go to next disk if this wraps round */
if (++stage2ImageNumber >= numStage2Images) {
stage2ImageNumber = 0;
if (++disk > 1) {
disk = 0;
}
}
} while (!
(status != 0 && *header_length
&& *header_length <= stage2_size
&& *header_crc == crc32(0, (unsigned char *) stage2_ram_addr,
*header_length)));
putstr(debug_uart, "800\r\n");
putstr(debug_uart, build_string);
putc_NS16550(debug_uart, '\r');
putc_NS16550(debug_uart, '\n');
#if (OVERCLOCK_PLL)
putstr(debug_uart, "Overclocking with ");
putstr(debug_uart, ultohex(OVERCLOCK_PLL));
putc_NS16550(debug_uart, ' ');
#endif // OVERCLOCK_PLL
((void (*)(void)) stage2_ram_addr) ();
return 0;
}
static void exynos5420_system_clock_init(void)
{
struct exynos5420_clock *clk =
(struct exynos5420_clock *)samsung_get_base_clock();
struct mem_timings *mem;
struct arm_clk_ratios *arm_clk_ratio;
u32 val;
mem = clock_get_mem_timings();
arm_clk_ratio = get_arm_ratios();
/* PLL locktime */
writel(arm_clk_ratio->apll_pdiv * PLL_LOCK_FACTOR, &clk->apll_lock);
writel(mem->mpll_pdiv * PLL_LOCK_FACTOR, &clk->mpll_lock);
writel(mem->bpll_pdiv * PLL_LOCK_FACTOR, &clk->bpll_lock);
writel(mem->cpll_pdiv * PLL_LOCK_FACTOR, &clk->cpll_lock);
writel(mem->dpll_pdiv * PLL_LOCK_FACTOR, &clk->dpll_lock);
writel(mem->epll_pdiv * PLL_X_LOCK_FACTOR, &clk->epll_lock);
writel(mem->vpll_pdiv * PLL_LOCK_FACTOR, &clk->vpll_lock);
writel(mem->ipll_pdiv * PLL_LOCK_FACTOR, &clk->ipll_lock);
writel(mem->spll_pdiv * PLL_LOCK_FACTOR, &clk->spll_lock);
writel(mem->kpll_pdiv * PLL_LOCK_FACTOR, &clk->kpll_lock);
writel(mem->rpll_pdiv * PLL_X_LOCK_FACTOR, &clk->rpll_lock);
setbits_le32(&clk->src_cpu, MUX_HPM_SEL_MASK);
writel(0, &clk->src_top6);
writel(0, &clk->src_cdrex);
writel(SRC_KFC_HPM_SEL, &clk->src_kfc);
writel(HPM_RATIO, &clk->div_cpu1);
writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0);
/* switch A15 clock source to OSC clock before changing APLL */
clrbits_le32(&clk->src_cpu, APLL_FOUT);
/* Set APLL */
writel(APLL_CON1_VAL, &clk->apll_con1);
val = set_pll(arm_clk_ratio->apll_mdiv,
arm_clk_ratio->apll_pdiv,
arm_clk_ratio->apll_sdiv);
writel(val, &clk->apll_con0);
while ((readl(&clk->apll_con0) & PLL_LOCKED) == 0)
;
/* now it is safe to switch to APLL */
setbits_le32(&clk->src_cpu, APLL_FOUT);
writel(SRC_KFC_HPM_SEL, &clk->src_kfc);
writel(CLK_DIV_KFC_VAL, &clk->div_kfc0);
/* switch A7 clock source to OSC clock before changing KPLL */
clrbits_le32(&clk->src_kfc, KPLL_FOUT);
/* Set KPLL*/
writel(KPLL_CON1_VAL, &clk->kpll_con1);
val = set_pll(mem->kpll_mdiv, mem->kpll_pdiv, mem->kpll_sdiv);
writel(val, &clk->kpll_con0);
while ((readl(&clk->kpll_con0) & PLL_LOCKED) == 0)
;
/* now it is safe to switch to KPLL */
setbits_le32(&clk->src_kfc, KPLL_FOUT);
/* Set MPLL */
writel(MPLL_CON1_VAL, &clk->mpll_con1);
val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv);
writel(val, &clk->mpll_con0);
while ((readl(&clk->mpll_con0) & PLL_LOCKED) == 0)
;
/* Set DPLL */
writel(DPLL_CON1_VAL, &clk->dpll_con1);
val = set_pll(mem->dpll_mdiv, mem->dpll_pdiv, mem->dpll_sdiv);
writel(val, &clk->dpll_con0);
while ((readl(&clk->dpll_con0) & PLL_LOCKED) == 0)
;
/* Set EPLL */
writel(EPLL_CON2_VAL, &clk->epll_con2);
writel(EPLL_CON1_VAL, &clk->epll_con1);
val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv);
writel(val, &clk->epll_con0);
while ((readl(&clk->epll_con0) & PLL_LOCKED) == 0)
;
/* Set CPLL */
writel(CPLL_CON1_VAL, &clk->cpll_con1);
val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv);
writel(val, &clk->cpll_con0);
while ((readl(&clk->cpll_con0) & PLL_LOCKED) == 0)
;
/* Set IPLL */
writel(IPLL_CON1_VAL, &clk->ipll_con1);
val = set_pll(mem->ipll_mdiv, mem->ipll_pdiv, mem->ipll_sdiv);
writel(val, &clk->ipll_con0);
while ((readl(&clk->ipll_con0) & PLL_LOCKED) == 0)
;
/* Set VPLL */
writel(VPLL_CON1_VAL, &clk->vpll_con1);
val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv);
writel(val, &clk->vpll_con0);
while ((readl(&clk->vpll_con0) & PLL_LOCKED) == 0)
;
/* Set BPLL */
writel(BPLL_CON1_VAL, &clk->bpll_con1);
val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv);
writel(val, &clk->bpll_con0);
while ((readl(&clk->bpll_con0) & PLL_LOCKED) == 0)
;
/* Set SPLL */
writel(SPLL_CON1_VAL, &clk->spll_con1);
val = set_pll(mem->spll_mdiv, mem->spll_pdiv, mem->spll_sdiv);
writel(val, &clk->spll_con0);
while ((readl(&clk->spll_con0) & PLL_LOCKED) == 0)
;
/* Set RPLL */
writel(RPLL_CON2_VAL, &clk->rpll_con2);
writel(RPLL_CON1_VAL, &clk->rpll_con1);
val = set_pll(mem->rpll_mdiv, mem->rpll_pdiv, mem->rpll_sdiv);
writel(val, &clk->rpll_con0);
while ((readl(&clk->rpll_con0) & PLL_LOCKED) == 0)
;
writel(CLK_DIV_CDREX0_VAL, &clk->div_cdrex0);
writel(CLK_DIV_CDREX1_VAL, &clk->div_cdrex1);
writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
writel(CLK_SRC_TOP2_VAL, &clk->src_top2);
writel(CLK_SRC_TOP7_VAL, &clk->src_top7);
writel(CLK_DIV_TOP0_VAL, &clk->div_top0);
writel(CLK_DIV_TOP1_VAL, &clk->div_top1);
writel(CLK_DIV_TOP2_VAL, &clk->div_top2);
writel(0, &clk->src_top10);
writel(0, &clk->src_top11);
writel(0, &clk->src_top12);
writel(CLK_SRC_TOP3_VAL, &clk->src_top3);
writel(CLK_SRC_TOP4_VAL, &clk->src_top4);
writel(CLK_SRC_TOP5_VAL, &clk->src_top5);
/* DISP1 BLK CLK SELECTION */
writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp10);
writel(CLK_DIV_DISP1_0_VAL, &clk->div_disp10);
/* AUDIO BLK */
writel(AUDIO0_SEL_EPLL, &clk->src_mau);
writel(DIV_MAU_VAL, &clk->div_mau);
/* FSYS */
writel(CLK_SRC_FSYS0_VAL, &clk->src_fsys);
writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0);
writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1);
writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2);
writel(CLK_SRC_ISP_VAL, &clk->src_isp);
writel(CLK_DIV_ISP0_VAL, &clk->div_isp0);
writel(CLK_DIV_ISP1_VAL, &clk->div_isp1);
writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0);
writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1);
writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0);
writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1);
writel(CLK_DIV_PERIC2_VAL, &clk->div_peric2);
writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3);
writel(CLK_DIV_PERIC4_VAL, &clk->div_peric4);
writel(CLK_DIV_CPERI1_VAL, &clk->div_cperi1);
writel(CLK_DIV2_RATIO, &clk->clkdiv2_ratio);
writel(CLK_DIV4_RATIO, &clk->clkdiv4_ratio);
writel(CLK_DIV_G2D, &clk->div_g2d);
writel(CLK_SRC_TOP6_VAL, &clk->src_top6);
writel(CLK_SRC_CDREX_VAL, &clk->src_cdrex);
writel(CLK_SRC_KFC_VAL, &clk->src_kfc);
}
void cpu_init_s(void)
{
timer_init();
set_pll();
}
/*
************************************************************************************************************
*
* function
*
* 函数名称：
*
* 参数列表：
*
* 返回值 ：
*
* 说明 ：
*
*
************************************************************************************************************
*/
void cpu_init_s(void)
{
set_pll();
}
