static struct reg_pair_t *mxl5007t_calc_init_regs(struct mxl5007t_state *state, enum mxl5007t_mode mode) { struct mxl5007t_config *cfg = state->config; memcpy(&state->tab_init, &init_tab, sizeof(init_tab)); memcpy(&state->tab_init_cable, &init_tab_cable, sizeof(init_tab_cable)); mxl5007t_set_mode_bits(state, mode, cfg->if_diff_out_level); mxl5007t_set_if_freq_bits(state, cfg->if_freq_hz, cfg->invert_if); mxl5007t_set_xtal_freq_bits(state, cfg->xtal_freq_hz); set_reg_bits(state->tab_init, 0x10, 0x40, cfg->loop_thru_enable << 6); set_reg_bits(state->tab_init, 0xd8, 0x08, cfg->clk_out_enable << 3); set_reg_bits(state->tab_init, 0x10, 0x07, cfg->clk_out_amp); /* set IDAC to automatic mode control by AGC */ set_reg_bits(state->tab_init, 0x12, 0x80, 0x00); if (mode >= MxL_MODE_CABLE_DIGITAL) { copy_reg_bits(state->tab_init, state->tab_init_cable); return state->tab_init_cable; } else return state->tab_init; }
static void mxl5007t_set_if_freq_bits(struct mxl5007t_state *state, enum mxl5007t_if_freq if_freq, int invert_if) { u8 val; switch (if_freq) { case MxL_IF_4_MHZ: val = 0x00; break; case MxL_IF_4_5_MHZ: val = 0x02; break; case MxL_IF_4_57_MHZ: val = 0x03; break; case MxL_IF_5_MHZ: val = 0x04; break; case MxL_IF_5_38_MHZ: val = 0x05; break; case MxL_IF_6_MHZ: val = 0x06; break; case MxL_IF_6_28_MHZ: val = 0x07; break; case MxL_IF_9_1915_MHZ: val = 0x08; break; case MxL_IF_35_25_MHZ: val = 0x09; break; case MxL_IF_36_15_MHZ: val = 0x0a; break; case MxL_IF_44_MHZ: val = 0x0b; break; default: mxl_fail(-EINVAL); return; } set_reg_bits(state->tab_init, 0x02, 0x0f, val); /* set inverted IF or normal IF */ set_reg_bits(state->tab_init, 0x02, 0x10, invert_if ? 0x10 : 0x00); return; }
static void mxl5007t_set_if_freq_bits(struct mxl5007t_state *state, enum mxl5007t_if_freq if_freq, int invert_if) { u8 val; switch (if_freq) { case MxL_IF_4_MHZ: val = 0x00; break; case MxL_IF_4_5_MHZ: val = 0x20; break; case MxL_IF_4_57_MHZ: val = 0x30; break; case MxL_IF_5_MHZ: val = 0x40; break; case MxL_IF_5_38_MHZ: val = 0x50; break; case MxL_IF_6_MHZ: val = 0x60; break; case MxL_IF_6_28_MHZ: val = 0x70; break; case MxL_IF_9_1915_MHZ: val = 0x80; break; case MxL_IF_35_25_MHZ: val = 0x90; break; case MxL_IF_36_15_MHZ: val = 0xa0; break; case MxL_IF_44_MHZ: val = 0xb0; break; default: mxl_fail(-EINVAL); return; } set_reg_bits(state->tab_init, 0x0c, 0xf0, val); /* set inverted IF or normal IF */ set_reg_bits(state->tab_init, 0x0c, 0x08, invert_if ? 0x08 : 0x00); return; }
static void mxl5007t_set_bw_bits(struct mxl5007t_state *state, enum mxl5007t_bw_mhz bw) { u8 val; switch (bw) { case MxL_BW_6MHz: val = 0x15; /* set DIG_MODEINDEX, DIG_MODEINDEX_A, * and DIG_MODEINDEX_CSF */ break; case MxL_BW_7MHz: val = 0x2a; break; case MxL_BW_8MHz: val = 0x3f; break; default: mxl_fail(-EINVAL); return; } set_reg_bits(state->tab_rftune, 0x0c, 0x3f, val); return; }
static void mxl5007t_set_xtal_freq_bits(struct mxl5007t_state *state, enum mxl5007t_xtal_freq xtal_freq) { u8 val; switch (xtal_freq) { case MxL_XTAL_16_MHZ: val = 0x00; /* select xtal freq & Ref Freq */ break; case MxL_XTAL_20_MHZ: val = 0x11; break; case MxL_XTAL_20_25_MHZ: val = 0x22; break; case MxL_XTAL_20_48_MHZ: val = 0x33; break; case MxL_XTAL_24_MHZ: val = 0x44; break; case MxL_XTAL_25_MHZ: val = 0x55; break; case MxL_XTAL_25_14_MHZ: val = 0x66; break; case MxL_XTAL_27_MHZ: val = 0x77; break; case MxL_XTAL_28_8_MHZ: val = 0x88; break; case MxL_XTAL_32_MHZ: val = 0x99; break; case MxL_XTAL_40_MHZ: val = 0xaa; break; case MxL_XTAL_44_MHZ: val = 0xbb; break; case MxL_XTAL_48_MHZ: val = 0xcc; break; case MxL_XTAL_49_3811_MHZ: val = 0xdd; break; default: mxl_fail(-EINVAL); return; } set_reg_bits(state->tab_init, 0x0b, 0xff, val); return; }
static struct reg_pair_t *mxl5007t_calc_rf_tune_regs(struct mxl5007t_state *state, u32 rf_freq, enum mxl5007t_bw_mhz bw) { u32 dig_rf_freq = 0; u32 temp; u32 frac_divider = 1000000; unsigned int i; memcpy(&state->tab_rftune, ®_pair_rftune, sizeof(reg_pair_rftune)); mxl5007t_set_bw_bits(state, bw); /* Convert RF frequency into 16 bits => * 10 bit integer (MHz) + 6 bit fraction */ dig_rf_freq = rf_freq / MHz; temp = rf_freq % MHz; for (i = 0; i < 6; i++) { dig_rf_freq <<= 1; frac_divider /= 2; if (temp > frac_divider) { temp -= frac_divider; dig_rf_freq++; } } /* add to have shift center point by 7.8124 kHz */ if (temp > 7812) dig_rf_freq++; set_reg_bits(state->tab_rftune, 0x0d, 0xff, (u8) dig_rf_freq); set_reg_bits(state->tab_rftune, 0x0e, 0xff, (u8)(dig_rf_freq >> 8)); if (rf_freq >= 333000000) set_reg_bits(state->tab_rftune, 0x80, 0x40, 0x40); return state->tab_rftune; }
static void mxl5007t_set_mode_bits(struct mxl5007t_state *state, enum mxl5007t_mode mode, s32 if_diff_out_level) { switch (mode) { case MxL_MODE_ATSC: set_reg_bits(state->tab_init, 0x06, 0x1f, 0x12); break; case MxL_MODE_DVBT: set_reg_bits(state->tab_init, 0x06, 0x1f, 0x11); break; case MxL_MODE_ISDBT: set_reg_bits(state->tab_init, 0x06, 0x1f, 0x10); break; case MxL_MODE_CABLE: set_reg_bits(state->tab_init_cable, 0x09, 0xff, 0xc1); set_reg_bits(state->tab_init_cable, 0x0a, 0xff, 8 - if_diff_out_level); set_reg_bits(state->tab_init_cable, 0x0b, 0xff, 0x17); break; default: mxl_fail(-EINVAL); } return; }
static struct reg_pair_t *mxl5007t_calc_init_regs(struct mxl5007t_state *state, enum mxl5007t_mode mode) { struct mxl5007t_config *cfg = state->config; memcpy(&state->tab_init, &init_tab, sizeof(init_tab)); memcpy(&state->tab_init_cable, &init_tab_cable, sizeof(init_tab_cable)); mxl5007t_set_mode_bits(state, mode, cfg->if_diff_out_level); mxl5007t_set_if_freq_bits(state, cfg->if_freq_hz, cfg->invert_if); mxl5007t_set_xtal_freq_bits(state, cfg->xtal_freq_hz); set_reg_bits(state->tab_init, 0x04, 0x01, cfg->loop_thru_enable); set_reg_bits(state->tab_init, 0x03, 0x08, cfg->clk_out_enable << 3); set_reg_bits(state->tab_init, 0x03, 0x07, cfg->clk_out_amp); if (mode >= MxL_MODE_CABLE) { copy_reg_bits(state->tab_init, state->tab_init_cable); return state->tab_init_cable; } else return state->tab_init; }
static void mxl5007t_set_mode_bits(struct mxl5007t_state *state, enum mxl5007t_mode mode, s32 if_diff_out_level) { switch (mode) { case MxL_MODE_OTA_DVBT_ATSC: set_reg_bits(state->tab_init, 0x32, 0x0f, 0x06); set_reg_bits(state->tab_init, 0x35, 0xff, 0x0e); break; case MxL_MODE_OTA_ISDBT: set_reg_bits(state->tab_init, 0x32, 0x0f, 0x06); set_reg_bits(state->tab_init, 0x35, 0xff, 0x12); break; case MxL_MODE_OTA_NTSC_PAL_GH: set_reg_bits(state->tab_init, 0x16, 0x70, 0x00); set_reg_bits(state->tab_init, 0x32, 0xff, 0x85); break; case MxL_MODE_OTA_PAL_IB: set_reg_bits(state->tab_init, 0x16, 0x70, 0x10); set_reg_bits(state->tab_init, 0x32, 0xff, 0x85); break; case MxL_MODE_OTA_PAL_D_SECAM_KL: set_reg_bits(state->tab_init, 0x16, 0x70, 0x20); set_reg_bits(state->tab_init, 0x32, 0xff, 0x85); break; case MxL_MODE_CABLE_DIGITAL: set_reg_bits(state->tab_init_cable, 0x71, 0xff, 0x01); set_reg_bits(state->tab_init_cable, 0x72, 0xff, 8 - if_diff_out_level); set_reg_bits(state->tab_init_cable, 0x74, 0xff, 0x17); break; case MxL_MODE_CABLE_NTSC_PAL_GH: set_reg_bits(state->tab_init, 0x16, 0x70, 0x00); set_reg_bits(state->tab_init, 0x32, 0xff, 0x85); set_reg_bits(state->tab_init_cable, 0x71, 0xff, 0x01); set_reg_bits(state->tab_init_cable, 0x72, 0xff, 8 - if_diff_out_level); set_reg_bits(state->tab_init_cable, 0x74, 0xff, 0x17); break; case MxL_MODE_CABLE_PAL_IB: set_reg_bits(state->tab_init, 0x16, 0x70, 0x10); set_reg_bits(state->tab_init, 0x32, 0xff, 0x85); set_reg_bits(state->tab_init_cable, 0x71, 0xff, 0x01); set_reg_bits(state->tab_init_cable, 0x72, 0xff, 8 - if_diff_out_level); set_reg_bits(state->tab_init_cable, 0x74, 0xff, 0x17); break; case MxL_MODE_CABLE_PAL_D_SECAM_KL: set_reg_bits(state->tab_init, 0x16, 0x70, 0x20); set_reg_bits(state->tab_init, 0x32, 0xff, 0x85); set_reg_bits(state->tab_init_cable, 0x71, 0xff, 0x01); set_reg_bits(state->tab_init_cable, 0x72, 0xff, 8 - if_diff_out_level); set_reg_bits(state->tab_init_cable, 0x74, 0xff, 0x17); break; case MxL_MODE_CABLE_SCTE40: set_reg_bits(state->tab_init_cable, 0x36, 0xff, 0x08); set_reg_bits(state->tab_init_cable, 0x68, 0xff, 0xbc); set_reg_bits(state->tab_init_cable, 0x71, 0xff, 0x01); set_reg_bits(state->tab_init_cable, 0x72, 0xff, 8 - if_diff_out_level); set_reg_bits(state->tab_init_cable, 0x74, 0xff, 0x17); break; default: mxl_fail(-EINVAL); } return; }
static void mxl5007t_set_xtal_freq_bits(struct mxl5007t_state *state, enum mxl5007t_xtal_freq xtal_freq) { switch (xtal_freq) { case MxL_XTAL_16_MHZ: /* select xtal freq & ref freq */ set_reg_bits(state->tab_init, 0x03, 0xf0, 0x00); set_reg_bits(state->tab_init, 0x05, 0x0f, 0x00); break; case MxL_XTAL_20_MHZ: set_reg_bits(state->tab_init, 0x03, 0xf0, 0x10); set_reg_bits(state->tab_init, 0x05, 0x0f, 0x01); break; case MxL_XTAL_20_25_MHZ: set_reg_bits(state->tab_init, 0x03, 0xf0, 0x20); set_reg_bits(state->tab_init, 0x05, 0x0f, 0x02); break; case MxL_XTAL_20_48_MHZ: set_reg_bits(state->tab_init, 0x03, 0xf0, 0x30); set_reg_bits(state->tab_init, 0x05, 0x0f, 0x03); break; case MxL_XTAL_24_MHZ: set_reg_bits(state->tab_init, 0x03, 0xf0, 0x40); set_reg_bits(state->tab_init, 0x05, 0x0f, 0x04); break; case MxL_XTAL_25_MHZ: set_reg_bits(state->tab_init, 0x03, 0xf0, 0x50); set_reg_bits(state->tab_init, 0x05, 0x0f, 0x05); break; case MxL_XTAL_25_14_MHZ: set_reg_bits(state->tab_init, 0x03, 0xf0, 0x60); set_reg_bits(state->tab_init, 0x05, 0x0f, 0x06); break; case MxL_XTAL_27_MHZ: set_reg_bits(state->tab_init, 0x03, 0xf0, 0x70); set_reg_bits(state->tab_init, 0x05, 0x0f, 0x07); break; case MxL_XTAL_28_8_MHZ: set_reg_bits(state->tab_init, 0x03, 0xf0, 0x80); set_reg_bits(state->tab_init, 0x05, 0x0f, 0x08); break; case MxL_XTAL_32_MHZ: set_reg_bits(state->tab_init, 0x03, 0xf0, 0x90); set_reg_bits(state->tab_init, 0x05, 0x0f, 0x09); break; case MxL_XTAL_40_MHZ: set_reg_bits(state->tab_init, 0x03, 0xf0, 0xa0); set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0a); break; case MxL_XTAL_44_MHZ: set_reg_bits(state->tab_init, 0x03, 0xf0, 0xb0); set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0b); break; case MxL_XTAL_48_MHZ: set_reg_bits(state->tab_init, 0x03, 0xf0, 0xc0); set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0c); break; case MxL_XTAL_49_3811_MHZ: set_reg_bits(state->tab_init, 0x03, 0xf0, 0xd0); set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0d); break; default: mxl_fail(-EINVAL); return; } return; }