コード例 #1
0
ファイル: clocks.c プロジェクト: Aorjoa/bootloader
static void setup_non_essential_dplls(void)
{
	u32 sys_clk_khz, abe_ref_clk;
	u32 sysclk_ind, sd_div, num, den;
	const struct dpll_params *params;

	sysclk_ind = get_sys_clk_index();
	sys_clk_khz = get_sys_clk_freq() / 1000;

	/* IVA */
	clrsetbits_le32(&prcm->cm_bypclk_dpll_iva,
		CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2);

	do_setup_dpll(&prcm->cm_clkmode_dpll_iva,
			&iva_dpll_params_1862mhz[sysclk_ind], DPLL_LOCK);

	/*
	 * USB:
	 * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction
	 * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250)
	 *      - where CLKINP is sys_clk in MHz
	 * Use CLKINP in KHz and adjust the denominator accordingly so
	 * that we have enough accuracy and at the same time no overflow
	 */
	params = &usb_dpll_params_1920mhz[sysclk_ind];
	num = params->m * sys_clk_khz;
	den = (params->n + 1) * 250 * 1000;
	num += den - 1;
	sd_div = num / den;
	clrsetbits_le32(&prcm->cm_clksel_dpll_usb,
			CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK,
			sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT);

	/* Now setup the dpll with the regular function */
	do_setup_dpll(&prcm->cm_clkmode_dpll_usb, params, DPLL_LOCK);

#ifdef CONFIG_SYS_OMAP4_ABE_SYSCK
	params = &abe_dpll_params_sysclk_196608khz[sysclk_ind];
	abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK;
#else
	params = &abe_dpll_params_32k_196608khz;
	abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK;
	/*
	 * We need to enable some additional options to achieve
	 * 196.608MHz from 32768 Hz
	 */
	setbits_le32(&prcm->cm_clkmode_dpll_abe,
			CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK|
			CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK|
			CM_CLKMODE_DPLL_LPMODE_EN_MASK|
			CM_CLKMODE_DPLL_REGM4XEN_MASK);
	/* Spend 4 REFCLK cycles at each stage */
	clrsetbits_le32(&prcm->cm_clkmode_dpll_abe,
			CM_CLKMODE_DPLL_RAMP_RATE_MASK,
			1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT);
#endif

	/* Select the right reference clk */
	clrsetbits_le32(&prcm->cm_abe_pll_ref_clksel,
			CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK,
			abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT);
	/* Lock the dpll */
	do_setup_dpll(&prcm->cm_clkmode_dpll_abe, params, DPLL_LOCK);
}
コード例 #2
0
static void exynos5_usb3_phy_init(struct exynos_usb3_phy *phy)
{
	u32 reg;

	/* enabling usb_drd phy */
	set_usbdrd_phy_ctrl(POWER_USB_DRD_PHY_CTRL_EN);

	/* Reset USB 3.0 PHY */
	writel(0x0, &phy->phy_reg0);

	clrbits_le32(&phy->phy_param0,
			/* Select PHY CLK source */
			PHYPARAM0_REF_USE_PAD |
			/* Set Loss-of-Signal Detector sensitivity */
			PHYPARAM0_REF_LOSLEVEL_MASK);
	setbits_le32(&phy->phy_param0, PHYPARAM0_REF_LOSLEVEL);

	writel(0x0, &phy->phy_resume);

	/*
	 * Setting the Frame length Adj value[6:1] to default 0x20
	 * See xHCI 1.0 spec, 5.2.4
	 */
	setbits_le32(&phy->link_system,
			LINKSYSTEM_XHCI_VERSION_CONTROL |
			LINKSYSTEM_FLADJ(0x20));

	/* Set Tx De-Emphasis level */
	clrbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH_MASK);
	setbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH);

	setbits_le32(&phy->phy_batchg, PHYBATCHG_UTMI_CLKSEL);

	/* PHYTEST POWERDOWN Control */
	clrbits_le32(&phy->phy_test,
			PHYTEST_POWERDOWN_SSP |
			PHYTEST_POWERDOWN_HSP);

	/* UTMI Power Control */
	writel(PHYUTMI_OTGDISABLE, &phy->phy_utmi);

		/* Use core clock from main PLL */
	reg = PHYCLKRST_REFCLKSEL_EXT_REFCLK |
		/* Default 24Mhz crystal clock */
		PHYCLKRST_FSEL(FSEL_CLKSEL_24M) |
		PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF |
		PHYCLKRST_SSC_REFCLKSEL(0x88) |
		/* Force PortReset of PHY */
		PHYCLKRST_PORTRESET |
		/* Digital power supply in normal operating mode */
		PHYCLKRST_RETENABLEN |
		/* Enable ref clock for SS function */
		PHYCLKRST_REF_SSP_EN |
		/* Enable spread spectrum */
		PHYCLKRST_SSC_EN |
		/* Power down HS Bias and PLL blocks in suspend mode */
		PHYCLKRST_COMMONONN;

	writel(reg, &phy->phy_clk_rst);

	/* giving time to Phy clock to settle before resetting */
	udelay(10);

	reg &= ~PHYCLKRST_PORTRESET;
	writel(reg, &phy->phy_clk_rst);
}
コード例 #3
0
ファイル: samsung-i2s.c プロジェクト: DFE/u-boot
/*
 * flushes the i2stx fifo
 *
 * @param i2s_reg	i2s regiter address
 * @param flush		Tx fifo flush command (0x00 - do not flush
 *				0x80 - flush tx fifo)
 */
void i2s_fifo(struct i2s_reg *i2s_reg, unsigned int flush)
{
	/* Flush the FIFO */
	setbits_le32(&i2s_reg->fic, flush);
	clrbits_le32(&i2s_reg->fic, flush);
}
コード例 #4
0
ファイル: m3_skt_v1.c プロジェクト: rofehr/uboot-amlogic
static int  sdio_detect(unsigned port)
{
	setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
	return readl(P_PREG_PAD_GPIO5_I)&(1<<29)?1:0;
}
コード例 #5
0
ファイル: gpio.c プロジェクト: MikeeHawk/coreboot
void gpio_output(gpio_t gpio, int value)
{
	setbits_le32(&gpio_port[gpio.port]->swporta_ddr, 1 << gpio.num);
	clrsetbits_le32(&gpio_port[gpio.port]->swporta_dr, 1 << gpio.num,
							   !!value << gpio.num);
}
コード例 #6
0
/* Unfreeze/Thaw HPS IOs */
void sys_mgr_frzctrl_thaw_req(void)
{
    u32 ioctrl_reg_offset;
    u32 reg_cfg_mask;
    u32 reg_value;
    u32 channel_id;
    unsigned long eosc1_freq;

    /* select software FSM */
    writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW,	&freeze_controller_base->src);

    /* Thaw channel 0 to 2 */
    for (channel_id = 0; channel_id <= 2; channel_id++) {
        ioctrl_reg_offset
            = (u32)(&freeze_controller_base->vioctrl + channel_id);

        /*
         * Assert active low bhniotri signal and
         * de-assert active high csrdone
         */
        reg_cfg_mask
            = SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK
              | SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK;
        setbits_le32(ioctrl_reg_offset,	reg_cfg_mask);

        /*
         * Note: Delay for 20ns at min
         * de-assert active low plniotri and niotri signals
         */
        reg_cfg_mask
            = SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK
              | SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK;
        setbits_le32(ioctrl_reg_offset,	reg_cfg_mask);

        /*
         * Note: Delay for 20ns at min
         * de-assert active low enrnsl signal
         */
        setbits_le32(ioctrl_reg_offset,
                     SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK);

        /* Set global flag to indicate channel is thawed */
        frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_THAWED;
    }

    /* Thaw channel 3 */
    /* de-assert active high reinit signal */
    clrbits_le32(&freeze_controller_base->hioctrl,
                 SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK);

    /*
     * Note: Delay for 40ns at min
     * assert active high pllbiasen signals
     */
    setbits_le32(&freeze_controller_base->hioctrl,
                 SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK);

    /* Delay 1000 intosc cycles. The intosc is based on eosc1. */
    eosc1_freq = cm_get_osc_clk_hz(1) / 1000;	/* kHz */
    udelay(DIV_ROUND_UP(1000000, eosc1_freq));

    /*
     * de-assert active low bhniotri signals,
     * assert active high csrdone and nfrzdrv signal
     */
    reg_value = readl(&freeze_controller_base->hioctrl);
    reg_value = (reg_value
                 | SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK
                 | SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK)
                & ~SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK;
    writel(reg_value, &freeze_controller_base->hioctrl);

    /*
     * Delay 33 intosc
     * Use worst case which is fatest eosc1=50MHz, delay required
     * is 1/50MHz * 33 = 660ns ~= 1us
     */
    udelay(1);

    /* de-assert active low plniotri and niotri signals */
    reg_cfg_mask
        = SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK
          | SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK;

    setbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask);

    /*
     * Note: Delay for 40ns at min
     * de-assert active high frzreg signal
     */
    clrbits_le32(&freeze_controller_base->hioctrl,
                 SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK);

    /*
     * Note: Delay for 40ns at min
     * de-assert active low enrnsl signal
     */
    setbits_le32(&freeze_controller_base->hioctrl,
                 SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK);

    /* Set global flag to indicate channel is thawed */
    frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_THAWED;
}
コード例 #7
0
ファイル: sunxi_display.c プロジェクト: Xilinx/u-boot-xlnx
static int sunxi_hdmi_edid_get_mode(struct ctfb_res_modes *mode)
{
	struct edid1_info edid1;
	struct edid_cea861_info cea681[4];
	struct edid_detailed_timing *t =
		(struct edid_detailed_timing *)edid1.monitor_details.timing;
	struct sunxi_hdmi_reg * const hdmi =
		(struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
	struct sunxi_ccm_reg * const ccm =
		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	int i, r, ext_blocks = 0;

	/* SUNXI_HDMI_CTRL_ENABLE & PAD_CTRL0 are already set by hpd_detect */
	writel(SUNXI_HDMI_PAD_CTRL1 | SUNXI_HDMI_PAD_CTRL1_HALVE,
	       &hdmi->pad_ctrl1);
	writel(SUNXI_HDMI_PLL_CTRL | SUNXI_HDMI_PLL_CTRL_DIV(15),
	       &hdmi->pll_ctrl);
	writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);

	/* Reset i2c controller */
	setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE);
	writel(SUNXI_HMDI_DDC_CTRL_ENABLE |
	       SUNXI_HMDI_DDC_CTRL_SDA_ENABLE |
	       SUNXI_HMDI_DDC_CTRL_SCL_ENABLE |
	       SUNXI_HMDI_DDC_CTRL_RESET, &hdmi->ddc_ctrl);
	if (await_completion(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_RESET, 0))
		return -EIO;

	writel(SUNXI_HDMI_DDC_CLOCK, &hdmi->ddc_clock);
#ifndef CONFIG_MACH_SUN6I
	writel(SUNXI_HMDI_DDC_LINE_CTRL_SDA_ENABLE |
	       SUNXI_HMDI_DDC_LINE_CTRL_SCL_ENABLE, &hdmi->ddc_line_ctrl);
#endif

	r = sunxi_hdmi_edid_get_block(0, (u8 *)&edid1);
	if (r == 0) {
		r = edid_check_info(&edid1);
		if (r) {
			printf("EDID: invalid EDID data\n");
			r = -EINVAL;
		}
	}
	if (r == 0) {
		ext_blocks = edid1.extension_flag;
		if (ext_blocks > 4)
			ext_blocks = 4;
		for (i = 0; i < ext_blocks; i++) {
			if (sunxi_hdmi_edid_get_block(1 + i,
						(u8 *)&cea681[i]) != 0) {
				ext_blocks = i;
				break;
			}
		}
	}

	/* Disable DDC engine, no longer needed */
	clrbits_le32(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_ENABLE);
	clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE);

	if (r)
		return r;

	/* We want version 1.3 or 1.2 with detailed timing info */
	if (edid1.version != 1 || (edid1.revision < 3 &&
			!EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(edid1))) {
		printf("EDID: unsupported version %d.%d\n",
		       edid1.version, edid1.revision);
		return -EINVAL;
	}

	/* Take the first usable detailed timing */
	for (i = 0; i < 4; i++, t++) {
		r = video_edid_dtd_to_ctfb_res_modes(t, mode);
		if (r == 0)
			break;
	}
	if (i == 4) {
		printf("EDID: no usable detailed timing found\n");
		return -ENOENT;
	}

	/* Check for basic audio support, if found enable hdmi output */
	sunxi_display.monitor = sunxi_monitor_dvi;
	for (i = 0; i < ext_blocks; i++) {
		if (cea681[i].extension_tag != EDID_CEA861_EXTENSION_TAG ||
		    cea681[i].revision < 2)
			continue;

		if (EDID_CEA861_SUPPORTS_BASIC_AUDIO(cea681[i]))
			sunxi_display.monitor = sunxi_monitor_hdmi;
	}

	return 0;
}
コード例 #8
0
ファイル: scan_manager.c プロジェクト: Adrizcorp/ARM_SOC_FPGA
/*
 * scan_mgr_io_scan_chain_prg
 * Program HPS IO Scan Chain
 */
unsigned long
scan_mgr_io_scan_chain_prg(
	IOScanChainSelect io_scan_chain_id,
	uint32_t io_scan_chain_len_in_bits,
	const unsigned long *iocsr_scan_chain)
{

	uint16_t tdi_tdo_header;
	uint32_t io_program_iter;
	uint32_t io_scan_chain_data_residual;
	uint32_t residual;
	uint32_t i;
	uint32_t index = 0;

	/*
	 * Check if IO bank is in frozen state before proceed to program IO
	 * scan chain.
	 * Note: IO scan chain ID is 1:1 mapping to freeze channel ID
	 */
	DEBUG_MEMORY
	 if (sys_mgr_frzctrl_frzchn_is_frozen(io_scan_chain_id)) {

		/* De-assert reinit if the IO scan chain is intended for HIO */
		if (IO_SCAN_CHAIN_3 == io_scan_chain_id) {
			DEBUG_MEMORY
			clrbits_le32((SOCFPGA_SYSMGR_ADDRESS+
				SYSMGR_FRZCTRL_HIOCTRL_ADDRESS),
				SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK);
		} /* if (HIO) */

		/*
		 * Check if the scan chain engine is inactive and the
		 * WFIFO is empty before enabling the IO scan chain
		 */
		if (SCAN_MGR_IO_SCAN_ENGINE_STATUS_IDLE
			!= scan_mgr_io_scan_chain_engine_is_idle(
			MAX_WAITING_DELAY_IO_SCAN_ENGINE)) {
			DEBUG_MEMORY
			return 1;
		}

		/*
		 * Enable IO Scan chain based on scan chain id
		 * Note: only one chain can be enabled at a time
		 */
		setbits_le32((SOCFPGA_SCANMGR_ADDRESS +
			SCANMGR_EN_ADDRESS),
			1 << io_scan_chain_id);

		/*
		 * Calculate number of iteration needed for
		 * full 128-bit (4 x32-bits) bits shifting.
		 * Each TDI_TDO packet can shift in maximum 128-bits
		 */
		io_program_iter
			= io_scan_chain_len_in_bits >>
			IO_SCAN_CHAIN_128BIT_SHIFT;
		io_scan_chain_data_residual
			= io_scan_chain_len_in_bits &
			IO_SCAN_CHAIN_128BIT_MASK;

		/*
		 * Construct TDI_TDO packet for
		 * 128-bit IO scan chain (2 bytes)
		 */
		tdi_tdo_header = TDI_TDO_HEADER_FIRST_BYTE
			| (TDI_TDO_MAX_PAYLOAD <<
			TDI_TDO_HEADER_SECOND_BYTE_SHIFT);

		/* Program IO scan chain in 128-bit iteration */
		DEBUG_MEMORY
		for (i = 0; i < io_program_iter; i++) {

			/* write TDI_TDO packet header to scan manager */
			writel(tdi_tdo_header,
				(SOCFPGA_SCANMGR_ADDRESS +
				SCANMGR_FIFODOUBLEBYTE_ADDRESS));

			/* calculate array index */
			index = i * 4;

			/*
			 * write 4 successive 32-bit IO scan
			 * chain data into WFIFO
			 */
			writel(iocsr_scan_chain[index],
				(SOCFPGA_SCANMGR_ADDRESS +
				SCANMGR_FIFOQUADBYTE_ADDRESS));
			writel(iocsr_scan_chain[index + 1],
				(SOCFPGA_SCANMGR_ADDRESS +
				SCANMGR_FIFOQUADBYTE_ADDRESS));
			writel(iocsr_scan_chain[index + 2],
				(SOCFPGA_SCANMGR_ADDRESS +
				SCANMGR_FIFOQUADBYTE_ADDRESS));
			writel(iocsr_scan_chain[index + 3],
				(SOCFPGA_SCANMGR_ADDRESS +
				SCANMGR_FIFOQUADBYTE_ADDRESS));

			/*
			 * Check if the scan chain engine has completed the
			 * IO scan chain data shifting
			 */
			if (SCAN_MGR_IO_SCAN_ENGINE_STATUS_IDLE
				!= scan_mgr_io_scan_chain_engine_is_idle(
				MAX_WAITING_DELAY_IO_SCAN_ENGINE)) {
				DEBUG_MEMORY
				/* Disable IO Scan chain when error detected */
				clrbits_le32((SOCFPGA_SCANMGR_ADDRESS +
					SCANMGR_EN_ADDRESS),
					1 << io_scan_chain_id);

				return 1;
			}
		}

		/* Calculate array index for final TDI_TDO packet */
		index = io_program_iter * 4;

		/* Final TDI_TDO packet if any */
		DEBUG_MEMORY
		if (0 != io_scan_chain_data_residual) {

			/*
			 * Calculate number of quad bytes FIFO write
			 * needed for the final TDI_TDO packet
			 */
			io_program_iter
				= io_scan_chain_data_residual >>
				IO_SCAN_CHAIN_32BIT_SHIFT;

			/*
			 * Construct TDI_TDO packet for remaining IO
			 * scan chain (2 bytes)
			 */
			tdi_tdo_header
				= TDI_TDO_HEADER_FIRST_BYTE |
				((io_scan_chain_data_residual - 1)
				<< TDI_TDO_HEADER_SECOND_BYTE_SHIFT);

			/*
			 * Program the last part of IO scan chain
			 * write TDI_TDO packet header (2 bytes) to
			 * scan manager
			 */
			writel(tdi_tdo_header,
				(SOCFPGA_SCANMGR_ADDRESS +
				SCANMGR_FIFODOUBLEBYTE_ADDRESS));

			DEBUG_MEMORY
			for (i = 0; i < io_program_iter; i++) {

				/*
				 * write remaining scan chain data into scan
				 * manager WFIFO with 4 bytes write
				*/
				writel(iocsr_scan_chain[index + i],
					(SOCFPGA_SCANMGR_ADDRESS +
					SCANMGR_FIFOQUADBYTE_ADDRESS));
			}

			index += io_program_iter;
			residual = io_scan_chain_data_residual &
				IO_SCAN_CHAIN_32BIT_MASK;

			if (IO_SCAN_CHAIN_PAYLOAD_24BIT < residual) {
				/*
				 * write the last 4B scan chain data
				 * into scan manager WFIFO
				 */
				DEBUG_MEMORY
				writel(iocsr_scan_chain[index],
					(SOCFPGA_SCANMGR_ADDRESS +
					SCANMGR_FIFOQUADBYTE_ADDRESS));

			} else {
				/*
				 * write the remaining 1 - 3 bytes scan chain
				 * data into scan manager WFIFO byte by byte
				 * to prevent JTAG engine shifting unused data
				 * from the FIFO and mistaken the data as a
				 * valid command (even though unused bits are
				 * set to 0, but just to prevent hardware
				 * glitch)
				 */
				DEBUG_MEMORY
				for (i = 0; i < residual; i += 8) {
					writel(
						((iocsr_scan_chain[index] >> i)
						& IO_SCAN_CHAIN_BYTE_MASK),
						(SOCFPGA_SCANMGR_ADDRESS +
						SCANMGR_FIFOSINGLEBYTE_ADDRESS)
						);

				}
			}

			/*
			 * Check if the scan chain engine has completed the
			 * IO scan chain data shifting
			 */
			if (SCAN_MGR_IO_SCAN_ENGINE_STATUS_IDLE
				!=  scan_mgr_io_scan_chain_engine_is_idle(
				MAX_WAITING_DELAY_IO_SCAN_ENGINE)) {
				DEBUG_MEMORY
				/* Disable IO Scan chain when error detected */
				clrbits_le32((SOCFPGA_SCANMGR_ADDRESS +
					SCANMGR_EN_ADDRESS),
					1 << io_scan_chain_id);
				return 1;
			}
		} /* if (io_scan_chain_data_residual) */
コード例 #9
0
ファイル: gic.c プロジェクト: lynxis/coreboot-signed
void enable_bcm_gic(void)
{
	setbits_le32(&mvmap2315_bcm_gicc->ctrl, MVMAP2315_BCM_GICC_EN0);
	setbits_le32(&mvmap2315_bcm_gicc->ctrl, MVMAP2315_BCM_GICD_FIQ_EN);
	setbits_le32(&mvmap2315_bcm_gicd->ctrl, MVMAP2315_BCM_GICD_EN0);
}
コード例 #10
0
ファイル: test.c プロジェクト: RoelandK/Amlogic-reff16-uboot
static void timer_init()
{
	//100uS stick timer a mode : periodic, timer a enable, timer e enable
    setbits_le32(P_AO_TIMER_REG,0x1f);
}
コード例 #11
0
ファイル: gmac.c プロジェクト: KunYi/uboot-samx6i
int sunxi_gmac_initialize(bd_t *bis)
{
	int pin;
	struct sunxi_ccm_reg *const ccm =
		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;

	/* Set up clock gating */
#ifndef CONFIG_MACH_SUN6I
	setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
#else
	setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_RESET_OFFSET_GMAC);
	setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_GMAC);
#endif

	/* Set MII clock */
#ifdef CONFIG_RGMII
	setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
		CCM_GMAC_CTRL_GPIT_RGMII);
	setbits_le32(&ccm->gmac_clk_cfg,
		     CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY));
#else
	setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII |
		CCM_GMAC_CTRL_GPIT_MII);
#endif

#ifndef CONFIG_MACH_SUN6I
	/* Configure pin mux settings for GMAC */
	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
#ifdef CONFIG_RGMII
		/* skip unused pins in RGMII mode */
		if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
			continue;
#endif
		sunxi_gpio_set_cfgpin(pin, SUN7I_GPA0_GMAC);
		sunxi_gpio_set_drv(pin, 3);
	}
#elif defined CONFIG_RGMII
	/* Configure sun6i RGMII mode pin mux settings */
	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++) {
		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
		sunxi_gpio_set_drv(pin, 3);
	}
	for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
		sunxi_gpio_set_drv(pin, 3);
	}
	for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(20); pin++) {
		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
		sunxi_gpio_set_drv(pin, 3);
	}
	for (pin = SUNXI_GPA(25); pin <= SUNXI_GPA(27); pin++) {
		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
		sunxi_gpio_set_drv(pin, 3);
	}
#elif defined CONFIG_GMII
	/* Configure sun6i GMII mode pin mux settings */
	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(27); pin++) {
		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
		sunxi_gpio_set_drv(pin, 2);
	}
#else
	/* Configure sun6i MII mode pin mux settings */
	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++)
		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
	for (pin = SUNXI_GPA(8); pin <= SUNXI_GPA(9); pin++)
		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
	for (pin = SUNXI_GPA(11); pin <= SUNXI_GPA(14); pin++)
		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
	for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(24); pin++)
		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
	for (pin = SUNXI_GPA(26); pin <= SUNXI_GPA(27); pin++)
		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
#endif

#ifdef CONFIG_RGMII
	return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_RGMII);
#elif defined CONFIG_GMII
	return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_GMII);
#else
	return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_MII);
#endif
}
コード例 #12
0
ファイル: test.c プロジェクト: RoelandK/Amlogic-reff16-uboot
void enter_power_down()
{
	int i;
	unsigned v1,v2,v;
	unsigned rtc_ctrl;
	unsigned power_key;

	//*******************************************
	//*  power down flow  
	//*******************************************

	f_serial_puts("\n");
	
	wait_uart_empty();

	// disable jtag
	setbits_le32(P_AO_RTI_PIN_MUX_REG, 1<<13);
	clrbits_le32(P_AO_RTI_PIN_MUX_REG, 1<<14);
	
	// turn off mali clock
	clrbits_le32(P_HHI_MALI_CLK_CNTL, 1 << 8);
	
	// disable all memory accesses.
    disable_mmc_req();
    
    //save registers for clk and ddr
    store_restore_plls(1);
    
    //mmc enter sleep
    mmc_sleep();
//    delay_ms(20);
    
    // save ddr power
    APB_Wr(MMC_PHY_CTRL, APB_Rd(MMC_PHY_CTRL)|(1<<0)|(1<<8)|(1<<13));
    APB_Wr(PCTL_PHYCR_ADDR, APB_Rd(PCTL_PHYCR_ADDR)|(1<<6));
    APB_Wr(PCTL_DLLCR9_ADDR, APB_Rd(PCTL_DLLCR9_ADDR)|(1<<31));
// 	  delay_ms(20);

 	// power down DDR
 	writel(readl(P_HHI_DDR_PLL_CNTL)|(1<<15),P_HHI_DDR_PLL_CNTL);

	// enable retention
	enable_retention();

	writel(0,P_AO_RTI_STATUS_REG1);

 	// reset A9
//	setbits_le32(P_A9_CFG2, 7<<16);
	clrbits_le32(P_HHI_SYS_CPU_CLK_CNTL, 1<<4); // disable APB_CLK
	clrbits_le32(P_HHI_SYS_CPU_CLK_CNTL, 1<<5); // disable AT_CLK
	setbits_le32(P_HHI_SYS_CPU_CLK_CNTL,1<<19);
	udelay(10);
	 
	// enable iso ee for A9
	writel(readl(P_AO_RTI_PWR_CNTL_REG0)&(~(1<<4)),P_AO_RTI_PWR_CNTL_REG0);
	udelay(1000);
	
#ifdef POWER_OFF_HDMI_VCC
	reg7_off();
#endif
#ifdef POWER_OFF_AVDD33
	reg5_off();
#endif

#ifdef POWER_OFF_EE 
	//iso EE from AO
	//comment isolate EE. otherwise cannot detect power key.
	// writel(readl(P_AO_RTI_PWR_CNTL_REG0)&(~(1<<0)),P_AO_RTI_PWR_CNTL_REG0); 
	writel(readl(P_AO_RTI_PWR_CNTL_REG0)&(~(1<<2)),P_AO_RTI_PWR_CNTL_REG0);
	writel(readl(P_AO_RTI_PWR_CNTL_REG0)&(~(1<<3)),P_AO_RTI_PWR_CNTL_REG0);

	//?? Gate off clk81 to EE domain
	writel(readl(P_AO_RTI_GEN_CNTL_REG0)&(~(1<<12)),P_AO_RTI_GEN_CNTL_REG0);
	//-------------------------------
	//turn off EE voltage
	//v = readl(0xC8100024);
	//v &= ~(1<<9);
	//v &= ~(1<<25);
	//writel(v,0xC8100024);
#else
	// ee use 32k
	writel(readl(P_HHI_MPEG_CLK_CNTL)|(1<<9),P_HHI_MPEG_CLK_CNTL);
#endif

	
	// change RTC filter for 32k
  rtc_ctrl = readl(0xC810074c);
	//writel(0x00800000,0xC810074c);
	writel(0,0xC810074c);
	// switch to 32k
    writel(readl(P_AO_RTI_PWR_CNTL_REG0)|(1<<8),P_AO_RTI_PWR_CNTL_REG0);
    udelay(100);
#ifdef POWER_OFF_VDDIO 
	vddio_off(); 
#endif		
#ifdef POWER_OFF_AVDD25
	reg6_off();
#endif
#ifdef POWER_OFF_VCC
    power_off_VCC(0);
#endif

	udelay(100);
#if (defined(POWER_DOWN_VCC12) || defined(POWER_DOWN_DDR))
	switch_voltage(1);
#endif
#ifdef POWER_DOWN_DDR
	powerdown_ddr();
#endif
#ifdef POWER_DOWN_VCC12
	powerdown_vcc12();
#endif

	// gate off REMOTE, UART
	//writel(readl(P_AO_RTI_GEN_CNTL_REG0)&(~(0xF)),P_AO_RTI_GEN_CNTL_REG0);
	// wait key
    #if 1
    //backup the remote config (on arm)
    backup_remote_register();
    
    //set the ir_remote to 32k mode at ARC
    init_custom_trigger();
    
    //set the detect gpio
    //setbits_le32(P_AO_GPIO_O_EN_N,(1<<3));
    while(1)
    {
    	//detect remote key
		  power_key=readl(P_AO_IR_DEC_FRAME);
		  if(power_key==0xf50a7748) break;
        		  
		  //detect IO key
		  /*power_key=readl(P_AO_GPIO_I); 
		  power_key=power_key&(1<<3);
		  if(!power_key)
		    break;
		  */
		 #ifdef RTC_AUTO_WAKE_UP
		  power_key = readl(0xc8100744);
		  if((power_key&8) != 0) break;
		 #endif
	  }
	  
    #elif 1
    power_key = readl(0Xc8100744);
    while (((power_key&4) != 0)&&((power_key&8) == 0))
   {
     	power_key = readl(0Xc8100744);
   }
   #else
    for(i=0;i<64;i++)
    {
        udelay(1000);
        //udelay(1000);
    }
   #endif
    
	// gate on REMOTE, I2C s/m, UART
	//writel(readl(P_AO_RTI_GEN_CNTL_REG0)|0xF, P_AO_RTI_GEN_CNTL_REG0); 
	udelay(10);
#ifdef POWER_DOWN_DDR
	powerup_ddr();
#endif
#ifdef POWER_DOWN_VCC12
	powerup_vcc12();
#endif
#if (defined(POWER_DOWN_VCC12) || defined(POWER_DOWN_DDR))
	switch_voltage(0);
#endif

#ifdef POWER_OFF_VCC
    power_off_VCC(1);
#endif

#ifdef POWER_OFF_AVDD25
	reg6_on();
#endif
#ifdef POWER_OFF_VDDIO 
	vddio_on();
#endif
	udelay(100);
   // switch to clk81 
	writel(readl(P_AO_RTI_PWR_CNTL_REG0)&(~(0x1<<8)),P_AO_RTI_PWR_CNTL_REG0);
	udelay(100);
	// restore RTC filter
	writel(rtc_ctrl,0xC810074c);

	// set AO interrupt mask
	writel(0xFFFF,P_AO_IRQ_STAT_CLR);
	
#ifdef POWER_OFF_EE
	//turn on EE voltage
	//v = readl(0xC8100024);
	//v &= ~(1<<9);
	//v |= (1<<25);
	//writel(v,0xC8100024);
	//delay_ms(200);

	// un-iso AO domain from EE bit0=signals, bit1=reset, bit2=irq, bit3=test_mode
 	writel(readl(P_AO_RTI_PWR_CNTL_REG0)|(0xD<<0),P_AO_RTI_PWR_CNTL_REG0);

	//un isolate the reset in the EE
	writel(readl(P_AO_RTI_PWR_CNTL_REG0)|(0x1<<5),P_AO_RTI_PWR_CNTL_REG0);

	writel(readl(P_AO_RTI_PWR_CNTL_REG0)|(0x1<<5)|(1<<3)|(1<<2)|(1<<1)|(1<<0), \
			   P_AO_RTI_PWR_CNTL_REG0);
#else
    // ee go back to clk81
	writel(readl(P_HHI_MPEG_CLK_CNTL)&(~(0x1<<9)),P_HHI_MPEG_CLK_CNTL);
#endif
	
#ifdef POWER_OFF_AVDD33
	reg5_on();
#endif
#ifdef POWER_OFF_HDMI_VCC
	reg7_on();
#endif    

    store_restore_plls(0);
     
    init_ddr_pll();
	
    udelay(1000);
    uart_reset();

    reset_mmc();

    // initialize mmc and put it to sleep
    init_pctl();

    mmc_sleep();
    
    // disable retention
    disable_retention();

    // Next, we wake up
    mmc_wakeup();

    // Next, we enable all requests
    enable_mmc_req();

//	f_serial_puts("restart arm...\n");
	
	//0. make sure a9 reset
	setbits_le32(P_A9_CFG2,1<<17); // release APB reset
	udelay(1000);
	setbits_le32(P_A9_CFG2,1<<16); // release AXI reset
	udelay(1000);
	setbits_le32(P_A9_CFG2,1<<18); // release A9DBG reset
	udelay(1000);
	setbits_le32(P_HHI_SYS_CPU_CLK_CNTL,1<<19);
	udelay(1000);	
	//1. write flag
	if (power_key&8)
		writel(0xabcd1234,P_AO_RTI_STATUS_REG2);
	else
		writel(0x1234abcd,P_AO_RTI_STATUS_REG2);
	
	//2. remap AHB SRAM
	writel(3,P_AO_REMAP_REG0);
	writel(2,P_AHB_ARBDEC_REG);
 
	//3. turn off romboot clock
	writel(readl(P_HHI_GCLK_MPEG1)&0x7fffffff,P_HHI_GCLK_MPEG1);
 
	//4. Release ISO for A9 domain.
	setbits_le32(P_AO_RTI_PWR_CNTL_REG0,1<<4);
	udelay(1000);
	
	writel(	(0 << 9)    | // select xtal as clock source
			(0 << 0)	, 
			P_HHI_MALI_CLK_CNTL);
	delay_ms(1);
	setbits_le32(P_HHI_SYS_CPU_CLK_CNTL, (1<<14)|(1<<15)); // soft reset
	udelay(10);
	clrbits_le32(P_HHI_SYS_CPU_CLK_CNTL, (1<<14)|(1<<15)); // soft reset
	udelay(1000);
	
	//reset A9
	writel(0xF,P_RESET4_REGISTER);// -- reset arm.ww
	writel(1<<14,P_RESET2_REGISTER);// -- reset arm.mali
	udelay(1000);
	clrbits_le32(P_A9_CFG2,1<<17); // release APB reset
	udelay(1000);
	clrbits_le32(P_A9_CFG2,1<<16); // release AXI reset
	udelay(1000);
	clrbits_le32(P_A9_CFG2,1<<18); // release A9DBG reset
	udelay(1000);

	setbits_le32(P_HHI_SYS_CPU_CLK_CNTL, 1<<4); // enable APB_CLK
	udelay(10);
	
	clrbits_le32(P_HHI_SYS_CPU_CLK_CNTL,1<<19); // release A9 reset
	
	
	udelay(1000);
	
	//reset the IR REMOTE
	resume_remote_register();
  
//	delay_1s();
//	delay_1s();
//	delay_1s();
}
コード例 #13
0
ファイル: clocks.c プロジェクト: Aorjoa/bootloader
/*
 * Enable non-essential clock domains, modules and
 * do some additional special settings needed
 */
static void enable_non_essential_clocks(void)
{
	u32 i, max = 100, wait_for_enable = 0;
	u32 *const clk_domains_non_essential[] = {
		&prcm->cm_mpu_m3_clkstctrl,
		&prcm->cm_ivahd_clkstctrl,
		&prcm->cm_dsp_clkstctrl,
		&prcm->cm_dss_clkstctrl,
		&prcm->cm_sgx_clkstctrl,
		&prcm->cm1_abe_clkstctrl,
		&prcm->cm_c2c_clkstctrl,
		&prcm->cm_cam_clkstctrl,
		&prcm->cm_dss_clkstctrl,
		&prcm->cm_sdma_clkstctrl,
		0
	};

	u32 *const clk_modules_hw_auto_non_essential[] = {
		&prcm->cm_mpu_m3_mpu_m3_clkctrl,
		&prcm->cm_ivahd_ivahd_clkctrl,
		&prcm->cm_ivahd_sl2_clkctrl,
		&prcm->cm_dsp_dsp_clkctrl,
		&prcm->cm_l3_2_gpmc_clkctrl,
		&prcm->cm_l3instr_l3_3_clkctrl,
		&prcm->cm_l3instr_l3_instr_clkctrl,
		&prcm->cm_l3instr_intrconn_wp1_clkctrl,
		&prcm->cm_l3init_hsi_clkctrl,
		&prcm->cm_l3init_hsusbtll_clkctrl,
		0
	};

	u32 *const clk_modules_explicit_en_non_essential[] = {
		&prcm->cm1_abe_aess_clkctrl,
		&prcm->cm1_abe_pdm_clkctrl,
		&prcm->cm1_abe_dmic_clkctrl,
		&prcm->cm1_abe_mcasp_clkctrl,
		&prcm->cm1_abe_mcbsp1_clkctrl,
		&prcm->cm1_abe_mcbsp2_clkctrl,
		&prcm->cm1_abe_mcbsp3_clkctrl,
		&prcm->cm1_abe_slimbus_clkctrl,
		&prcm->cm1_abe_timer5_clkctrl,
		&prcm->cm1_abe_timer6_clkctrl,
		&prcm->cm1_abe_timer7_clkctrl,
		&prcm->cm1_abe_timer8_clkctrl,
		&prcm->cm1_abe_wdt3_clkctrl,
		&prcm->cm_l4per_gptimer9_clkctrl,
		&prcm->cm_l4per_gptimer10_clkctrl,
		&prcm->cm_l4per_gptimer11_clkctrl,
		&prcm->cm_l4per_gptimer3_clkctrl,
		&prcm->cm_l4per_gptimer4_clkctrl,
		&prcm->cm_l4per_hdq1w_clkctrl,
		&prcm->cm_l4per_mcbsp4_clkctrl,
		&prcm->cm_l4per_mcspi2_clkctrl,
		&prcm->cm_l4per_mcspi3_clkctrl,
		&prcm->cm_l4per_mcspi4_clkctrl,
		&prcm->cm_l4per_mmcsd3_clkctrl,
		&prcm->cm_l4per_mmcsd4_clkctrl,
		&prcm->cm_l4per_mmcsd5_clkctrl,
		&prcm->cm_l4per_uart1_clkctrl,
		&prcm->cm_l4per_uart2_clkctrl,
		&prcm->cm_l4per_uart4_clkctrl,
		&prcm->cm_wkup_keyboard_clkctrl,
		&prcm->cm_wkup_wdtimer2_clkctrl,
		&prcm->cm_cam_iss_clkctrl,
		&prcm->cm_cam_fdif_clkctrl,
		&prcm->cm_dss_dss_clkctrl,
		&prcm->cm_sgx_sgx_clkctrl,
		&prcm->cm_l3init_hsusbhost_clkctrl,
		&prcm->cm_l3init_fsusb_clkctrl,
		0
	};

	/* Enable optional functional clock for ISS */
	setbits_le32(&prcm->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);

	/* Enable all optional functional clocks of DSS */
	setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);


	/* Put the clock domains in SW_WKUP mode */
	for (i = 0; (i < max) && clk_domains_non_essential[i]; i++) {
		enable_clock_domain(clk_domains_non_essential[i],
				    CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
	}

	/* Clock modules that need to be put in HW_AUTO */
	for (i = 0; (i < max) && clk_modules_hw_auto_non_essential[i]; i++) {
		enable_clock_module(clk_modules_hw_auto_non_essential[i],
				    MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
				    wait_for_enable);
	};

	/* Clock modules that need to be put in SW_EXPLICIT_EN mode */
	for (i = 0; (i < max) && clk_modules_explicit_en_non_essential[i];
	     i++) {
		enable_clock_module(clk_modules_explicit_en_non_essential[i],
				    MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
				    wait_for_enable);
	};

	/* Put the clock domains in HW_AUTO mode now */
	for (i = 0; (i < max) && clk_domains_non_essential[i]; i++) {
		enable_clock_domain(clk_domains_non_essential[i],
				    CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
	}

	/* Put camera module in no sleep mode */
	clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK,
			CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
			MODULE_CLKCTRL_MODULEMODE_SHIFT);
}
コード例 #14
0
ファイル: clocks.c プロジェクト: Aorjoa/bootloader
/*
 * Enable essential clock domains, modules and
 * do some additional special settings needed
 */
static void enable_basic_clocks(void)
{
	u32 i, max = 100, wait_for_enable = 1;
	u32 *const clk_domains_essential[] = {
		&prcm->cm_l4per_clkstctrl,
		&prcm->cm_l3init_clkstctrl,
		&prcm->cm_memif_clkstctrl,
		&prcm->cm_l4cfg_clkstctrl,
		0
	};

	u32 *const clk_modules_hw_auto_essential[] = {
		&prcm->cm_wkup_gpio1_clkctrl,
		&prcm->cm_l4per_gpio2_clkctrl,
		&prcm->cm_l4per_gpio3_clkctrl,
		&prcm->cm_l4per_gpio4_clkctrl,
		&prcm->cm_l4per_gpio5_clkctrl,
		&prcm->cm_l4per_gpio6_clkctrl,
		&prcm->cm_memif_emif_1_clkctrl,
		&prcm->cm_memif_emif_2_clkctrl,
		&prcm->cm_l3init_hsusbotg_clkctrl,
		&prcm->cm_l3init_usbphy_clkctrl,
		&prcm->cm_l4cfg_l4_cfg_clkctrl,
		0
	};

	u32 *const clk_modules_explicit_en_essential[] = {
		&prcm->cm_l4per_gptimer2_clkctrl,
		&prcm->cm_l3init_hsmmc1_clkctrl,
		&prcm->cm_l3init_hsmmc2_clkctrl,
		&prcm->cm_l4per_mcspi1_clkctrl,
		&prcm->cm_wkup_gptimer1_clkctrl,
		&prcm->cm_l4per_i2c1_clkctrl,
		&prcm->cm_l4per_i2c2_clkctrl,
		&prcm->cm_l4per_i2c3_clkctrl,
		&prcm->cm_l4per_i2c4_clkctrl,
		&prcm->cm_wkup_wdtimer2_clkctrl,
		&prcm->cm_l4per_uart3_clkctrl,
		0
	};

	/* Enable optional additional functional clock for GPIO4 */
	setbits_le32(&prcm->cm_l4per_gpio4_clkctrl,
			GPIO4_CLKCTRL_OPTFCLKEN_MASK);

	/* Enable 96 MHz clock for MMC1 & MMC2 */
	setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl,
			HSMMC_CLKCTRL_CLKSEL_MASK);
	setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl,
			HSMMC_CLKCTRL_CLKSEL_MASK);

	/* Select 32KHz clock as the source of GPTIMER1 */
	setbits_le32(&prcm->cm_wkup_gptimer1_clkctrl,
			GPTIMER1_CLKCTRL_CLKSEL_MASK);

	/* Enable optional 48M functional clock for USB  PHY */
	setbits_le32(&prcm->cm_l3init_usbphy_clkctrl,
			USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK);

	/* Put the clock domains in SW_WKUP mode */
	for (i = 0; (i < max) && clk_domains_essential[i]; i++) {
		enable_clock_domain(clk_domains_essential[i],
				    CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
	}

	/* Clock modules that need to be put in HW_AUTO */
	for (i = 0; (i < max) && clk_modules_hw_auto_essential[i]; i++) {
		enable_clock_module(clk_modules_hw_auto_essential[i],
				    MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
				    wait_for_enable);
	};

	/* Clock modules that need to be put in SW_EXPLICIT_EN mode */
	for (i = 0; (i < max) && clk_modules_explicit_en_essential[i]; i++) {
		enable_clock_module(clk_modules_explicit_en_essential[i],
				    MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
				    wait_for_enable);
	};

	/* Put the clock domains in HW_AUTO mode now */
	for (i = 0; (i < max) && clk_domains_essential[i]; i++) {
		enable_clock_domain(clk_domains_essential[i],
				    CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
	}
}
コード例 #15
0
ファイル: lpc.c プロジェクト: 150balbes/Amlogic_S905-u-boot
/* CougarPoint PCH Power Management init */
static void cpt_pm_init(pci_dev_t dev)
{
	debug("CougarPoint PM init\n");
	pci_write_config8(dev, 0xa9, 0x47);
	setbits_le32(RCB_REG(0x2238), (1 << 6) | (1 << 0));

	setbits_le32(RCB_REG(0x228c), 1 << 0);
	setbits_le32(RCB_REG(0x1100), (1 << 13) | (1 << 14));
	setbits_le32(RCB_REG(0x0900), 1 << 14);
	writel(0xc0388400, RCB_REG(0x2304));
	setbits_le32(RCB_REG(0x2314), (1 << 5) | (1 << 18));
	setbits_le32(RCB_REG(0x2320), (1 << 15) | (1 << 1));
	clrsetbits_le32(RCB_REG(0x3314), ~0x1f, 0xf);
	writel(0x050f0000, RCB_REG(0x3318));
	writel(0x04000000, RCB_REG(0x3324));
	setbits_le32(RCB_REG(0x3340), 0xfffff);
	setbits_le32(RCB_REG(0x3344), 1 << 1);

	writel(0x0001c000, RCB_REG(0x3360));
	writel(0x00061100, RCB_REG(0x3368));
	writel(0x7f8fdfff, RCB_REG(0x3378));
	writel(0x000003fc, RCB_REG(0x337c));
	writel(0x00001000, RCB_REG(0x3388));
	writel(0x0001c000, RCB_REG(0x3390));
	writel(0x00000800, RCB_REG(0x33a0));
	writel(0x00001000, RCB_REG(0x33b0));
	writel(0x00093900, RCB_REG(0x33c0));
	writel(0x24653002, RCB_REG(0x33cc));
	writel(0x062108fe, RCB_REG(0x33d0));
	clrsetbits_le32(RCB_REG(0x33d4), 0x0fff0fff, 0x00670060);
	writel(0x01010000, RCB_REG(0x3a28));
	writel(0x01010404, RCB_REG(0x3a2c));
	writel(0x01041041, RCB_REG(0x3a80));
	clrsetbits_le32(RCB_REG(0x3a84), 0x0000ffff, 0x00001001);
	setbits_le32(RCB_REG(0x3a84), 1 << 24); /* SATA 2/3 disabled */
	setbits_le32(RCB_REG(0x3a88), 1 << 0);  /* SATA 4/5 disabled */
	writel(0x00000001, RCB_REG(0x3a6c));
	clrsetbits_le32(RCB_REG(0x2344), ~0x00ffff00, 0xff00000c);
	clrsetbits_le32(RCB_REG(0x80c), 0xff << 20, 0x11 << 20);
	writel(0, RCB_REG(0x33c8));
	setbits_le32(RCB_REG(0x21b0), 0xf);
}
コード例 #16
0
ファイル: clock_init.c プロジェクト: 0ida/coreboot
void system_clock_init(struct mem_timings *mem,
		struct arm_clk_ratios *arm_clk_ratio)
{
	u32 val, tmp;

	/* Turn on the MCT as early as possible. */
	exynos_mct->g_tcon |= (1 << 8);

	clrbits_le32(&exynos_clock->src_cpu, MUX_APLL_SEL_MASK);
	do {
		val = readl(&exynos_clock->mux_stat_cpu);
	} while ((val | MUX_APLL_SEL_MASK) != val);

	clrbits_le32(&exynos_clock->src_core1, MUX_MPLL_SEL_MASK);
	do {
		val = readl(&exynos_clock->mux_stat_core1);
	} while ((val | MUX_MPLL_SEL_MASK) != val);

	clrbits_le32(&exynos_clock->src_top2, MUX_CPLL_SEL_MASK);
	clrbits_le32(&exynos_clock->src_top2, MUX_EPLL_SEL_MASK);
	clrbits_le32(&exynos_clock->src_top2, MUX_VPLL_SEL_MASK);
	clrbits_le32(&exynos_clock->src_top2, MUX_GPLL_SEL_MASK);
	tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK
		| MUX_GPLL_SEL_MASK;
	do {
		val = readl(&exynos_clock->mux_stat_top2);
	} while ((val | tmp) != val);

	clrbits_le32(&exynos_clock->src_cdrex, MUX_BPLL_SEL_MASK);
	do {
		val = readl(&exynos_clock->mux_stat_cdrex);
	} while ((val | MUX_BPLL_SEL_MASK) != val);

	/* PLL locktime */
	writel(APLL_LOCK_VAL, &exynos_clock->apll_lock);

	writel(MPLL_LOCK_VAL, &exynos_clock->mpll_lock);

	writel(BPLL_LOCK_VAL, &exynos_clock->bpll_lock);

	writel(CPLL_LOCK_VAL, &exynos_clock->cpll_lock);

	writel(GPLL_LOCK_VAL, &exynos_clock->gpll_lock);

	writel(EPLL_LOCK_VAL, &exynos_clock->epll_lock);

	writel(VPLL_LOCK_VAL, &exynos_clock->vpll_lock);

	writel(CLK_REG_DISABLE, &exynos_clock->pll_div2_sel);

	writel(MUX_HPM_SEL_MASK, &exynos_clock->src_cpu);
	do {
		val = readl(&exynos_clock->mux_stat_cpu);
	} while ((val | HPM_SEL_SCLK_MPLL) != val);

	val = arm_clk_ratio->arm2_ratio << 28
		| arm_clk_ratio->apll_ratio << 24
		| arm_clk_ratio->pclk_dbg_ratio << 20
		| arm_clk_ratio->atb_ratio << 16
		| arm_clk_ratio->periph_ratio << 12
		| arm_clk_ratio->acp_ratio << 8
		| arm_clk_ratio->cpud_ratio << 4
		| arm_clk_ratio->arm_ratio;
	writel(val, &exynos_clock->div_cpu0);
	do {
		val = readl(&exynos_clock->div_stat_cpu0);
	} while (0 != val);

	writel(CLK_DIV_CPU1_VAL, &exynos_clock->div_cpu1);
	do {
		val = readl(&exynos_clock->div_stat_cpu1);
	} while (0 != val);

	/* switch A15 clock source to OSC clock before changing APLL */
	clrbits_le32(&exynos_clock->src_cpu, APLL_FOUT);

	/* Set APLL */
	writel(APLL_CON1_VAL, &exynos_clock->apll_con1);
	val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv,
			arm_clk_ratio->apll_sdiv);
	writel(val, &exynos_clock->apll_con0);
	while ((readl(&exynos_clock->apll_con0) & APLL_CON0_LOCKED) == 0)
		;

	/* now it is safe to switch to APLL */
	setbits_le32(&exynos_clock->src_cpu, APLL_FOUT);

	/* Set MPLL */
	writel(MPLL_CON1_VAL, &exynos_clock->mpll_con1);
	val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv);
	writel(val, &exynos_clock->mpll_con0);
	while ((readl(&exynos_clock->mpll_con0) & MPLL_CON0_LOCKED) == 0)
		;

	/*
	 * Configure MUX_MPLL_FOUT to choose the direct clock source
	 * path and avoid the fixed DIV/2 block to save power
	 */
	setbits_le32(&exynos_clock->pll_div2_sel, MUX_MPLL_FOUT_SEL);

	/* Set BPLL */
	if (mem->use_bpll) {
		writel(BPLL_CON1_VAL, &exynos_clock->bpll_con1);
		val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv);
		writel(val, &exynos_clock->bpll_con0);
		while ((readl(&exynos_clock->bpll_con0) & BPLL_CON0_LOCKED) == 0)
			;

		setbits_le32(&exynos_clock->pll_div2_sel, MUX_BPLL_FOUT_SEL);
	}

	/* Set CPLL */
	writel(CPLL_CON1_VAL, &exynos_clock->cpll_con1);
	val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv);
	writel(val, &exynos_clock->cpll_con0);
	while ((readl(&exynos_clock->cpll_con0) & CPLL_CON0_LOCKED) == 0)
		;

	/* Set GPLL */
	writel(GPLL_CON1_VAL, &exynos_clock->gpll_con1);
	val = set_pll(mem->gpll_mdiv, mem->gpll_pdiv, mem->gpll_sdiv);
	writel(val, &exynos_clock->gpll_con0);
	while ((readl(&exynos_clock->gpll_con0) & GPLL_CON0_LOCKED) == 0)
		;

	/* Set EPLL */
	writel(EPLL_CON2_VAL, &exynos_clock->epll_con2);
	writel(EPLL_CON1_VAL, &exynos_clock->epll_con1);
	val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv);
	writel(val, &exynos_clock->epll_con0);
	while ((readl(&exynos_clock->epll_con0) & EPLL_CON0_LOCKED) == 0)
		;

	/* Set VPLL */
	writel(VPLL_CON2_VAL, &exynos_clock->vpll_con2);
	writel(VPLL_CON1_VAL, &exynos_clock->vpll_con1);
	val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv);
	writel(val, &exynos_clock->vpll_con0);
	while ((readl(&exynos_clock->vpll_con0) & VPLL_CON0_LOCKED) == 0)
		;

	writel(CLK_SRC_CORE0_VAL, &exynos_clock->src_core0);
	writel(CLK_DIV_CORE0_VAL, &exynos_clock->div_core0);
	while (readl(&exynos_clock->div_stat_core0) != 0)
		;

	writel(CLK_DIV_CORE1_VAL, &exynos_clock->div_core1);
	while (readl(&exynos_clock->div_stat_core1) != 0)
		;

	writel(CLK_DIV_SYSRGT_VAL, &exynos_clock->div_sysrgt);
	while (readl(&exynos_clock->div_stat_sysrgt) != 0)
		;

	writel(CLK_DIV_ACP_VAL, &exynos_clock->div_acp);
	while (readl(&exynos_clock->div_stat_acp) != 0)
		;

	writel(CLK_DIV_SYSLFT_VAL, &exynos_clock->div_syslft);
	while (readl(&exynos_clock->div_stat_syslft) != 0)
		;

	writel(CLK_SRC_TOP0_VAL, &exynos_clock->src_top0);
	writel(CLK_SRC_TOP1_VAL, &exynos_clock->src_top1);
	writel(TOP2_VAL, &exynos_clock->src_top2);
	writel(CLK_SRC_TOP3_VAL, &exynos_clock->src_top3);

	writel(CLK_DIV_TOP0_VAL, &exynos_clock->div_top0);
	while (readl(&exynos_clock->div_stat_top0))
		;

	writel(CLK_DIV_TOP1_VAL, &exynos_clock->div_top1);
	while (readl(&exynos_clock->div_stat_top1))
		;

	writel(CLK_SRC_LEX_VAL, &exynos_clock->src_lex);
	while (1) {
		val = readl(&exynos_clock->mux_stat_lex);
		if (val == (val | 1))
			break;
	}

	writel(CLK_DIV_LEX_VAL, &exynos_clock->div_lex);
	while (readl(&exynos_clock->div_stat_lex))
		;

	writel(CLK_DIV_R0X_VAL, &exynos_clock->div_r0x);
	while (readl(&exynos_clock->div_stat_r0x))
		;

	writel(CLK_DIV_R0X_VAL, &exynos_clock->div_r0x);
	while (readl(&exynos_clock->div_stat_r0x))
		;

	writel(CLK_DIV_R1X_VAL, &exynos_clock->div_r1x);
	while (readl(&exynos_clock->div_stat_r1x))
		;

	if (mem->use_bpll) {
		writel(MUX_BPLL_SEL_MASK | MUX_MCLK_CDREX_SEL |
			MUX_MCLK_DPHY_SEL, &exynos_clock->src_cdrex);
	} else {
		writel(CLK_REG_DISABLE, &exynos_clock->src_cdrex);
	}

	writel(CLK_DIV_CDREX_VAL, &exynos_clock->div_cdrex);
	while (readl(&exynos_clock->div_stat_cdrex))
		;

	val = readl(&exynos_clock->src_cpu);
	val |= CLK_SRC_CPU_VAL;
	writel(val, &exynos_clock->src_cpu);

	val = readl(&exynos_clock->src_top2);
	val |= CLK_SRC_TOP2_VAL;
	writel(val, &exynos_clock->src_top2);

	val = readl(&exynos_clock->src_core1);
	val |= CLK_SRC_CORE1_VAL;
	writel(val, &exynos_clock->src_core1);

	writel(CLK_SRC_FSYS0_VAL, &exynos_clock->src_fsys);
	writel(CLK_DIV_FSYS0_VAL, &exynos_clock->div_fsys0);
	while (readl(&exynos_clock->div_stat_fsys0))
		;

	writel(CLK_REG_DISABLE, &exynos_clock->clkout_cmu_cpu);
	writel(CLK_REG_DISABLE, &exynos_clock->clkout_cmu_core);
	writel(CLK_REG_DISABLE, &exynos_clock->clkout_cmu_acp);
	writel(CLK_REG_DISABLE, &exynos_clock->clkout_cmu_top);
	writel(CLK_REG_DISABLE, &exynos_clock->clkout_cmu_lex);
	writel(CLK_REG_DISABLE, &exynos_clock->clkout_cmu_r0x);
	writel(CLK_REG_DISABLE, &exynos_clock->clkout_cmu_r1x);
	writel(CLK_REG_DISABLE, &exynos_clock->clkout_cmu_cdrex);

	writel(CLK_SRC_PERIC0_VAL, &exynos_clock->src_peric0);
	writel(CLK_DIV_PERIC0_VAL, &exynos_clock->div_peric0);

	writel(CLK_SRC_PERIC1_VAL, &exynos_clock->src_peric1);
	writel(CLK_DIV_PERIC1_VAL, &exynos_clock->div_peric1);
	writel(CLK_DIV_PERIC2_VAL, &exynos_clock->div_peric2);
	writel(SCLK_SRC_ISP_VAL, &exynos_clock->sclk_src_isp);
	writel(SCLK_DIV_ISP_VAL, &exynos_clock->sclk_div_isp);
	writel(CLK_DIV_ISP0_VAL, &exynos_clock->div_isp0);
	writel(CLK_DIV_ISP1_VAL, &exynos_clock->div_isp1);
	writel(CLK_DIV_ISP2_VAL, &exynos_clock->div_isp2);

	/* FIMD1 SRC CLK SELECTION */
	writel(CLK_SRC_DISP1_0_VAL, &exynos_clock->src_disp1_0);

	val = MMC2_PRE_RATIO_VAL << MMC2_PRE_RATIO_OFFSET
		| MMC2_RATIO_VAL << MMC2_RATIO_OFFSET
		| MMC3_PRE_RATIO_VAL << MMC3_PRE_RATIO_OFFSET
		| MMC3_RATIO_VAL << MMC3_RATIO_OFFSET;
	writel(val, &exynos_clock->div_fsys2);
}
コード例 #17
0
ファイル: lpc.c プロジェクト: 150balbes/Amlogic_S905-u-boot
void lpc_enable(pci_dev_t dev)
{
	/* Enable PCH Display Port */
	writew(0x0010, RCB_REG(DISPBDF));
	setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF);
}
コード例 #18
0
ファイル: fb.c プロジェクト: tidatida/coreboot
/* Bypass FIMD of DISP1_BLK */
static void fimd_bypass(void)
{
	setbits_le32(&exynos_sysreg->disp1blk_cfg, FIMDBYPASS_DISP1);
	exynos_sysreg->disp1blk_cfg &= ~FIMDBYPASS_DISP1;
}
コード例 #19
0
ファイル: ehci-fsl.c プロジェクト: AeroGirl/u-boot-kern3.2
/*
 * Create the appropriate control structures to manage
 * a new EHCI host controller.
 *
 * Excerpts from linux ehci fsl driver.
 */
int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
	struct usb_ehci *ehci;
	const char *phy_type = NULL;
	size_t len;
#ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
	char usb_phy[5];

	usb_phy[0] = '\0';
#endif

	ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR;
	*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
	*hcor = (struct ehci_hcor *)((uint32_t) *hccr +
			HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));

	/* Set to Host mode */
	setbits_le32(&ehci->usbmode, CM_HOST);

	out_be32(&ehci->snoop1, SNOOP_SIZE_2GB);
	out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB);

	/* Init phy */
	if (hwconfig_sub("usb1", "phy_type"))
		phy_type = hwconfig_subarg("usb1", "phy_type", &len);
	else
		phy_type = getenv("usb_phy_type");

	if (!phy_type) {
#ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
		/* if none specified assume internal UTMI */
		strcpy(usb_phy, "utmi");
		phy_type = usb_phy;
#else
		printf("WARNING: USB phy type not defined !!\n");
		return -1;
#endif
	}

	if (!strcmp(phy_type, "utmi")) {
#if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
		setbits_be32(&ehci->control, PHY_CLK_SEL_UTMI);
		setbits_be32(&ehci->control, UTMI_PHY_EN);
		udelay(1000); /* delay required for PHY Clk to appear */
#endif
		out_le32(&(*hcor)->or_portsc[0], PORT_PTS_UTMI);
		setbits_be32(&ehci->control, USB_EN);
	} else {
		setbits_be32(&ehci->control, PHY_CLK_SEL_ULPI);
		clrsetbits_be32(&ehci->control, UTMI_PHY_EN, USB_EN);
		udelay(1000); /* delay required for PHY Clk to appear */
		if (!usb_phy_clk_valid(ehci))
			return -EINVAL;
		out_le32(&(*hcor)->or_portsc[0], PORT_PTS_ULPI);
	}

	out_be32(&ehci->prictrl, 0x0000000c);
	out_be32(&ehci->age_cnt_limit, 0x00000040);
	out_be32(&ehci->sictrl, 0x00000001);

	in_le32(&ehci->usbmode);

	return 0;
}
コード例 #20
0
ファイル: fb.c プロジェクト: tidatida/coreboot
/*
 * DP H/w Link Training. Set DPCD link rate and bandwidth.
 * param dp		pointer to main s5p-dp structure
 * param max_lane	No of lanes
 * param max_rate	bandwidth
 * return status
 */
static int s5p_dp_hw_link_training(struct s5p_dp_device *dp,
				   unsigned int max_lane,
				   unsigned int max_rate)
{
	int pll_is_locked = 0;
	u32 data;
	int lane;
	struct stopwatch sw;
	struct exynos5_dp *base = dp->base;

	/* Stop Video */
	clrbits_le32(&base->video_ctl_1, VIDEO_EN);

	stopwatch_init_msecs_expire(&sw, PLL_LOCK_TIMEOUT);

	while ((pll_is_locked = s5p_dp_get_pll_lock_status(dp)) == PLL_UNLOCKED) {
		if (stopwatch_expired(&sw)) {
			/* Ignore this error, and try to continue */
			printk(BIOS_ERR, "PLL is not locked yet.\n");
			break;
		}
	}
	printk(BIOS_SPEW, "PLL is %slocked\n",
			pll_is_locked == PLL_LOCKED ? "": "not ");
	/* Reset Macro */
	setbits_le32(&base->dp_phy_test, MACRO_RST);

	/* 10 us is the minimum reset time. */
	udelay(10);

	clrbits_le32(&base->dp_phy_test, MACRO_RST);

	/* Set TX pre-emphasis to minimum */
	for (lane = 0; lane < max_lane; lane++)
		if (s5p_dp_set_lane_lane_pre_emphasis(dp,
					      PRE_EMPHASIS_LEVEL_0, lane)) {
			printk(BIOS_DEBUG, "Unable to set pre emphasis level\n");
			return -ERR_PRE_EMPHASIS_LEVELS;
		}

	/* All DP analog module power up */
	writel(0x00, &base->dp_phy_pd);

	/* Initialize by reading RX's DPCD */
	s5p_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
	s5p_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);

	printk(BIOS_SPEW, "%s: rate 0x%x, lane_count %d\n", __func__,
		dp->link_train.link_rate, dp->link_train.lane_count);

	if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
	    (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
		printk(BIOS_DEBUG, "Rx Max Link Rate is abnormal :%x !\n",
		      dp->link_train.link_rate);
		/* Not Retrying */
		return -ERR_LINK_RATE_ABNORMAL;
	}

	if (dp->link_train.lane_count == 0) {
		printk(BIOS_DEBUG, "Rx Max Lane count is abnormal :%x !\n",
		      dp->link_train.lane_count);
		/* Not retrying */
		return -ERR_MAX_LANE_COUNT_ABNORMAL;
	}

	/* Setup TX lane count & rate */
	if (dp->link_train.lane_count > max_lane)
		dp->link_train.lane_count = max_lane;
	if (dp->link_train.link_rate > max_rate)
		dp->link_train.link_rate = max_rate;

	/* Set link rate and count as you want to establish*/
	writel(dp->link_train.lane_count, &base->lane_count_set);
	writel(dp->link_train.link_rate, &base->link_bw_set);

	/* Set sink to D0 (Sink Not Ready) mode. */
	s5p_dp_write_byte_to_dpcd(dp, DPCD_ADDR_SINK_POWER_STATE,
				  DPCD_SET_POWER_STATE_D0);

	/* Start HW link training */
	writel(HW_TRAINING_EN, &base->dp_hw_link_training);

	/* Wait until HW link training done */
	s5p_dp_wait_hw_link_training_done(dp);

	/* Get hardware link training status */
	data = readl(&base->dp_hw_link_training);
	printk(BIOS_SPEW, "hardware link training status: 0x%08x\n", data);
	if (data != 0) {
		printk(BIOS_ERR, " H/W link training failure: 0x%x\n", data);
		return -ERR_LINK_TRAINING_FAILURE;
	}

	/* Get Link Bandwidth */
	data = readl(&base->link_bw_set);

	dp->link_train.link_rate = data;

	data = readl(&base->lane_count_set);
	dp->link_train.lane_count = data;
	printk(BIOS_SPEW, "Done training: Link bandwidth: 0x%x, lane_count: %d\n",
		dp->link_train.link_rate, data);

	return 0;
}
コード例 #21
0
ファイル: sunxi_display.c プロジェクト: Xilinx/u-boot-xlnx
static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode,
				      bool for_ext_vga_dac)
{
	struct sunxi_lcdc_reg * const lcdc =
		(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
	struct sunxi_ccm_reg * const ccm =
		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	int clk_div, clk_double, pin;
	struct display_timing timing;

#if defined CONFIG_MACH_SUN8I && defined CONFIG_VIDEO_LCD_IF_LVDS
	for (pin = SUNXI_GPD(18); pin <= SUNXI_GPD(27); pin++) {
#else
	for (pin = SUNXI_GPD(0); pin <= SUNXI_GPD(27); pin++) {
#endif
#ifdef CONFIG_VIDEO_LCD_IF_PARALLEL
		sunxi_gpio_set_cfgpin(pin, SUNXI_GPD_LCD0);
#endif
#ifdef CONFIG_VIDEO_LCD_IF_LVDS
		sunxi_gpio_set_cfgpin(pin, SUNXI_GPD_LVDS0);
#endif
#ifdef CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
		sunxi_gpio_set_drv(pin, 3);
#endif
	}

	lcdc_pll_set(ccm, 0, mode->pixclock_khz, &clk_div, &clk_double,
		     sunxi_is_composite());

	sunxi_ctfb_mode_to_display_timing(mode, &timing);
	lcdc_tcon0_mode_set(lcdc, &timing, clk_div, for_ext_vga_dac,
			    sunxi_display.depth, CONFIG_VIDEO_LCD_DCLK_PHASE);
}

#if defined CONFIG_VIDEO_HDMI || defined CONFIG_VIDEO_VGA || defined CONFIG_VIDEO_COMPOSITE
static void sunxi_lcdc_tcon1_mode_set(const struct ctfb_res_modes *mode,
				      int *clk_div, int *clk_double,
				      bool use_portd_hvsync)
{
	struct sunxi_lcdc_reg * const lcdc =
		(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
	struct sunxi_ccm_reg * const ccm =
		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	struct display_timing timing;

	sunxi_ctfb_mode_to_display_timing(mode, &timing);
	lcdc_tcon1_mode_set(lcdc, &timing, use_portd_hvsync,
			    sunxi_is_composite());

	if (use_portd_hvsync) {
		sunxi_gpio_set_cfgpin(SUNXI_GPD(26), SUNXI_GPD_LCD0);
		sunxi_gpio_set_cfgpin(SUNXI_GPD(27), SUNXI_GPD_LCD0);
	}

	lcdc_pll_set(ccm, 1, mode->pixclock_khz, clk_div, clk_double,
		     sunxi_is_composite());
}
#endif /* CONFIG_VIDEO_HDMI || defined CONFIG_VIDEO_VGA || CONFIG_VIDEO_COMPOSITE */

#ifdef CONFIG_VIDEO_HDMI

static void sunxi_hdmi_setup_info_frames(const struct ctfb_res_modes *mode)
{
	struct sunxi_hdmi_reg * const hdmi =
		(struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
	u8 checksum = 0;
	u8 avi_info_frame[17] = {
		0x82, 0x02, 0x0d, 0x00, 0x12, 0x00, 0x88, 0x00,
		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
		0x00
	};
	u8 vendor_info_frame[19] = {
		0x81, 0x01, 0x06, 0x29, 0x03, 0x0c, 0x00, 0x40,
		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
		0x00, 0x00, 0x00
	};
	int i;

	if (mode->pixclock_khz <= 27000)
		avi_info_frame[5] = 0x40; /* SD-modes, ITU601 colorspace */
	else
		avi_info_frame[5] = 0x80; /* HD-modes, ITU709 colorspace */

	if (mode->xres * 100 / mode->yres < 156)
		avi_info_frame[5] |= 0x18; /* 4 : 3 */
	else
		avi_info_frame[5] |= 0x28; /* 16 : 9 */

	for (i = 0; i < ARRAY_SIZE(avi_info_frame); i++)
		checksum += avi_info_frame[i];

	avi_info_frame[3] = 0x100 - checksum;

	for (i = 0; i < ARRAY_SIZE(avi_info_frame); i++)
		writeb(avi_info_frame[i], &hdmi->avi_info_frame[i]);

	writel(SUNXI_HDMI_QCP_PACKET0, &hdmi->qcp_packet0);
	writel(SUNXI_HDMI_QCP_PACKET1, &hdmi->qcp_packet1);

	for (i = 0; i < ARRAY_SIZE(vendor_info_frame); i++)
		writeb(vendor_info_frame[i], &hdmi->vendor_info_frame[i]);

	writel(SUNXI_HDMI_PKT_CTRL0, &hdmi->pkt_ctrl0);
	writel(SUNXI_HDMI_PKT_CTRL1, &hdmi->pkt_ctrl1);

	setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_HDMI);
}

static void sunxi_hdmi_mode_set(const struct ctfb_res_modes *mode,
				int clk_div, int clk_double)
{
	struct sunxi_hdmi_reg * const hdmi =
		(struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
	int x, y;

	/* Write clear interrupt status bits */
	writel(SUNXI_HDMI_IRQ_STATUS_BITS, &hdmi->irq);

	if (sunxi_display.monitor == sunxi_monitor_hdmi)
		sunxi_hdmi_setup_info_frames(mode);

	/* Set input sync enable */
	writel(SUNXI_HDMI_UNKNOWN_INPUT_SYNC, &hdmi->unknown);

	/* Init various registers, select pll3 as clock source */
	writel(SUNXI_HDMI_VIDEO_POL_TX_CLK, &hdmi->video_polarity);
	writel(SUNXI_HDMI_PAD_CTRL0_RUN, &hdmi->pad_ctrl0);
	writel(SUNXI_HDMI_PAD_CTRL1, &hdmi->pad_ctrl1);
	writel(SUNXI_HDMI_PLL_CTRL, &hdmi->pll_ctrl);
	writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);

	/* Setup clk div and doubler */
	clrsetbits_le32(&hdmi->pll_ctrl, SUNXI_HDMI_PLL_CTRL_DIV_MASK,
			SUNXI_HDMI_PLL_CTRL_DIV(clk_div));
	if (!clk_double)
		setbits_le32(&hdmi->pad_ctrl1, SUNXI_HDMI_PAD_CTRL1_HALVE);

	/* Setup timing registers */
	writel(SUNXI_HDMI_Y(mode->yres) | SUNXI_HDMI_X(mode->xres),
	       &hdmi->video_size);

	x = mode->hsync_len + mode->left_margin;
	y = mode->vsync_len + mode->upper_margin;
	writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_bp);

	x = mode->right_margin;
	y = mode->lower_margin;
	writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_fp);

	x = mode->hsync_len;
	y = mode->vsync_len;
	writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_spw);

	if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
		setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_HOR);

	if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
		setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_VER);
}

static void sunxi_hdmi_enable(void)
{
	struct sunxi_hdmi_reg * const hdmi =
		(struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;

	udelay(100);
	setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_ENABLE);
}

#endif /* CONFIG_VIDEO_HDMI */

#if defined CONFIG_VIDEO_VGA || defined CONFIG_VIDEO_COMPOSITE

static void sunxi_tvencoder_mode_set(void)
{
	struct sunxi_ccm_reg * const ccm =
		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	struct sunxi_tve_reg * const tve =
		(struct sunxi_tve_reg *)SUNXI_TVE0_BASE;

	/* Reset off */
	setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_TVE_RST);
	/* Clock on */
	setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_TVE0);

	switch (sunxi_display.monitor) {
	case sunxi_monitor_vga:
		tvencoder_mode_set(tve, tve_mode_vga);
		break;
	case sunxi_monitor_composite_pal_nc:
		tvencoder_mode_set(tve, tve_mode_composite_pal_nc);
		break;
	case sunxi_monitor_composite_pal:
		tvencoder_mode_set(tve, tve_mode_composite_pal);
		break;
	case sunxi_monitor_composite_pal_m:
		tvencoder_mode_set(tve, tve_mode_composite_pal_m);
		break;
	case sunxi_monitor_composite_ntsc:
		tvencoder_mode_set(tve, tve_mode_composite_ntsc);
		break;
	case sunxi_monitor_none:
	case sunxi_monitor_dvi:
	case sunxi_monitor_hdmi:
	case sunxi_monitor_lcd:
		break;
	}
}

#endif /* CONFIG_VIDEO_VGA || defined CONFIG_VIDEO_COMPOSITE */

static void sunxi_drc_init(void)
{
#ifdef CONFIG_SUNXI_GEN_SUN6I
	struct sunxi_ccm_reg * const ccm =
		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;

	/* On sun6i the drc must be clocked even when in pass-through mode */
#ifdef CONFIG_MACH_SUN8I_A33
	setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_SAT);
#endif
	setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DRC0);
	clock_set_de_mod_clock(&ccm->iep_drc0_clk_cfg, 300000000);
#endif
}

#ifdef CONFIG_VIDEO_VGA_VIA_LCD
static void sunxi_vga_external_dac_enable(void)
{
	int pin;

	pin = sunxi_name_to_gpio(CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN);
	if (pin >= 0) {
		gpio_request(pin, "vga_enable");
		gpio_direction_output(pin, 1);
	}
}
コード例 #22
0
ファイル: hw_data.c プロジェクト: dzemskov/pia-uboot
/*
 * Enable essential clock domains, modules and
 * do some additional special settings needed
 */
void enable_basic_clocks(void)
{
    u32 const clk_domains_essential[] = {
        (*prcm)->cm_l4per_clkstctrl,
        (*prcm)->cm_l3init_clkstctrl,
        (*prcm)->cm_memif_clkstctrl,
        (*prcm)->cm_l4cfg_clkstctrl,
#ifdef CONFIG_DRIVER_TI_CPSW
        (*prcm)->cm_gmac_clkstctrl,
#endif
        0
    };

    u32 const clk_modules_hw_auto_essential[] = {
        (*prcm)->cm_l3_gpmc_clkctrl,
        (*prcm)->cm_memif_emif_1_clkctrl,
        (*prcm)->cm_memif_emif_2_clkctrl,
        (*prcm)->cm_l4cfg_l4_cfg_clkctrl,
        (*prcm)->cm_wkup_gpio1_clkctrl,
        (*prcm)->cm_l4per_gpio2_clkctrl,
        (*prcm)->cm_l4per_gpio3_clkctrl,
        (*prcm)->cm_l4per_gpio4_clkctrl,
        (*prcm)->cm_l4per_gpio5_clkctrl,
        (*prcm)->cm_l4per_gpio6_clkctrl,
        (*prcm)->cm_l4per_gpio7_clkctrl,
        (*prcm)->cm_l4per_gpio8_clkctrl,
        0
    };

    u32 const clk_modules_explicit_en_essential[] = {
        (*prcm)->cm_wkup_gptimer1_clkctrl,
        (*prcm)->cm_l3init_hsmmc1_clkctrl,
        (*prcm)->cm_l3init_hsmmc2_clkctrl,
        (*prcm)->cm_l4per_gptimer2_clkctrl,
        (*prcm)->cm_wkup_wdtimer2_clkctrl,
        (*prcm)->cm_l4per_uart3_clkctrl,
        (*prcm)->cm_l4per_i2c1_clkctrl,
#ifdef CONFIG_DRIVER_TI_CPSW
        (*prcm)->cm_gmac_gmac_clkctrl,
#endif

#ifdef CONFIG_TI_QSPI
        (*prcm)->cm_l4per_qspi_clkctrl,
#endif
        0
    };

    /* Enable optional additional functional clock for GPIO4 */
    setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
                 GPIO4_CLKCTRL_OPTFCLKEN_MASK);

    /* Enable 96 MHz clock for MMC1 & MMC2 */
    setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
                 HSMMC_CLKCTRL_CLKSEL_MASK);
    setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
                 HSMMC_CLKCTRL_CLKSEL_MASK);

    /* Set the correct clock dividers for mmc */
    setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
                 HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
    setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
                 HSMMC_CLKCTRL_CLKSEL_DIV_MASK);

    /* Select 32KHz clock as the source of GPTIMER1 */
    setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
                 GPTIMER1_CLKCTRL_CLKSEL_MASK);

    do_enable_clocks(clk_domains_essential,
                     clk_modules_hw_auto_essential,
                     clk_modules_explicit_en_essential,
                     1);

#ifdef CONFIG_TI_QSPI
    setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24));
#endif

    /* Enable SCRM OPT clocks for PER and CORE dpll */
    setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
                 OPTFCLKEN_SCRM_PER_MASK);
    setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
                 OPTFCLKEN_SCRM_CORE_MASK);
}
コード例 #23
0
ファイル: m3_skt_v1.c プロジェクト: rofehr/uboot-amlogic
static void sdio_pwr_off(unsigned port)
{
	setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
	clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
	/// @todo NOT FINISH
}
コード例 #24
0
static int  sdio_init(unsigned port)
{
	setbits_le32(P_PREG_CGPIO_EN_N,1<<5);

    return cpu_sdio_init(port);
}
コード例 #25
0
ファイル: dram.c プロジェクト: dwlinux/u-boot
static void mctl_setup_dram_clock(u32 clk)
{
	u32 reg_val;
	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;

	/* setup DRAM PLL */
	reg_val = readl(&ccm->pll5_cfg);
	reg_val &= ~CCM_PLL5_CTRL_M_MASK;		/* set M to 0 (x1) */
	reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
	reg_val &= ~CCM_PLL5_CTRL_K_MASK;		/* set K to 0 (x1) */
	reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2));
	reg_val &= ~CCM_PLL5_CTRL_N_MASK;		/* set N to 0 (x0) */
	reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(clk / 24));
	reg_val &= ~CCM_PLL5_CTRL_P_MASK;		/* set P to 0 (x1) */
	reg_val |= CCM_PLL5_CTRL_P(CCM_PLL5_CTRL_P_X(2));
	reg_val &= ~CCM_PLL5_CTRL_VCO_GAIN;		/* PLL VCO Gain off */
	reg_val |= CCM_PLL5_CTRL_EN;			/* PLL On */
	writel(reg_val, &ccm->pll5_cfg);
	udelay(5500);

	setbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_DDR_CLK);

#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I)
	/* reset GPS */
	clrbits_le32(&ccm->gps_clk_cfg, CCM_GPS_CTRL_RESET | CCM_GPS_CTRL_GATE);
	setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS);
	udelay(1);
	clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS);
#endif

	/* setup MBUS clock */
	reg_val = CCM_MBUS_CTRL_GATE |
#if defined(CONFIG_SUN7I) && defined(CONFIG_FAST_MBUS)
		  CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL6) |
		  CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(1)) |
		  CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(3));
#elif defined(CONFIG_SUN7I) && !defined(CONFIG_FAST_MBUS)
		  CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL6) |
		  CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(2)) |
		  CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(2));
#else /* defined(CONFIG_SUN5I) */
		  CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL5) |
		  CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(1)) |
		  CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(2));
#endif
	writel(reg_val, &ccm->mbus_clk_cfg);

	/*
	 * open DRAMC AHB & DLL register clock
	 * close it first
	 */
#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
	clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);
#else
	clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM);
#endif
	udelay(22);

	/* then open it */
#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
	setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);
#else
	setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM);
#endif
	udelay(22);
}
コード例 #26
0
/* Disable the watchdog (toggle reset to watchdog) */
void socfpga_watchdog_disable(void)
{
	/* assert reset for watchdog */
	setbits_le32(&reset_manager_base->per1modrst,
		     ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
}
コード例 #27
0
ファイル: ehci-tegra.c プロジェクト: SunnyBrother/u-boot-at91
/* set up the UTMI USB controller with the parameters provided */
static int init_utmi_usb_controller(struct fdt_usb *config,
				    enum usb_init_type init)
{
	struct fdt_usb_controller *controller;
	u32 b_sess_valid_mask, val;
	int loop_count;
	const unsigned *timing;
	struct usb_ctlr *usbctlr = config->reg;
	struct clk_rst_ctlr *clkrst;
	struct usb_ctlr *usb1ctlr;

	clock_enable(config->periph_id);

	/* Reset the usb controller */
	usbf_reset_controller(config, usbctlr);

	/* Stop crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN low */
	clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN);

	/* Follow the crystal clock disable by >100ns delay */
	udelay(1);

	b_sess_valid_mask = (VBUS_B_SESS_VLD_SW_VALUE | VBUS_B_SESS_VLD_SW_EN);
	clrsetbits_le32(&usbctlr->phy_vbus_sensors, b_sess_valid_mask,
			(init == USB_INIT_DEVICE) ? b_sess_valid_mask : 0);

	/*
	 * To Use the A Session Valid for cable detection logic, VBUS_WAKEUP
	 * mux must be switched to actually use a_sess_vld threshold.
	 */
	if (config->dr_mode == DR_MODE_OTG &&
	    dm_gpio_is_valid(&config->vbus_gpio))
		clrsetbits_le32(&usbctlr->usb1_legacy_ctrl,
			VBUS_SENSE_CTL_MASK,
			VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT);

	controller = &fdt_usb_controllers[config->type];
	debug("controller=%p, type=%d\n", controller, config->type);

	/*
	 * PLL Delay CONFIGURATION settings. The following parameters control
	 * the bring up of the plls.
	 */
	timing = get_pll_timing(controller);

	if (!controller->has_hostpc) {
		val = readl(&usbctlr->utmip_misc_cfg1);
		clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK,
				timing[PARAM_STABLE_COUNT] <<
				UTMIP_PLLU_STABLE_COUNT_SHIFT);
		clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK,
				timing[PARAM_ACTIVE_DELAY_COUNT] <<
				UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT);
		writel(val, &usbctlr->utmip_misc_cfg1);

		/* Set PLL enable delay count and crystal frequency count */
		val = readl(&usbctlr->utmip_pll_cfg1);
		clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK,
				timing[PARAM_ENABLE_DELAY_COUNT] <<
				UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT);
		clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK,
				timing[PARAM_XTAL_FREQ_COUNT] <<
				UTMIP_XTAL_FREQ_COUNT_SHIFT);
		writel(val, &usbctlr->utmip_pll_cfg1);
	} else {
		clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;

		val = readl(&clkrst->crc_utmip_pll_cfg2);
		clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK,
				timing[PARAM_STABLE_COUNT] <<
				UTMIP_PLLU_STABLE_COUNT_SHIFT);
		clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK,
				timing[PARAM_ACTIVE_DELAY_COUNT] <<
				UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT);
		writel(val, &clkrst->crc_utmip_pll_cfg2);

		/* Set PLL enable delay count and crystal frequency count */
		val = readl(&clkrst->crc_utmip_pll_cfg1);
		clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK,
				timing[PARAM_ENABLE_DELAY_COUNT] <<
				UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT);
		clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK,
				timing[PARAM_XTAL_FREQ_COUNT] <<
				UTMIP_XTAL_FREQ_COUNT_SHIFT);
		writel(val, &clkrst->crc_utmip_pll_cfg1);

		/* Disable Power Down state for PLL */
		clrbits_le32(&clkrst->crc_utmip_pll_cfg1,
			     PLLU_POWERDOWN | PLL_ENABLE_POWERDOWN |
			     PLL_ACTIVE_POWERDOWN);

		/* Recommended PHY settings for EYE diagram */
		val = readl(&usbctlr->utmip_xcvr_cfg0);
		clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MASK,
				0x4 << UTMIP_XCVR_SETUP_SHIFT);
		clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MSB_MASK,
				0x3 << UTMIP_XCVR_SETUP_MSB_SHIFT);
		clrsetbits_le32(&val, UTMIP_XCVR_HSSLEW_MSB_MASK,
				0x8 << UTMIP_XCVR_HSSLEW_MSB_SHIFT);
		writel(val, &usbctlr->utmip_xcvr_cfg0);
		clrsetbits_le32(&usbctlr->utmip_xcvr_cfg1,
				UTMIP_XCVR_TERM_RANGE_ADJ_MASK,
				0x7 << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT);

		/* Some registers can be controlled from USB1 only. */
		if (config->periph_id != PERIPH_ID_USBD) {
			clock_enable(PERIPH_ID_USBD);
			/* Disable Reset if in Reset state */
			reset_set_enable(PERIPH_ID_USBD, 0);
		}
		usb1ctlr = (struct usb_ctlr *)
			((unsigned long)config->reg & USB1_ADDR_MASK);
		val = readl(&usb1ctlr->utmip_bias_cfg0);
		setbits_le32(&val, UTMIP_HSDISCON_LEVEL_MSB);
		clrsetbits_le32(&val, UTMIP_HSDISCON_LEVEL_MASK,
				0x1 << UTMIP_HSDISCON_LEVEL_SHIFT);
		clrsetbits_le32(&val, UTMIP_HSSQUELCH_LEVEL_MASK,
				0x2 << UTMIP_HSSQUELCH_LEVEL_SHIFT);
		writel(val, &usb1ctlr->utmip_bias_cfg0);

		/* Miscellaneous setting mentioned in Programming Guide */
		clrbits_le32(&usbctlr->utmip_misc_cfg0,
			     UTMIP_SUSPEND_EXIT_ON_EDGE);
	}

	/* Setting the tracking length time */
	clrsetbits_le32(&usbctlr->utmip_bias_cfg1,
		UTMIP_BIAS_PDTRK_COUNT_MASK,
		timing[PARAM_BIAS_TIME] << UTMIP_BIAS_PDTRK_COUNT_SHIFT);

	/* Program debounce time for VBUS to become valid */
	clrsetbits_le32(&usbctlr->utmip_debounce_cfg0,
		UTMIP_DEBOUNCE_CFG0_MASK,
		timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT);

	if (timing[PARAM_DEBOUNCE_A_TIME] > 0xFFFF) {
		clrsetbits_le32(&usbctlr->utmip_debounce_cfg0,
				UTMIP_DEBOUNCE_CFG0_MASK,
				(timing[PARAM_DEBOUNCE_A_TIME] >> 1)
				<< UTMIP_DEBOUNCE_CFG0_SHIFT);
		clrsetbits_le32(&usbctlr->utmip_bias_cfg1,
				UTMIP_BIAS_DEBOUNCE_TIMESCALE_MASK,
				1 << UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT);
	}
コード例 #28
0
ファイル: lpc.c プロジェクト: 150balbes/Amlogic_S905-u-boot
static int pch_power_options(const void *blob, int node, pci_dev_t dev)
{
	u8 reg8;
	u16 reg16, pmbase;
	u32 reg32;
	const char *state;
	int pwr_on;
	int nmi_option;
	int ret;

	/*
	 * Which state do we want to goto after g3 (power restored)?
	 * 0 == S0 Full On
	 * 1 == S5 Soft Off
	 *
	 * If the option is not existent (Laptops), use Kconfig setting.
	 * TODO([email protected]): Make this configurable
	 */
	pwr_on = MAINBOARD_POWER_ON;

	reg16 = pci_read_config16(dev, GEN_PMCON_3);
	reg16 &= 0xfffe;
	switch (pwr_on) {
	case MAINBOARD_POWER_OFF:
		reg16 |= 1;
		state = "off";
		break;
	case MAINBOARD_POWER_ON:
		reg16 &= ~1;
		state = "on";
		break;
	case MAINBOARD_POWER_KEEP:
		reg16 &= ~1;
		state = "state keep";
		break;
	default:
		state = "undefined";
	}

	reg16 &= ~(3 << 4);	/* SLP_S4# Assertion Stretch 4s */
	reg16 |= (1 << 3);	/* SLP_S4# Assertion Stretch Enable */

	reg16 &= ~(1 << 10);
	reg16 |= (1 << 11);	/* SLP_S3# Min Assertion Width 50ms */

	reg16 |= (1 << 12);	/* Disable SLP stretch after SUS well */

	pci_write_config16(dev, GEN_PMCON_3, reg16);
	debug("Set power %s after power failure.\n", state);

	/* Set up NMI on errors. */
	reg8 = inb(0x61);
	reg8 &= 0x0f;		/* Higher Nibble must be 0 */
	reg8 &= ~(1 << 3);	/* IOCHK# NMI Enable */
	reg8 |= (1 << 2); /* PCI SERR# Disable for now */
	outb(reg8, 0x61);

	reg8 = inb(0x70);
	/* TODO([email protected]): Make this configurable */
	nmi_option = NMI_OFF;
	if (nmi_option) {
		debug("NMI sources enabled.\n");
		reg8 &= ~(1 << 7);	/* Set NMI. */
	} else {
		debug("NMI sources disabled.\n");
		/* Can't mask NMI from PCI-E and NMI_NOW */
		reg8 |= (1 << 7);
	}
	outb(reg8, 0x70);

	/* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */
	reg16 = pci_read_config16(dev, GEN_PMCON_1);
	reg16 &= ~(3 << 0);	/* SMI# rate 1 minute */
	reg16 &= ~(1 << 10);	/* Disable BIOS_PCI_EXP_EN for native PME */
#if DEBUG_PERIODIC_SMIS
	/* Set DEBUG_PERIODIC_SMIS in pch.h to debug using periodic SMIs */
	reg16 |= (3 << 0);	/* Periodic SMI every 8s */
#endif
	pci_write_config16(dev, GEN_PMCON_1, reg16);

	/* Set the board's GPI routing. */
	ret = pch_gpi_routing(blob, node, dev);
	if (ret)
		return ret;

	pmbase = pci_read_config16(dev, 0x40) & 0xfffe;

	writel(pmbase + GPE0_EN, fdtdec_get_int(blob, node,
						"intel,gpe0-enable", 0));
	writew(pmbase + ALT_GP_SMI_EN, fdtdec_get_int(blob, node,
						"intel,alt-gp-smi-enable", 0));

	/* Set up power management block and determine sleep mode */
	reg32 = inl(pmbase + 0x04); /* PM1_CNT */
	reg32 &= ~(7 << 10);	/* SLP_TYP */
	reg32 |= (1 << 0);	/* SCI_EN */
	outl(reg32, pmbase + 0x04);

	/* Clear magic status bits to prevent unexpected wake */
	setbits_le32(RCB_REG(0x3310), (1 << 4) | (1 << 5) | (1 << 0));
	clrbits_le32(RCB_REG(0x3f02), 0xf);

	return 0;
}
コード例 #29
0
ファイル: arc_pwr.c プロジェクト: matt0526/matt_uboot
void enter_power_down()
{
	int i;
	unsigned int uboot_cmd_flag=readl(P_AO_RTI_STATUS_REG2);//u-boot suspend cmd flag
	unsigned int vcin_state = 0;

    int voltage   = 0;
    int axp_ocv = 0;
	int wdt_flag;
	// First, we disable all memory accesses.

	f_serial_puts("step 1\n");

	asm(".long 0x003f236f"); //add sync instruction.

	store_restore_plls(0);

	f_serial_puts("ddr self-refresh\n");
	wait_uart_empty();

	ddr_self_refresh();

 	f_serial_puts("CPU off...\n");
 	wait_uart_empty();
	cpu_off();
	f_serial_puts("CPU off done\n");
	wait_uart_empty();
#ifdef CONFIG_CEC_WAKEUP
    hdmi_cec_func_config = readl(P_AO_DEBUG_REG0); 
    f_serial_puts("CEC M8:uboot: P_AO_DEBUG_REG0:\n");
    serial_put_hex(hdmi_cec_func_config,32);
    f_serial_puts("\n");
#endif
 	if(p_arc_pwr_op->power_off_at_24M)
		p_arc_pwr_op->power_off_at_24M();

#ifdef CONFIG_M201_COSTDOWN
	/* for led */
    clrbits_le32(P_AO_GPIO_O_EN_N,1<<18);
	setbits_le32(P_AO_GPIO_O_EN_N,1<<29);
#endif
	
//	while(readl(0xc8100000) != 0x13151719)
//	{}

//non 32k crystal oscillator platform DONT enter 32k in suspend mode
#ifndef CONFIG_NON_32K
	switch_24M_to_32K();
#endif 
	if(p_arc_pwr_op->power_off_at_32K_1)
		p_arc_pwr_op->power_off_at_32K_1();

	if(p_arc_pwr_op->power_off_at_32K_2)
		p_arc_pwr_op->power_off_at_32K_2();
	

	// gate off:  bit0: REMOTE;   bit3: UART
#ifndef CONFIG_NON_32K
	writel(readl(P_AO_RTI_GEN_CNTL_REG0)&(~(0x8)),P_AO_RTI_GEN_CNTL_REG0);
#endif
	if(uboot_cmd_flag == 0x87654321)//u-boot suspend cmd flag
	{
		if(p_arc_pwr_op->power_off_ddr15)
			p_arc_pwr_op->power_off_ddr15();
	}

	wdt_flag=readl(P_WATCHDOG_TC)&(1<<19);
	if(wdt_flag)
		writel(readl(P_WATCHDOG_TC)&(~(1<<19)),P_WATCHDOG_TC);
#if 1
	vcin_state = p_arc_pwr_op->detect_key(uboot_cmd_flag);
#else
	for(i=0;i<10;i++)
	{
		udelay__(1000);
		//udelay(1000);
	}
#endif

	if(uboot_cmd_flag == 0x87654321)//u-boot suspend cmd flag
	{
		if(p_arc_pwr_op->power_on_ddr15)
			p_arc_pwr_op->power_on_ddr15();
	}
	if(wdt_flag)
		writel((6*7812|((1<<16)-1))|(1<<19),P_WATCHDOG_TC);

// gate on:  bit0: REMOTE;   bit3: UART
	writel(readl(P_AO_RTI_GEN_CNTL_REG0)|0x8,P_AO_RTI_GEN_CNTL_REG0);

	if(p_arc_pwr_op->power_on_at_32K_2)
		p_arc_pwr_op->power_on_at_32K_2();

	if(p_arc_pwr_op->power_on_at_32K_1)
		p_arc_pwr_op->power_on_at_32K_1();

#ifndef CONFIG_NON_32K
	switch_32K_to_24M();
#endif

	// power on even more domains
	if(p_arc_pwr_op->power_on_at_24M)
		p_arc_pwr_op->power_on_at_24M();

 	uart_reset();
	f_serial_puts("step 8: ddr resume\n");
	wait_uart_empty();
	ddr_resume();

#ifdef CONFIG_M201_COSTDOWN
	/* for led */
    clrbits_le32(P_AO_GPIO_O_EN_N,1<<29);
	setbits_le32(P_AO_GPIO_O_EN_N,1<<18);
#endif
	
	f_serial_puts("restore pll\n");
	wait_uart_empty();
	store_restore_plls(1);//Before switch back to clk81, we need set PLL

	if (uboot_cmd_flag == 0x87654321 && (vcin_state == FLAG_WAKEUP_PWROFF)) {
		/*
		 * power off system before ARM is restarted
		 */
		f_serial_puts("no extern power shutdown\n");
		wait_uart_empty();
		p_arc_pwr_op->shut_down();
		do {
			udelay__(2000 * 100);
			f_serial_puts("wait shutdown...\n");
			wait_uart_empty();
		}while(1);
	}
#ifdef CONFIG_MESON_TRUSTZONE
	copy_reboot_code(temp_arm_base);
#else
	copy_reboot_code(NULL);
#endif
	writel(vcin_state,P_AO_RTI_STATUS_REG2);
	f_serial_puts("restart arm\n");
	wait_uart_empty();
	restart_arm();

    if (uboot_cmd_flag == 0x87654321) {
        writel(0,P_AO_RTI_STATUS_REG2);
        writel(readl(P_AO_RTI_PWR_CNTL_REG0)|(1<<4),P_AO_RTI_PWR_CNTL_REG0);
        clrbits_le32(P_HHI_SYS_CPU_CLK_CNTL,1<<19);
        //writel(10,0xc1109904);
        writel(1<<19|1<<24|10,0xc1109900);
        
        do{udelay__(200);f_serial_puts("wait reset...\n");wait_uart_empty();}while(1);
    }
}
コード例 #30
0
ファイル: cam_enc_4xx.c プロジェクト: JasonCC/u-boot-xlnx
	/* reset the phy */
	miiphy_reset(name, 0x0);
}

#else /* #ifndef CONFIG_SPL_BUILD */
static void cam_enc_4xx_set_all_led(void)
{
	struct davinci_gpio *gpio = davinci_gpio_bank45;

	setbits_le32(&gpio->out_data, CONFIG_CAM_ENC_LED_MASK);
}