void startPulses()
{
// s_current_protocol[0] = g_model.protocol + 1 ; // Not the same!
// s_current_protocol[1] = g_model.xprotocol + 1 ; // Not the same!
setupPulses(0) ;// For DSM-9XR this won't be sent
setupPulses(1) ;// For DSM-9XR this won't be sent
pass = 0 ; // Force a type 0 packet
pass_x = 0 ; // Force a type 0 packet
}
extern "C" void TIM8_CC_IRQHandler()
{
EXTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE ; // stop this interrupt
EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF ; // Clear flag
setupPulses(EXTERNAL_MODULE) ;
if (s_current_protocol[EXTERNAL_MODULE] == PROTO_PXX) {
DMA2_Stream2->CR &= ~DMA_SxCR_EN ; // Disable DMA
DMA2->LIFCR = DMA_LIFCR_CTCIF2 | DMA_LIFCR_CHTIF2 | DMA_LIFCR_CTEIF2 | DMA_LIFCR_CDMEIF2 | DMA_LIFCR_CFEIF2 ; // Write ones to clear bits
DMA2_Stream2->M0AR = CONVERT_PTR_UINT(&modulePulsesData[EXTERNAL_MODULE].pxx.pulses[1]);
DMA2_Stream2->CR |= DMA_SxCR_EN ; // Enable DMA
EXTMODULE_TIMER->CCR1 = modulePulsesData[EXTERNAL_MODULE].pxx.pulses[0];
EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
}
#if defined(DSM2)
else if (s_current_protocol[EXTERNAL_MODULE] >= PROTO_DSM2_LP45 && s_current_protocol[EXTERNAL_MODULE] <= PROTO_DSM2_DSMX) {
DMA2_Stream2->CR &= ~DMA_SxCR_EN ; // Disable DMA
DMA2->LIFCR = DMA_LIFCR_CTCIF2 | DMA_LIFCR_CHTIF2 | DMA_LIFCR_CTEIF2 | DMA_LIFCR_CDMEIF2 | DMA_LIFCR_CFEIF2 ; // Write ones to clear bits
DMA2_Stream2->M0AR = CONVERT_PTR_UINT(&modulePulsesData[EXTERNAL_MODULE].dsm2.pulses[1]);
DMA2_Stream2->CR |= DMA_SxCR_EN ; // Enable DMA
EXTMODULE_TIMER->CCR1 = modulePulsesData[EXTERNAL_MODULE].dsm2.pulses[0];
EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
}
#endif
else if (s_current_protocol[EXTERNAL_MODULE] == PROTO_PPM) {
EXTMODULE_TIMER->DIER |= TIM_DIER_UDE ;
EXTMODULE_TIMER->SR &= ~TIM_SR_UIF ; // Clear this flag
EXTMODULE_TIMER->DIER |= TIM_DIER_UIE ; // Enable this interrupt
}
else {
EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
}
}
extern "C" void TIM8_CC_IRQHandler()
{
TIM8->DIER &= ~TIM_DIER_CC2IE ; // stop this interrupt
TIM8->SR &= ~TIM_SR_CC2IF ; // Clear flag
setupPulses(EXTERNAL_MODULE) ;
if (s_current_protocol[EXTERNAL_MODULE] == PROTO_PXX) {
DMA2_Stream2->CR &= ~DMA_SxCR_EN ; // Disable DMA
DMA2->LIFCR = DMA_LIFCR_CTCIF2 | DMA_LIFCR_CHTIF2 | DMA_LIFCR_CTEIF2 | DMA_LIFCR_CDMEIF2 | DMA_LIFCR_CFEIF2 ; // Write ones to clear bits
DMA2_Stream2->M0AR = CONVERT_PTR_UINT(&pxxStream[EXTERNAL_MODULE][1]);
DMA2_Stream2->CR |= DMA_SxCR_EN ; // Enable DMA
TIM8->CCR1 = pxxStream[EXTERNAL_MODULE][0];
TIM8->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
}
#if defined(DSM2)
else if (s_current_protocol[EXTERNAL_MODULE] >= PROTO_DSM2_LP45 && s_current_protocol[EXTERNAL_MODULE] <= PROTO_DSM2_DSMX) {
DMA2_Stream2->CR &= ~DMA_SxCR_EN ; // Disable DMA
DMA2->LIFCR = DMA_LIFCR_CTCIF2 | DMA_LIFCR_CHTIF2 | DMA_LIFCR_CTEIF2 | DMA_LIFCR_CDMEIF2 | DMA_LIFCR_CFEIF2 ; // Write ones to clear bits
DMA2_Stream2->M0AR = CONVERT_PTR_UINT(&dsm2Stream[1]);
DMA2_Stream2->CR |= DMA_SxCR_EN ; // Enable DMA
TIM8->CCR1 = dsm2Stream[0];
TIM8->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
}
#endif
else if (s_current_protocol[EXTERNAL_MODULE] == PROTO_PPM) {
ppmStreamPtr[EXTERNAL_MODULE] = ppmStream[EXTERNAL_MODULE];
TIM8->DIER |= TIM_DIER_UDE ;
TIM8->SR &= ~TIM_SR_UIF ; // Clear this flag
TIM8->DIER |= TIM_DIER_UIE ; // Enable this interrupt
}
else {
TIM8->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
}
}
extern "C" void TIM1_CC_IRQHandler()
{
INTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE; // stop this interrupt
INTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // clear flag
DMA2_Stream6->CR &= ~DMA_SxCR_EN; // disable DMA, it will have the whole of the execution time of setupPulses() to actually stop
setupPulses(INTERNAL_MODULE);
if (s_current_protocol[INTERNAL_MODULE] == PROTO_PXX) {
DMA2->HIFCR = DMA_HIFCR_CTCIF6 | DMA_HIFCR_CHTIF6 | DMA_HIFCR_CTEIF6 | DMA_HIFCR_CDMEIF6 | DMA_HIFCR_CFEIF6;
DMA2_Stream6->M0AR = CONVERT_PTR_UINT(&modulePulsesData[INTERNAL_MODULE].pxx.pulses[1]);
DMA2_Stream6->CR |= DMA_SxCR_EN; // enable DMA
INTMODULE_TIMER->CCR3 = modulePulsesData[INTERNAL_MODULE].pxx.pulses[0];
INTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; // enable this interrupt
}
#if defined(TARANIS_INTERNAL_PPM)
else if (s_current_protocol[INTERNAL_MODULE] == PROTO_PPM) {
INTMODULE_TIMER->DIER |= TIM_DIER_UDE;
INTMODULE_TIMER->SR &= ~TIM_SR_UIF;
INTMODULE_TIMER->DIER |= TIM_DIER_UIE;
}
#endif
else {
INTMODULE_TIMER->DIER |= TIM_DIER_CC2IE;
}
}
extern "C" void TIM1_CC_IRQHandler()
{
TIM1->DIER &= ~TIM_DIER_CC2IE ; // stop this interrupt
TIM1->SR &= ~TIM_SR_CC2IF ; // Clear flag
setupPulses(INTERNAL_MODULE) ;
if (s_current_protocol[INTERNAL_MODULE] == PROTO_PXX) {
DMA2_Stream6->CR &= ~DMA_SxCR_EN ; // Disable DMA
DMA2->HIFCR = DMA_HIFCR_CTCIF6 | DMA_HIFCR_CHTIF6 | DMA_HIFCR_CTEIF6 | DMA_HIFCR_CDMEIF6 | DMA_HIFCR_CFEIF6 ; // Write ones to clear bits
DMA2_Stream6->M0AR = CONVERT_PTR_UINT(&pxxStream[INTERNAL_MODULE][1]);
DMA2_Stream6->CR |= DMA_SxCR_EN ; // Enable DMA
TIM1->CCR3 = pxxStream[INTERNAL_MODULE][0];
TIM1->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
}
else if (s_current_protocol[INTERNAL_MODULE] == PROTO_PPM) {
ppmStreamPtr[INTERNAL_MODULE] = ppmStream[INTERNAL_MODULE];
TIM1->DIER |= TIM_DIER_UDE ;
TIM1->SR &= ~TIM_SR_UIF ; // Clear this flag
TIM1->DIER |= TIM_DIER_UIE ; // Enable this interrupt
}
else {
TIM1->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
}
}
extern "C" void TIM1_CC_IRQHandler()
{
uint16_t t0 = TIM3->CNT;
TIM1->DIER &= ~TIM_DIER_CC2IE ; // stop this interrupt
TIM1->SR &= ~TIM_SR_CC2IF ; // Clear flag
#ifdef REV9E
s_current_protocol[INTERNAL_MODULE] = PROTO_OFF ;
#endif
DMA2_Stream6->CR &= ~DMA_SxCR_EN ; // Disable DMA
setupPulses(0) ;
if (s_current_protocol[INTERNAL_MODULE] == PROTO_PXX) {
// DMA2_Stream6->CR &= ~DMA_SxCR_EN ; // Disable DMA
DMA2->HIFCR = DMA_HIFCR_CTCIF6 | DMA_HIFCR_CHTIF6 | DMA_HIFCR_CTEIF6 | DMA_HIFCR_CDMEIF6 | DMA_HIFCR_CFEIF6 ; // Write ones to clear bits
DMA2_Stream6->M0AR = CONVERT_PTR(&pxxStream[INTERNAL_MODULE][1]);
DMA2_Stream6->CR |= DMA_SxCR_EN ; // Enable DMA
TIM1->CCR3 = pxxStream[INTERNAL_MODULE][0];
TIM1->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
}
else if (s_current_protocol[INTERNAL_MODULE] == PROTO_PPM) {
ppmStreamPtr[INTERNAL_MODULE] = ppmStream[INTERNAL_MODULE];
TIM1->DIER |= TIM_DIER_UDE ;
TIM1->SR &= ~TIM_SR_UIF ; // Clear this flag
TIM1->DIER |= TIM_DIER_UIE ; // Enable this interrupt
}
else {
TIM1->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
}
t0 = TIM3->CNT - t0;
g_timePXX = t0 ;
}
void startPulses()
{
PulsePol16 = PulsePol = !g_model.pulsePol ;
if(!PulsePol)
{
PORTB |= (1<<OUT_B_PPM);
}
Current_protocol = g_model.protocol + 10 ; // Not the same!
PausePulses = 0 ;
setupPulses() ;
}
void startPulses()
{
#if defined(PCBGRUVIN9X)
#if defined(DSM2_SERIAL)
if (!IS_DSM2_PROTOCOL(g_model.protocol))
#endif
{
// TODO g: There has to be a better place for this bug fix
OCR1B = 0xffff; /* Prevent any PPM_OUT pin toggle before the TCNT1 interrupt
fires for the first time and sets up the pulse period.
*** Prevents WDT reset loop. */
}
#endif
#if defined(SIMU)
s_current_protocol[0] = g_model.protocol;
#else
setupPulses();
#endif // SIMU
}
extern "C" void PWM_IRQHandler(void)
{
register Pwm *pwmptr;
register Ssc *sscptr;
uint32_t period;
uint32_t reason;
pwmptr = PWM;
reason = pwmptr->PWM_ISR1 ;
if (reason & PWM_ISR1_CHID3) {
// Use the current protocol, don't switch until set_up_pulses
switch (s_current_protocol[EXTERNAL_MODULE]) {
case PROTO_PXX:
// Alternate periods of 6.5mS and 2.5 mS
period = pwmptr->PWM_CH_NUM[3].PWM_CPDR;
if (period == 2500 * 2) {
period = 6500 * 2;
}
else {
period = 2500 * 2;
}
pwmptr->PWM_CH_NUM[3].PWM_CPDRUPD = period; // Period in half uS
if (period != 2500 * 2) {
setupPulses(EXTERNAL_MODULE);
}
else {
// Kick off serial output here
sscptr = SSC;
sscptr->SSC_TPR = CONVERT_PTR_UINT(modulePulsesData[EXTERNAL_MODULE].pxx.pulses);
sscptr->SSC_TCR = (uint8_t *)modulePulsesData[EXTERNAL_MODULE].pxx.ptr - (uint8_t *)modulePulsesData[EXTERNAL_MODULE].pxx.pulses;
sscptr->SSC_PTCR = SSC_PTCR_TXTEN; // Start transfers
}
break;
case PROTO_DSM2_LP45:
case PROTO_DSM2_DSM2:
case PROTO_DSM2_DSMX:
// Alternate periods of 19.5mS and 2.5 mS
period = pwmptr->PWM_CH_NUM[3].PWM_CPDR;
if (period == 2500 * 2) {
period = 19500 * 2;
}
else {
period = 2500 * 2;
}
pwmptr->PWM_CH_NUM[3].PWM_CPDRUPD = period; // Period in half uS
if (period != 2500 * 2) {
setupPulses(EXTERNAL_MODULE);
}
else {
// Kick off serial output here
sscptr = SSC;
sscptr->SSC_TPR = CONVERT_PTR_UINT(modulePulsesData[EXTERNAL_MODULE].dsm2.pulses);
sscptr->SSC_TCR = (uint8_t *)modulePulsesData[EXTERNAL_MODULE].dsm2.ptr - (uint8_t *)modulePulsesData[EXTERNAL_MODULE].dsm2.pulses;
sscptr->SSC_PTCR = SSC_PTCR_TXTEN; // Start transfers
}
break;
default:
pwmptr->PWM_CH_NUM[3].PWM_CPDRUPD = modulePulsesData[EXTERNAL_MODULE].ppm.pulses[modulePulsesData[EXTERNAL_MODULE].ppm.index++]; // Period in half uS
if (modulePulsesData[EXTERNAL_MODULE].ppm.pulses[modulePulsesData[EXTERNAL_MODULE].ppm.index] == 0) {
modulePulsesData[EXTERNAL_MODULE].ppm.index = 0;
setupPulses(EXTERNAL_MODULE);
}
break;
}
}
#if !defined(REVA)
if (reason & PWM_ISR1_CHID1) {
pwmptr->PWM_CH_NUM[1].PWM_CPDRUPD = modulePulsesData[EXTRA_MODULE].ppm.pulses[modulePulsesData[EXTRA_MODULE].ppm.index++] ; // Period in half uS
if (modulePulsesData[EXTRA_MODULE].ppm.pulses[modulePulsesData[EXTRA_MODULE].ppm.index] == 0) {
modulePulsesData[EXTRA_MODULE].ppm.index = 0;
setupPulsesPPM(EXTRA_MODULE);
}
}
#endif
}
extern "C" void PWM_IRQHandler (void)
{
register Pwm *pwmptr ;
register Ssc *sscptr ;
uint32_t period ;
uint32_t reason ;
pwmptr = PWM ;
reason = pwmptr->PWM_ISR1 ;
if ( reason & PWM_ISR1_CHID3 )
{
switch ( Current_protocol ) // Use the current, don't switch until set_up_pulses
{
case PROTO_PPM:
pwmptr->PWM_CH_NUM[3].PWM_CPDRUPD = Pulses[Pulses_index++] ; // Period in half uS
if ( Pulses[Pulses_index] == 0 )
{
Pulses_index = 0 ;
setupPulses() ;
}
break ;
case PROTO_PXX:
// Alternate periods of 6.5mS and 2.5 mS
period = pwmptr->PWM_CH_NUM[3].PWM_CPDR ;
if ( period == 5000 ) // 2.5 mS
{
period = 6500*2 ;
}
else
{
period = 5000 ; // 2.5 mS
}
pwmptr->PWM_CH_NUM[3].PWM_CPDRUPD = period ; // Period in half uS
if ( period != 5000 ) // 2.5 mS
{
setupPulses() ;
}
else
{
// Kick off serial output here
sscptr = SSC ;
sscptr->SSC_TPR = (uint32_t) Bit_pulses ;
sscptr->SSC_TCR = Serial_byte_count ;
sscptr->SSC_PTCR = SSC_PTCR_TXTEN ; // Start transfers
}
break ;
case PROTO_MULTI:
case PROTO_DSM2:
case PROTO_ASSAN:
// Alternate periods of 19.5mS/8.5mS and 2.5 mS
period = pwmptr->PWM_CH_NUM[3].PWM_CPDR ;
if ( period == 5000 ) // 2.5 mS
{
// if ( Dsm_Type )
// {
period = 8500*2 ; // Total 11 mS
// }
// else
// {
// period = 19500*2 ;
// }
}
else
{
period = 5000 ;
}
pwmptr->PWM_CH_NUM[3].PWM_CPDRUPD = period ; // Period in half uS
if ( period != 5000 ) // 2.5 mS
{
setupPulses() ;
}
else
{
// Kick off serial output here
if ( Current_protocol == PROTO_ASSAN )
{
// Enable SSC, output
PIOA->PIO_PDR = PIO_PA17 ; // Assign A17 to Peripheral
USART0->US_CR = US_CR_RXDIS ;
// PIOA->PIO_PER = PIO_PA5 ; // Assign A5 to PIO
}
sscptr = SSC ;
sscptr->SSC_TPR = (uint32_t) Bit_pulses ;
sscptr->SSC_TCR = Serial_byte_count ;
sscptr->SSC_PTCR = SSC_PTCR_TXTEN ; // Start transfers
if ( Current_protocol == PROTO_ASSAN )
{
// Enable termination interrupt
sscptr->SSC_IER = SSC_IER_TXBUFE ;
}
}
break ;
}
}
if ( reason & PWM_ISR1_CHID1 )
{
pwmptr->PWM_CH_NUM[1].PWM_CPDRUPD = Pulses2[Pulses2_index++] ; // Period in half uS
if ( Pulses2[Pulses2_index] == 0 )
{
Pulses2_index = 0 ;
setupPulsesPPM2() ;
}
}
}
extern "C" void PWM_IRQHandler(void)
{
register Pwm *pwmptr;
register Ssc *sscptr;
uint32_t period;
uint32_t reason;
pwmptr = PWM;
reason = pwmptr->PWM_ISR1 ;
if (reason & PWM_ISR1_CHID3) {
// Use the current protocol, don't switch until set_up_pulses
switch (s_current_protocol[EXTERNAL_MODULE]) {
case PROTO_PXX:
// Alternate periods of 15.5mS and 2.5 mS
period = pwmptr->PWM_CH_NUM[3].PWM_CPDR;
if (period == 5000) { // 2.5 mS
period = 15500 * 2;
}
else {
period = 5000;
}
pwmptr->PWM_CH_NUM[3].PWM_CPDRUPD = period; // Period in half uS
if (period != 5000) { // 2.5 mS
setupPulses(EXTERNAL_MODULE);
}
else {
// Kick off serial output here
sscptr = SSC;
sscptr->SSC_TPR = CONVERT_PTR_UINT(pxxStream[EXTERNAL_MODULE]);
sscptr->SSC_TCR = (uint8_t *)pxxStreamPtr[EXTERNAL_MODULE] - (uint8_t *)pxxStream[EXTERNAL_MODULE];
sscptr->SSC_PTCR = SSC_PTCR_TXTEN; // Start transfers
}
break;
case PROTO_DSM2_LP45:
case PROTO_DSM2_DSM2:
case PROTO_DSM2_DSMX:
// Alternate periods of 19.5mS and 2.5 mS
period = pwmptr->PWM_CH_NUM[3].PWM_CPDR;
if (period == 5000) { // 2.5 mS
period = 19500 * 2;
}
else {
period = 5000;
}
pwmptr->PWM_CH_NUM[3].PWM_CPDRUPD = period; // Period in half uS
if (period != 5000) { // 2.5 mS
setupPulses(0);
}
else {
// Kick off serial output here
sscptr = SSC;
sscptr->SSC_TPR = CONVERT_PTR_UINT(dsm2Stream);
sscptr->SSC_TCR = (uint8_t *)dsm2StreamPtr - (uint8_t *)dsm2Stream;
sscptr->SSC_PTCR = SSC_PTCR_TXTEN; // Start transfers
}
break;
default:
pwmptr->PWM_CH_NUM[3].PWM_CPDRUPD = ppmStream[EXTERNAL_MODULE][ppmStreamIndex[EXTERNAL_MODULE]++]; // Period in half uS
if (ppmStream[EXTERNAL_MODULE][ppmStreamIndex[EXTERNAL_MODULE]] == 0) {
ppmStreamIndex[EXTERNAL_MODULE] = 0;
setupPulses(EXTERNAL_MODULE);
}
break;
}
}
if (reason & PWM_ISR1_CHID1) {
pwmptr->PWM_CH_NUM[1].PWM_CPDRUPD = ppmStream[EXTRA_MODULE][ppmStreamIndex[EXTRA_MODULE]++] ; // Period in half uS
if (ppmStream[EXTRA_MODULE][ppmStreamIndex[EXTRA_MODULE]] == 0) {
ppmStreamIndex[EXTRA_MODULE] = 0;
setupPulsesPPM(EXTRA_MODULE);
}
}
}
extern "C" void TIM8_CC_IRQHandler()
{
#ifdef ASSAN
if ( TIM8->DIER & TIM_DIER_CC3IE )
{
if ( TIM8->SR & TIM_SR_CC3IF )
{
// must be ASSAN disable Tx output
uint32_t status;
TIM8->SR &= ~TIM_SR_CC3IF ; // Clear flag
#ifdef PCB9XT
GPIOB->BSRRH = 0x0004 ; // output disable
#else
GPIOD->BSRRH = PIN_SPORT_ON ; // output disable
#endif
USART2->CR1 |= USART_CR1_RE ;
status = USART2->SR ;
while (status & (USART_FLAG_RXNE))
{
status = USART2->DR;
status = USART2->SR ;
}
dsmTelemetryStartReceive() ;
return ;
}
}
if ( TIM8->DIER & TIM_DIER_CC1IE )
{
if ( TIM8->SR & TIM_SR_CC1IF )
{
// must be ASSAN re-enable Tx output
TIM8->SR &= ~TIM_SR_CC1IF ; // Clear flag
USART2->CR1 &= ~USART_CR1_RE ; // Stop receive
#ifdef PCB9XT
GPIOB->BSRRL = 0x0004 ; // output disable
#else
GPIOD->BSRRL = PIN_SPORT_ON ; // output enable
#endif
return ;
}
}
#endif
TIM8->DIER &= ~TIM_DIER_CC2IE ; // stop this interrupt
TIM8->SR &= ~TIM_SR_CC2IF ; // Clear flag
setupPulses(EXTERNAL_MODULE) ;
if (s_current_protocol[EXTERNAL_MODULE] == PROTO_PXX)
{
DMA2_Stream2->CR &= ~DMA_SxCR_EN ; // Disable DMA
DMA2->LIFCR = DMA_LIFCR_CTCIF2 | DMA_LIFCR_CHTIF2 | DMA_LIFCR_CTEIF2 | DMA_LIFCR_CDMEIF2 | DMA_LIFCR_CFEIF2 ; // Write ones to clear bits
DMA2_Stream2->M0AR = CONVERT_PTR(&pxxStream[EXTERNAL_MODULE][1]);
DMA2_Stream2->CR |= DMA_SxCR_EN ; // Enable DMA
TIM8->CCR1 = pxxStream[EXTERNAL_MODULE][0];
TIM8->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
}
else if ( (s_current_protocol[EXTERNAL_MODULE] == PROTO_DSM2 ) || (s_current_protocol[EXTERNAL_MODULE] == PROTO_MULTI ) )
{
DMA2_Stream2->CR &= ~DMA_SxCR_EN ; // Disable DMA
DMA2->LIFCR = DMA_LIFCR_CTCIF2 | DMA_LIFCR_CHTIF2 | DMA_LIFCR_CTEIF2 | DMA_LIFCR_CDMEIF2 | DMA_LIFCR_CFEIF2 ; // Write ones to clear bits
DMA2_Stream2->M0AR = CONVERT_PTR(&dsm2Stream[1]);
TIM8->CCMR1 = TIM_CCMR1_OC1M_2 ; // Force O/P low, hardware inverts it
TIM8->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0 ; // Toggle CC1 o/p
DMA2_Stream2->CR |= DMA_SxCR_EN ; // Enable DMA
TIM8->CCR1 = dsm2Stream[0];
TIM8->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
}
else if (s_current_protocol[EXTERNAL_MODULE] == PROTO_PPM) {
ppmStreamPtr[EXTERNAL_MODULE] = ppmStream[EXTERNAL_MODULE];
TIM8->DIER |= TIM_DIER_UDE ;
TIM8->SR &= ~TIM_SR_UIF ; // Clear this flag
TIM8->DIER |= TIM_DIER_UIE ; // Enable this interrupt
}
else
{
TIM8->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
}
}
