static void setup_epdc(void) { /*** epdc Maxim PMIC settings ***/ /* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */ imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); /* EPDC_VCOM0 - GPIO4[14] for VCOM control */ imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); /* EPDC_PWRWAKEUP - GPIO4[23] for EPD PMIC WAKEUP */ imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); /* EPDC_PWRCTRL0 - GPIO4[20] for EPD PWR CTL0 */ imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); /* Set pixel clock rates for EPDC in clock.c */ panel_info.epdc_data.wv_modes.mode_init = 0; panel_info.epdc_data.wv_modes.mode_du = 1; panel_info.epdc_data.wv_modes.mode_gc4 = 3; panel_info.epdc_data.wv_modes.mode_gc8 = 2; panel_info.epdc_data.wv_modes.mode_gc16 = 2; panel_info.epdc_data.wv_modes.mode_gc32 = 2; panel_info.epdc_data.epdc_timings = panel_timings; setup_epdc_power(); }
static void setup_epdc(void) { unsigned int reg; /*** epdc Maxim PMIC settings ***/ /* EPDC PWRSTAT - GPIO2[13] for PWR_GOOD status */ mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_PWRSTAT__GPIO_2_13); /* EPDC VCOM0 - GPIO2[3] for VCOM control */ mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_VCOM0__GPIO_2_3); /* UART4 TXD - GPIO2[14] for EPD PMIC WAKEUP */ mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_PWRWAKEUP__GPIO_2_14); /* EIM_A18 - GPIO2[7] for EPD PWR CTL0 */ mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_PWRCTRL0__GPIO_2_7); /*** Set pixel clock rates for EPDC ***/ /* EPDC AXI clk from PFD_400M, set to 396/2 = 198MHz */ reg = readl(CCM_BASE_ADDR + CLKCTL_CHSCCDR); reg &= ~0x3F000; reg |= (0x4 << 15) | (1 << 12); writel(reg, CCM_BASE_ADDR + CLKCTL_CHSCCDR); /* EPDC AXI clk enable */ reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR3); reg |= 0x0030; writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR3); /* EPDC PIX clk from PFD_540M, set to 540/4/5 = 27MHz */ reg = readl(CCM_BASE_ADDR + CLKCTL_CSCDR2); reg &= ~0x03F000; reg |= (0x5 << 15) | (4 << 12); writel(reg, CCM_BASE_ADDR + CLKCTL_CSCDR2); reg = readl(CCM_BASE_ADDR + CLKCTL_CBCMR); reg &= ~0x03800000; reg |= (0x3 << 23); writel(reg, CCM_BASE_ADDR + CLKCTL_CBCMR); /* EPDC PIX clk enable */ reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR3); reg |= 0x0C00; writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR3); panel_info.epdc_data.working_buf_addr = CONFIG_WORKING_BUF_ADDR; panel_info.epdc_data.waveform_buf_addr = CONFIG_WAVEFORM_BUF_ADDR; panel_info.epdc_data.wv_modes.mode_init = 0; panel_info.epdc_data.wv_modes.mode_du = 1; panel_info.epdc_data.wv_modes.mode_gc4 = 3; panel_info.epdc_data.wv_modes.mode_gc8 = 2; panel_info.epdc_data.wv_modes.mode_gc16 = 2; panel_info.epdc_data.wv_modes.mode_gc32 = 2; panel_info.epdc_data.epdc_timings = panel_timings; setup_epdc_power(); /* Assign fb_base */ gd->fb_base = CONFIG_FB_BASE; }
static void setup_epdc(void) { unsigned int reg; struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR; /*** epdc Maxim PMIC settings ***/ /* EPDC PWRSTAT - GPIO2[21] for PWR_GOOD status */ imx_iomux_v3_setup_pad(MX6_PAD_EIM_A17__GPIO2_IO21 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); /* EPDC VCOM0 - GPIO3[17] for VCOM control */ imx_iomux_v3_setup_pad(MX6_PAD_EIM_D17__GPIO3_IO17 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); /* UART4 TXD - GPIO3[20] for EPD PMIC WAKEUP */ imx_iomux_v3_setup_pad(MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); /* EIM_A18 - GPIO2[20] for EPD PWR CTL0 */ imx_iomux_v3_setup_pad(MX6_PAD_EIM_A18__GPIO2_IO20 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); /*** Set pixel clock rates for EPDC ***/ /* EPDC AXI clk (IPU2_CLK) from PFD_400M, set to 396/2 = 198MHz */ reg = readl(&ccm_regs->cscdr3); reg &= ~0x7C000; reg |= (1 << 16) | (1 << 14); writel(reg, &ccm_regs->cscdr3); /* EPDC AXI clk enable */ reg = readl(&ccm_regs->CCGR3); reg |= 0x00C0; writel(reg, &ccm_regs->CCGR3); /* EPDC PIX clk (IPU2_DI1_CLK) from PLL5, set to 650/4/6 = ~27MHz */ reg = readl(&ccm_regs->cscdr2); reg &= ~0x3FE00; reg |= (2 << 15) | (5 << 12); writel(reg, &ccm_regs->cscdr2); /* PLL5 enable (defaults to 650) */ reg = readl(&ccm_regs->analog_pll_video); reg &= ~((1 << 16) | (1 << 12)); reg |= (1 << 13); writel(reg, &ccm_regs->analog_pll_video); /* EPDC PIX clk enable */ reg = readl(&ccm_regs->CCGR3); reg |= 0x0C00; writel(reg, &ccm_regs->CCGR3); panel_info.epdc_data.wv_modes.mode_init = 0; panel_info.epdc_data.wv_modes.mode_du = 1; panel_info.epdc_data.wv_modes.mode_gc4 = 3; panel_info.epdc_data.wv_modes.mode_gc8 = 2; panel_info.epdc_data.wv_modes.mode_gc16 = 2; panel_info.epdc_data.wv_modes.mode_gc32 = 2; panel_info.epdc_data.epdc_timings = panel_timings; setup_epdc_power(); }
static void setup_epdc(void) { unsigned int reg; struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR; /*** epdc Maxim PMIC settings ***/ /* EPDC PWRSTAT - GPIO2[13] for PWR_GOOD status */ imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWRSTAT__GPIO_2_13 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); /* EPDC VCOM0 - GPIO2[3] for VCOM control */ imx_iomux_v3_setup_pad(MX6_PAD_EPDC_VCOM0__GPIO_2_3 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); /* UART4 TXD - GPIO2[14] for EPD PMIC WAKEUP */ imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWRWAKEUP__GPIO_2_14 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); /* EIM_A18 - GPIO2[7] for EPD PWR CTL0 */ imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWRCTRL0__GPIO_2_7 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); /*** Set pixel clock rates for EPDC ***/ /* EPDC AXI clk from PFD_400M, set to 396/2 = 198MHz */ reg = readl(&ccm_regs->chsccdr); reg &= ~0x3F000; reg |= (0x4 << 15) | (1 << 12); writel(reg, &ccm_regs->chsccdr); /* EPDC AXI clk enable */ reg = readl(&ccm_regs->CCGR3); reg |= 0x0030; writel(reg, &ccm_regs->CCGR3); /* EPDC PIX clk from PFD_540M, set to 540/4/5 = 27MHz */ reg = readl(&ccm_regs->cscdr2); reg &= ~0x03F000; reg |= (0x5 << 15) | (4 << 12); writel(reg, &ccm_regs->cscdr2); reg = readl(&ccm_regs->cbcmr); reg &= ~0x03800000; reg |= (0x3 << 23); writel(reg, &ccm_regs->cbcmr); /* EPDC PIX clk enable */ reg = readl(&ccm_regs->CCGR3); reg |= 0x0C00; writel(reg, &ccm_regs->CCGR3); panel_info.epdc_data.wv_modes.mode_init = 0; panel_info.epdc_data.wv_modes.mode_du = 1; panel_info.epdc_data.wv_modes.mode_gc4 = 3; panel_info.epdc_data.wv_modes.mode_gc8 = 2; panel_info.epdc_data.wv_modes.mode_gc16 = 2; panel_info.epdc_data.wv_modes.mode_gc32 = 2; panel_info.epdc_data.epdc_timings = panel_timings; setup_epdc_power(); }
static void setup_epdc(void) { unsigned int reg; /*** epdc Maxim PMIC settings ***/ /* EPDC PWRSTAT - GPIO2[21] for PWR_GOOD status */ imx_iomux_v3_setup_pad(MX6_PAD_EIM_A17__GPIO_2_21 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); /* EPDC VCOM0 - GPIO3[17] for VCOM control */ imx_iomux_v3_setup_pad(MX6_PAD_EIM_D17__GPIO_3_17 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); /* UART4 TXD - GPIO3[20] for EPD PMIC WAKEUP */ imx_iomux_v3_setup_pad(MX6_PAD_EIM_D20__GPIO_3_20 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); /* EIM_A18 - GPIO2[20] for EPD PWR CTL0 */ imx_iomux_v3_setup_pad(MX6_PAD_EIM_A18__GPIO_2_20 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); /*** Set pixel clock rates for EPDC ***/ /* EPDC AXI clk (IPU2_CLK) from PFD_400M, set to 396/2 = 198MHz */ reg = readl(CCM_BASE_ADDR + CLKCTL_CSCDR3); reg &= ~0x7C000; reg |= (1 << 16) | (1 << 14); writel(reg, CCM_BASE_ADDR + CLKCTL_CSCDR3); /* EPDC AXI clk enable */ reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR3); reg |= 0x00C0; writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR3); /* EPDC PIX clk (IPU2_DI1_CLK) from PLL5, set to 650/4/6 = ~27MHz */ reg = readl(CCM_BASE_ADDR + CLKCTL_CSCDR2); reg &= ~0x3FE00; reg |= (2 << 15) | (5 << 12); writel(reg, CCM_BASE_ADDR + CLKCTL_CSCDR2); /* PLL5 enable (defaults to 650) */ reg = readl(ANATOP_BASE_ADDR + ANATOP_PLL_VIDEO); reg &= ~((1 << 16) | (1 << 12)); reg |= (1 << 13); writel(reg, ANATOP_BASE_ADDR + ANATOP_PLL_VIDEO); /* EPDC PIX clk enable */ reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR3); reg |= 0x0C00; writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR3); panel_info.epdc_data.working_buf_addr = CONFIG_WORKING_BUF_ADDR; panel_info.epdc_data.waveform_buf_addr = CONFIG_WAVEFORM_BUF_ADDR; panel_info.epdc_data.wv_modes.mode_init = 0; panel_info.epdc_data.wv_modes.mode_du = 1; panel_info.epdc_data.wv_modes.mode_gc4 = 3; panel_info.epdc_data.wv_modes.mode_gc8 = 2; panel_info.epdc_data.wv_modes.mode_gc16 = 2; panel_info.epdc_data.wv_modes.mode_gc32 = 2; panel_info.epdc_data.epdc_timings = panel_timings; setup_epdc_power(); /* Assign fb_base */ gd->fb_base = CONFIG_FB_BASE; }