void init_HW(void)
{
#if defined(USE_PLL) && USE_PLL
setup_flash(6);
init_clocks(true);
setup_flash(5); // 100 MHz
#else
init_clocks(false);
setup_flash(0);
#endif
}
inline void sys_init(){
// Perform basic system initialization
WDOG_disable(myWDog);
CLK_enableAdcClock(myClk);
(*Device_cal)();
// CLK_disableAdcClock(myClk);
//Select the internal oscillator 1 as the clock source
CLK_setOscSrc(myClk, CLK_OscSrc_Internal);
// Setup the PLL for x12 /2 which will yield 50Mhz = 10Mhz * 10 / 2
PLL_setup(myPll, PLL_Multiplier_12, PLL_DivideSelect_ClkIn_by_2);
// Disable the PIE and all interrupts
PIE_disable(myPie);
PIE_disableAllInts(myPie);
CPU_disableGlobalInts(myCpu);
CPU_clearIntFlags(myCpu);
// If running from flash copy RAM only functions to RAM
#ifdef _FLASH
memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize);
setup_flash(myFlash);
#endif
// Setup a debug vector table and enable the PIE
PIE_setDebugIntVectorTable(myPie);
PIE_enable(myPie);
}
void init(void) {
setup_flash();
setup_clocks();
setup_nvic();
systick_init(SYSTICK_RELOAD_VAL);
wirish::priv::board_setup_gpio();
setup_adcs();
setup_timers();
wirish::priv::board_setup_usb();
wirish::priv::series_init();
boardInit();
}
//Initialize functions for the board
//Starts up
void init(void) {
setup_flash();
setup_clocks();
setup_nvic();
systick_init(SYSTICK_RELOAD_VAL);
board_setup_gpio();
setup_timers();
board_setup_usb();
series_init();
disableDebugPorts();
}
/**
* @brief Starts the PLL
*
* Configure and enable PLL. This function uses defines provided in the
* configuration header: PLL_PLLM, PLL_PLLN, PLL_PLLQ, PLL_PLLP.
* Frequencies are calculated as follows:
* Fvco = CRYSTAL * (PLL_PLLN / PLL_PLLM)
* Fsysclk = Fvco / PLL_PLLP
* Fusb = Fsysclk / PLL_PLLQ
* Fahb = Fsysclk
* Fapb1 = Fahb / 4
* Fapb2 = Fahb / 2
*/
void
sysclk_init(void)
{
/* Enable HSE */
RCC->CR |= RCC_CR_HSEON;
/* Configure Flash prior to PLL modifications */
setup_flash();
/* Configure PLL */
RCC->PLLCFGR = (PLL_PLLM << RCC_PLLCFGR_PLLM_bit) |
(PLL_PLLN << RCC_PLLCFGR_PLLN_bit) |
((PLL_PLLP / 2 - 1) << RCC_PLLCFGR_PLLP_bit) |
(PLL_PLLQ << RCC_PLLCFGR_PLLQ_bit) | RCC_PLLCFGR_PLLSRC_HSE;
/*
* Set divisors:
* AHB - no prescaler
* APB1 - divide by 4
* APB2 - divide by 2
*/
RCC->CFGR = RCC_CFGR_PPRE2_DIV2 | RCC_CFGR_PPRE1_DIV4 | RCC_CFGR_HPRE_DIV1;
/* Wait until HSE clock is ready */
while ((RCC->CR & RCC_CR_HSERDY) == 0) {};
/* Enable PLL */
RCC->CR |= RCC_CR_PLLON;
while ((RCC->CR & RCC_CR_PLLRDY) == 0) {};
/* Switch SYSCLK to PLL source */
RCC->CFGR |= RCC_CFGR_SW_PLL;
while (((RCC->CFGR) & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) {};
/* Setup global variables */
g_vco_freq = ((uint64_t)CRYSTAL * (uint64_t)PLL_PLLN) / (uint64_t)PLL_PLLM;
g_sysclk_freq = g_vco_freq / PLL_PLLP;
g_ahb_freq = g_sysclk_freq;
g_apb1_freq = g_ahb_freq / 4;
g_apb2_freq = g_ahb_freq / 2;
}
/*
* main
*/
int main(int argc, char **argv)
{
int vflash_on, result;
//netInitialize();
//udp_printf_init();
printf("%s:%d: start\n", __func__, __LINE__);
vflash_on = is_vflash_on();
printf("%s:%d: vflash %s\n", __func__, __LINE__, vflash_on ? "on" : "off");
if (vflash_on) {
result = setup_vflash();
if (result) {
printf("%s:%d: setup_vflash failed (0x%08x)\n", __func__, __LINE__, result);
goto done;
}
} else {
result = setup_flash();
if (result) {
printf("%s:%d: setup_flash failed (0x%08x)\n", __func__, __LINE__, result);
goto done;
}
}
lv2_sm_ring_buzzer(0x1004, 0xa, 0x1b6);
printf("%s:%d: end\n", __func__, __LINE__);
done:
//udp_printf_deinit();
//netDeinitialize();
return 0;
}
void setup(void) {
setup_urandom();
setup_flash();
}
static int stm32f10x_clock_control_init(struct device *dev)
{
struct stm32f10x_rcc_data *data = dev->driver_data;
volatile struct stm32f10x_rcc *rcc =
(struct stm32f10x_rcc *)(data->base);
/* SYSCLK source defaults to HSI */
int sysclk_src = STM32F10X_RCC_CFG_SYSCLK_SRC_HSI;
u32_t hpre =
ahb_prescaler(CONFIG_CLOCK_STM32F10X_CONN_LINE_AHB_PRESCALER);
u32_t ppre1 =
apb_prescaler(CONFIG_CLOCK_STM32F10X_CONN_LINE_APB1_PRESCALER);
u32_t ppre2 =
apb_prescaler(CONFIG_CLOCK_STM32F10X_CONN_LINE_APB2_PRESCALER);
#ifdef CONFIG_CLOCK_STM32F10X_CONN_LINE_PLL_MULTIPLIER
u32_t pll_mul =
pllmul(CONFIG_CLOCK_STM32F10X_CONN_LINE_PLL_MULTIPLIER);
#endif /* CONFIG_CLOCK_STM32F10X_CONN_LINE_PLL_MULTIPLIER */
#ifdef CONFIG_CLOCK_STM32F10X_CONN_LINE_PLL2_MULTIPLIER
u32_t pll2_mul =
pll2mul(CONFIG_CLOCK_STM32F10X_CONN_LINE_PLL2_MULTIPLIER);
#endif /* CONFIG_CLOCK_STM32F10X_CONN_LINE_PLL2_MULTIPLIER */
#ifdef CONFIG_CLOCK_STM32F10X_CONN_LINE_PREDIV1
u32_t prediv1 =
prediv_prescaler(CONFIG_CLOCK_STM32F10X_CONN_LINE_PREDIV1);
#endif /* CONFIG_CLOCK_STM32F10X_CONN_LINE_PREDIV1 */
#ifdef CONFIG_CLOCK_STM32F10X_CONN_LINE_PREDIV2
u32_t prediv2 =
prediv_prescaler(CONFIG_CLOCK_STM32F10X_CONN_LINE_PREDIV2);
#endif /* CLOCK_STM32F10X_CONN_LINE_PREDIV2 */
/* disable PLLs */
rcc->cr.bit.pllon = 0;
rcc->cr.bit.pll2on = 0;
rcc->cr.bit.pll3on = 0;
/* disable HSE */
rcc->cr.bit.hseon = 0;
#ifdef CONFIG_CLOCK_STM32F10X_CONN_LINE_HSE_BYPASS
/* HSE is disabled, HSE bypass can be enabled*/
rcc->cr.bit.hsebyp = 1;
#endif /* CONFIG_CLOCK_STM32F10X_CONN_LINE_HSE_BYPASS */
#ifdef CONFIG_CLOCK_STM32F10X_CONN_LINE_PLL_SRC_HSI
/* enable HSI clock */
rcc->cr.bit.hsion = 1;
/* this should end after one test */
while (rcc->cr.bit.hsirdy != 1) {
}
/* HSI oscillator clock / 2 selected as PLL input clock */
rcc->cfgr.bit.pllsrc = STM32F10X_RCC_CFG_PLL_SRC_HSI;
#endif /* CONFIG_CLOCK_STM32F10X_PLL_SRC_HSI */
#ifdef CONFIG_CLOCK_STM32F10X_CONN_LINE_PLL_SRC_PREDIV1
/* wait for to become ready */
rcc->cr.bit.hseon = 1;
while (rcc->cr.bit.hserdy != 1) {
}
rcc->cfgr2.bit.prediv1 = prediv1;
/* Clock from PREDIV1 selected as PLL input clock */
rcc->cfgr.bit.pllsrc = STM32F10X_RCC_CFG_PLL_SRC_PREDIV1;
#ifdef CONFIG_CLOCK_STM32F10X_CONN_LINE_PREDIV1_SRC_HSE
/* HSE oscillator clock selected as PREDIV1 clock entry */
rcc->cfgr2.bit.prediv1src = STM32F10X_RCC_CFG2_PREDIV1_SRC_HSE;
#else
/* PLL2 selected as PREDIV1 clock entry */
rcc->cfgr2.bit.prediv1src = STM32F10X_RCC_CFG2_PREDIV1_SRC_PLL2;
rcc->cfgr2.bit.prediv2 = prediv2;
rcc->cfgr2.bit.pll2mul = pll2_mul;
/* enable PLL2 */
rcc->cr.bit.pll2on = 1;
/* wait for PLL to become ready */
while (rcc->cr.bit.pll2rdy != 1) {
}
#endif /* CONFIG_CLOCK_STM32F10X_CONN_LINE_PREDIV1_SRC_HSE */
#endif /* CONFIG_CLOCK_STM32F10X_CONN_LINE_PLL_SRC_PREDIV1 */
/* setup AHB prescaler */
rcc->cfgr.bit.hpre = hpre;
/* setup APB1, must not exceed 36MHz */
rcc->cfgr.bit.ppre1 = ppre1;
/* setup APB2 */
rcc->cfgr.bit.ppre2 = ppre2;
#ifdef CONFIG_CLOCK_STM32F10X_CONN_LINE_SYSCLK_SRC_HSI
/* enable HSI clock */
rcc->cr.bit.hsion = 1;
/* this should end after one test */
while (rcc->cr.bit.hsirdy != 1) {
}
sysclk_src = STM32F10X_RCC_CFG_SYSCLK_SRC_HSI;
#elif defined(CONFIG_CLOCK_STM32F10X_SYSCLK_SRC_HSE)
/* enable HSE clock */
rcc->cr.bit.hseon = 1;
/* wait for to become ready */
while (rcc->cr.bit.hserdy != 1) {
}
sysclk_src = STM32F10X_RCC_CFG_SYSCLK_SRC_HSE;
#elif defined(CONFIG_CLOCK_STM32F10X_CONN_LINE_SYSCLK_SRC_PLLCLK)
/* setup PLL multiplication (PLL must be disabled) */
rcc->cfgr.bit.pllmul = pll_mul;
/* enable PLL */
rcc->cr.bit.pllon = 1;
/* wait for PLL to become ready */
while (rcc->cr.bit.pllrdy != 1) {
}
sysclk_src = STM32F10X_RCC_CFG_SYSCLK_SRC_PLL;
#endif /* CONFIG_CLOCK_STM32F10X_CONN_LINE_SYSCLK_SRC_HSI */
/* configure flash access latency before SYSCLK source
* switch
*/
setup_flash();
/* set SYSCLK clock value */
rcc->cfgr.bit.sw = sysclk_src;
/* wait for SYSCLK to switch the source */
while (rcc->cfgr.bit.sws != sysclk_src) {
}
return 0;
}
