int board_eth_init(bd_t *bis) { setup_iomux_fec(CONFIG_FEC_ENET_DEV); return fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV, CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); }
int board_early_init_f(void) { setup_iomux_uart(); setup_iomux_fec(); return 0; }
int board_early_init_f(void) { setup_iomux_uart(); setup_iomux_fec(); #ifdef CONFIG_USB_EHCI_MX5 setup_usb_h1(); #endif return 0; }
int board_eth_init(bd_t *bis) { int ret; setup_iomux_fec(); ret = cpu_eth_init(bis); if (ret) printf("FEC MXC: %s:failed\n", __func__); return 0; }
int board_eth_init(bd_t *bis) { int ret; setup_iomux_fec(CONFIG_FEC_ENET_DEV); ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV, CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); if (ret) printf("FEC%d MXC: %s:failed\n", CONFIG_FEC_ENET_DEV, __func__); return 0; }
int board_init(void) { system_rev = get_cpu_rev(); gd->bd->bi_arch_number = MACH_TYPE_MX51_BABBAGE; /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; setup_iomux_uart(); setup_iomux_fec(); return 0; }
int board_early_init_f(void) { struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; /* setup GPIO3_1 to set HighVCore signal */ imx_iomux_v3_setup_pad(MX35_PAD_ATA_DA1__GPIO3_1); gpio_direction_output(65, 1); /* initialize PLL and clock configuration */ writel(CCM_CCMR_CONFIG, &ccm->ccmr); writel(CCM_MPLL_532_HZ, &ccm->mpctl); writel(CCM_PPLL_300_HZ, &ccm->ppctl); /* Set the core to run at 532 Mhz */ writel(0x00001000, &ccm->pdr0); /* Set-up RAM */ board_setup_sdram(); /* enable clocks */ writel(readl(&ccm->cgr0) | MXC_CCM_CGR0_EMI_MASK | MXC_CCM_CGR0_EDIO_MASK | MXC_CCM_CGR0_EPIT1_MASK, &ccm->cgr0); writel(readl(&ccm->cgr1) | MXC_CCM_CGR1_FEC_MASK | MXC_CCM_CGR1_GPIO1_MASK | MXC_CCM_CGR1_GPIO2_MASK | MXC_CCM_CGR1_GPIO3_MASK | MXC_CCM_CGR1_I2C1_MASK | MXC_CCM_CGR1_I2C2_MASK | MXC_CCM_CGR1_I2C3_MASK, &ccm->cgr1); /* Set-up NAND */ __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr); /* Set pinmux for the required peripherals */ setup_iomux_uart3(); setup_iomux_i2c(); setup_iomux_fec(); setup_iomux_spi(); return 0; }
int board_early_init_f(void) { setup_iomux_uart(); setup_iomux_fec(); setup_iomux_i2c(); setup_iomux_nand(); setup_iomux_video(); m53_set_clock(); mxc_set_sata_internal_clock(); /* NAND clock @ 33MHz */ m53_set_nand(); return 0; }
static int setup_fec(void) { struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; int ret; setup_iomux_fec(); /* provide the PHY clock from the i.MX 6 */ ret = enable_fec_anatop_clock(1, ENET_50MHZ); if (ret) return ret; /* Use 50M anatop REF_CLK and output it on the ENET2_TX_CLK */ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK, IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); return 0; }
int board_eth_init(bd_t *bis) { setup_iomux_fec(); return cpu_eth_init(bis); }