/**
* send USB data (IN device transaction)
*
* So far this function is specialized for EP 0 only.
*
* Returns: size to be transfered, or -1 on error.
*/
int
usb_tx(struct usbd_ep_pipe_state_t *s, const void *buf, size_t len, size_t reqlen, ep_callback_t cb, void *cb_data)
{
setup_tx(s, buf, len, reqlen, cb, cb_data);
submit_tx(s);
return (s->transfer_size);
}
int
usb_ep0_tx_cp(const void *buf, size_t len, size_t reqlen, ep_callback_t cb, void *cb_data)
{
struct usbd_ep_pipe_state_t *s = &usbd_pipe_state[USBD_PIPE_EP0_TX];
enum usb_ep_pingpong pp = s->pingpong;
setup_tx(s, ep0_buf[pp], len, reqlen, cb, cb_data);
s->copy_source = buf;
submit_tx(s);
return (s->transfer_size);
}
int
main(void)
{
u2_init();
putstr("\nFactory Test\n");
print_mac_addr(ethernet_mac_addr()->addr);
newline();
if(test_sd())
puts("SD OK\n");
else {
puts("SD FAIL\n");
// hal_finish();
//return 0;
}
if(test_ram())
puts("RAM OK\n");
else {
puts("RAM FAIL\n");
hal_finish();
return 0;
}
print_mac_addr(ethernet_mac_addr()->addr);
newline();
output_regs->led_src = 0x7; // make bottom 3 controlled by HW
ethernet_register_link_changed_callback(link_changed_callback);
ethernet_init();
clocks_enable_tx_dboard(true,1);
clocks_mimo_config(MC_WE_LOCK_TO_SMA);
#if 0
// make bit 15 of Tx gpio's be a s/w output
hal_gpio_set_sel(GPIO_TX_BANK, 15, 's');
hal_gpio_set_ddr(GPIO_TX_BANK, 0x8000, 0x8000);
#endif
output_regs->debug_mux_ctrl = 1;
#if 0
hal_gpio_set_sels(GPIO_TX_BANK, "1111111111111111");
hal_gpio_set_sels(GPIO_RX_BANK, "1111111111111111");
hal_gpio_set_ddr(GPIO_TX_BANK, 0xffff, 0xffff);
hal_gpio_set_ddr(GPIO_RX_BANK, 0xffff, 0xffff);
#endif
// initialize double buffering state machine for ethernet -> DSP Tx
dbsm_init(&dsp_tx_sm, DSP_TX_BUF_0,
&dsp_tx_recv_args, &dsp_tx_send_args,
eth_pkt_inspector);
// initialize double buffering state machine for DSP RX -> Ethernet
if (FW_SETS_SEQNO){
dbsm_init(&dsp_rx_sm, DSP_RX_BUF_0,
&dsp_rx_recv_args, &dsp_rx_send_args,
fw_sets_seqno_inspector);
}
else {
dbsm_init(&dsp_rx_sm, DSP_RX_BUF_0,
&dsp_rx_recv_args, &dsp_rx_send_args,
dbsm_nop_inspector);
}
// tell app_common that this dbsm could be sending to the ethernet
ac_could_be_sending_to_eth = &dsp_rx_sm;
// program tx registers
setup_tx();
// kick off the state machine
dbsm_start(&dsp_tx_sm);
//int which = 0;
while(1){
// hal_gpio_write(GPIO_TX_BANK, which, 0x8000);
// which ^= 0x8000;
buffer_irq_handler(0);
int pending = pic_regs->pending; // poll for under or overrun
if (pending & PIC_UNDERRUN_INT){
dbsm_handle_tx_underrun(&dsp_tx_sm);
pic_regs->pending = PIC_UNDERRUN_INT; // clear interrupt
putchar('U');
}
if (pending & PIC_OVERRUN_INT){
dbsm_handle_rx_overrun(&dsp_rx_sm);
pic_regs->pending = PIC_OVERRUN_INT; // clear pending interrupt
// FIXME Figure out how to handle this robustly.
// Any buffers that are emptying should be allowed to drain...
if (streaming_p){
// restart_streaming();
// FIXME report error
}
else {
// FIXME report error
}
putchar('O');
}
}
}
int
main(void)
{
u2_init();
output_regs->led_src = 0x3; // h/w controls bottom two bits
clocks_enable_test_clk(true, 1);
putstr("\nMIMO Tx Slave\n");
cpu_tx_buf_dest_port = PORT_SERDES;
// ethernet_register_link_changed_callback(link_changed_callback);
// ethernet_init();
clocks_mimo_config(MC_WE_LOCK_TO_MIMO);
// puts("post clocks_mimo_config");
#if 0
// make bit 15 of Tx gpio's be a s/w output
hal_gpio_set_sel(GPIO_TX_BANK, 15, 's');
hal_gpio_set_ddr(GPIO_TX_BANK, 0x8000, 0x8000);
#endif
#if 0
output_regs->debug_mux_ctrl = 1;
hal_gpio_set_sels(GPIO_TX_BANK, "0000000000000000");
hal_gpio_set_sels(GPIO_RX_BANK, "0000000000000000");
hal_gpio_set_ddr(GPIO_TX_BANK, 0xffff, 0xffff);
hal_gpio_set_ddr(GPIO_RX_BANK, 0xffff, 0xffff);
#endif
// initialize double buffering state machine for ethernet -> DSP Tx
dbsm_init(&dsp_tx_sm, DSP_TX_BUF_0,
&dsp_tx_recv_args, &dsp_tx_send_args,
eth_pkt_inspector);
//output_regs->flush_icache = 1;
// initialize double buffering state machine for DSP RX -> Ethernet
if (FW_SETS_SEQNO){
dbsm_init(&dsp_rx_sm, DSP_RX_BUF_0,
&dsp_rx_recv_args, &dsp_rx_send_args,
fw_sets_seqno_inspector);
}
else {
dbsm_init(&dsp_rx_sm, DSP_RX_BUF_0,
&dsp_rx_recv_args, &dsp_rx_send_args,
dbsm_nop_inspector);
}
// puts("post dbsm_init's");
// tell app_common that this dbsm could be sending to the ethernet
ac_could_be_sending_to_eth = &dsp_rx_sm;
// program tx registers
setup_tx();
// puts("post setup_tx");
// kick off the state machine
dbsm_start(&dsp_tx_sm);
// puts("post dbsm_start");
//int which = 0;
while(1){
// hal_gpio_write(GPIO_TX_BANK, which, 0x8000);
// which ^= 0x8000;
buffer_irq_handler(0);
int pending = pic_regs->pending; // poll for under or overrun
if (pending & PIC_UNDERRUN_INT){
dbsm_handle_tx_underrun(&dsp_tx_sm);
pic_regs->pending = PIC_UNDERRUN_INT; // clear interrupt
putchar('U');
}
if (pending & PIC_OVERRUN_INT){
dbsm_handle_rx_overrun(&dsp_rx_sm);
pic_regs->pending = PIC_OVERRUN_INT; // clear pending interrupt
// FIXME Figure out how to handle this robustly.
// Any buffers that are emptying should be allowed to drain...
if (streaming_p){
// restart_streaming();
// FIXME report error
}
else {
// FIXME report error
}
putchar('O');
}
}
}
int main(int argc, char *argv[]) {
struct epoll_event ev;
cfg.prog = argv[0];
int n,opt;
while ( (opt=getopt(argc,argv,"vi:o:hPV:s:D:")) != -1) {
switch(opt) {
case 'v': cfg.verbose++; break;
case 'i': cfg.idev=strdup(optarg); break;
case 'o': cfg.odev=strdup(optarg); break;
case 'P': cfg.nopromisc=1; break;
case 'V': cfg.vlan=atoi(optarg); break;
case 's': cfg.snaplen=atoi(optarg); break;
case 'D': cfg.tail=atoi(optarg); break;
case 'h': default: usage(); break;
}
}
/* block all signals. we take signals synchronously via signalfd */
sigset_t all;
sigfillset(&all);
sigprocmask(SIG_SETMASK,&all,NULL);
/* a few signals we'll accept via our signalfd */
sigset_t sw;
sigemptyset(&sw);
for(n=0; n < sizeof(sigs)/sizeof(*sigs); n++) sigaddset(&sw, sigs[n]);
/* create the signalfd for receiving signals */
cfg.signal_fd = signalfd(-1, &sw, 0);
if (cfg.signal_fd == -1) {
fprintf(stderr,"signalfd: %s\n", strerror(errno));
goto done;
}
/* set up the raw socket */
if (setup_rx() < 0) goto done;
if (setup_tx() < 0) goto done;
/* set up the epoll instance */
cfg.epoll_fd = epoll_create(1);
if (cfg.epoll_fd == -1) {
fprintf(stderr,"epoll: %s\n", strerror(errno));
goto done;
}
/* add descriptors of interest */
if (new_epoll(EPOLLIN, cfg.signal_fd)) goto done; // signals
if (new_epoll(EPOLLIN, cfg.rx_fd)) goto done; // packets
alarm(1);
while (epoll_wait(cfg.epoll_fd, &ev, 1, -1) > 0) {
if (cfg.verbose > 1) fprintf(stderr,"epoll reports fd %d\n", ev.data.fd);
if (ev.data.fd == cfg.signal_fd) { if (handle_signal() < 0) goto done; }
else if (ev.data.fd == cfg.rx_fd) { if (handle_packet() < 0) goto done; }
}
done:
if (cfg.rx_fd != -1) close(cfg.rx_fd);
if (cfg.signal_fd != -1) close(cfg.signal_fd);
if (cfg.epoll_fd != -1) close(cfg.epoll_fd);
return 0;
}
