/*
* sfi_platform_init(): register lapics & io-apics
*/
int __init sfi_platform_init(void)
{
#ifdef CONFIG_X86_LOCAL_APIC
mp_sfi_register_lapic_address(sfi_lapic_addr);
sfi_table_parse(SFI_SIG_CPUS, NULL, NULL, sfi_parse_cpus);
#endif
#ifdef CONFIG_X86_IO_APIC
sfi_table_parse(SFI_SIG_APIC, NULL, NULL, sfi_parse_ioapic);
#endif
return 0;
}
static int __init sfi_cpufreq_init(void)
{
int ret, i;
/* parse the freq table from SFI */
ret = sfi_table_parse(SFI_SIG_FREQ, NULL, NULL, sfi_parse_freq);
if (ret)
return ret;
freq_table = kzalloc(sizeof(*freq_table) *
(num_freq_table_entries + 1), GFP_KERNEL);
if (!freq_table) {
ret = -ENOMEM;
goto err_free_array;
}
for (i = 0; i < num_freq_table_entries; i++) {
freq_table[i].driver_data = i;
freq_table[i].frequency = sfi_cpufreq_array[i].freq_mhz * 1000;
}
freq_table[i].frequency = CPUFREQ_TABLE_END;
ret = cpufreq_register_driver(&sfi_cpufreq_driver);
if (ret)
goto err_free_tbl;
return ret;
err_free_tbl:
kfree(freq_table);
err_free_array:
kfree(sfi_cpufreq_array);
return ret;
}
/*
* sfi_platform_init(): register lapics & io-apics
*/
int __init sfi_platform_init(void)
{
#ifdef CONFIG_XEN
/* FIXME: reserve IRQs based on hypervisor's IOAPIC info */
gsi_top += 100;
return;
#endif
#ifdef CONFIG_X86_LOCAL_APIC
register_lapic_address(sfi_lapic_addr);
sfi_table_parse(SFI_SIG_CPUS, NULL, NULL, sfi_parse_cpus);
#endif
#ifdef CONFIG_X86_IO_APIC
sfi_table_parse(SFI_SIG_APIC, NULL, NULL, sfi_parse_ioapic);
#endif
return 0;
}
int __init sfi_acpi_init(void)
{
struct sfi_table_key xsdt_key = { .sig = SFI_SIG_XSDT };
sfi_table_parse(SFI_SIG_XSDT, NULL, NULL, sfi_acpi_parse_xsdt);
xsdt_va = (struct acpi_table_xsdt *)sfi_get_table(&xsdt_key);
return 0;
}
/*
* handle_sfi_table() - Finds the SFI table with given signature and
* runs handler() on it.
*/
int handle_sfi_table(char *signature, char *oem_id, char *oem_table_id,
sfi_table_handler handler)
{
int ret = -EINVAL;
ret = sfi_table_parse(signature, oem_id, oem_table_id, handler);
if (ret) {
pr_err("Failed to parse %s SFI table\n", signature);
ret = fix_sfi_table(signature, handler);
}
return ret;
}
void __init intel_mid_rtc_init(void)
{
unsigned long vrtc_paddr;
sfi_table_parse(SFI_SIG_MRTC, NULL, NULL, sfi_parse_mrtc);
vrtc_paddr = sfi_mrtc_array[0].phys_addr;
if (!sfi_mrtc_num || !vrtc_paddr)
return;
vrtc_virt_base = (void __iomem *)set_fixmap_offset_nocache(FIX_LNW_VRTC,
vrtc_paddr);
x86_platform.get_wallclock = vrtc_get_time;
x86_platform.set_wallclock = vrtc_set_mmss;
}
static void __init intel_mid_time_init(void)
{
sfi_table_parse(SFI_SIG_MTMR, NULL, NULL, sfi_parse_mtmr);
switch (intel_mid_timer_options) {
case INTEL_MID_TIMER_APBT_ONLY:
break;
case INTEL_MID_TIMER_LAPIC_APBT:
/* Use apbt and local apic */
x86_init.timers.setup_percpu_clockev = intel_mid_setup_bp_timer;
x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock;
return;
default:
if (!boot_cpu_has(X86_FEATURE_ARAT))
break;
/* Lapic only, no apbt */
x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock;
x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock;
return;
}
x86_init.timers.setup_percpu_clockev = apbt_time_init;
}
static void __init intel_mid_time_init(void)
{
#ifdef CONFIG_SFI
sfi_table_parse(SFI_SIG_MTMR, NULL, NULL, sfi_parse_mtmr);
#endif
switch (intel_mid_timer_options) {
case INTEL_MID_TIMER_APBT_ONLY:
break;
case INTEL_MID_TIMER_LAPIC_APBT:
x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock;
x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock;
break;
default:
if (!boot_cpu_has(X86_FEATURE_ARAT))
break;
x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock;
x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock;
return;
}
/* we need at least one APB timer */
pre_init_apic_IRQ0();
apbt_time_init();
}
int mdfld_dsi_h8c7_panel_reset(struct mdfld_dsi_config *dsi_config,
int reset_from)
{
struct mdfld_dsi_hw_registers *regs;
struct mdfld_dsi_hw_context *ctx;
struct drm_device *dev;
int ret = 0;
bool b_gpio_required[PSB_NUM_PIPE] = {0};
unsigned gpio_mipi_panel_reset = 128;
regs = &dsi_config->regs;
ctx = &dsi_config->dsi_hw_context;
dev = dsi_config->dev;
if (IS_CTP(dev)) {
sfi_table_parse(SFI_SIG_GPIO, NULL, NULL, mdfld_mipi_panel_gpio_parse);
gpio_mipi_panel_reset = mdfld_mipi_panel_gpio_reset;
}
if (reset_from == RESET_FROM_BOOT_UP) {
b_gpio_required[dsi_config->pipe] = false;
if (dsi_config->pipe) {
PSB_DEBUG_ENTRY(
"GPIO reset for MIPIC is skipped!\n");
goto fun_exit;
}
ret = gpio_request(gpio_mipi_panel_reset, "gfx");
if (ret) {
DRM_ERROR(
"Failed to request gpio %d\n", gpio_mipi_panel_reset);
goto err;
}
b_gpio_required[dsi_config->pipe] = true;
/* for get date from panel side is not easy,
so here use display side setting to judge
wheather panel have enabled or not by FW */
if ((REG_READ(regs->dpll_reg) & BIT31) &&
(REG_READ(regs->pipeconf_reg) & BIT30) &&
(REG_READ(regs->mipi_reg) & BIT31)) {
PSB_DEBUG_ENTRY(
"FW has initialized the panel, skip reset during boot up\n.");
psb_enable_vblank(dev, dsi_config->pipe);
goto fun_exit;
}
}
if (b_gpio_required[dsi_config->pipe]) {
gpio_direction_output(gpio_mipi_panel_reset, 0);
gpio_set_value_cansleep(gpio_mipi_panel_reset, 0);
/*reset low level width 11ms*/
mdelay(10);
gpio_direction_output(gpio_mipi_panel_reset, 1);
gpio_set_value_cansleep(gpio_mipi_panel_reset, 1);
/*reset time 5ms*/
mdelay(5);
} else {
PSB_DEBUG_ENTRY("pr2 panel reset fail.!");
}
fun_exit:
if (b_gpio_required[dsi_config->pipe])
PSB_DEBUG_ENTRY("pr2 panel reset successfull.");
return 0;
err:
gpio_free(gpio_mipi_panel_reset);
PSB_DEBUG_ENTRY("pr2 panel reset fail.!");
return 0;
}
