static int __sh_tmu_enable(struct sh_tmu_channel *ch) { int ret; /* enable clock */ ret = clk_enable(ch->tmu->clk); if (ret) { dev_err(&ch->tmu->pdev->dev, "ch%u: cannot enable clock\n", ch->index); return ret; } /* make sure channel is disabled */ sh_tmu_start_stop_ch(ch, 0); /* maximum timeout */ sh_tmu_write(ch, TCOR, 0xffffffff); sh_tmu_write(ch, TCNT, 0xffffffff); /* configure channel to parent clock / 4, irq off */ ch->rate = clk_get_rate(ch->tmu->clk) / 4; sh_tmu_write(ch, TCR, TCR_TPSC_CLK4); /* enable channel */ sh_tmu_start_stop_ch(ch, 1); return 0; }
static int sh_tmu_enable(struct sh_tmu_priv *p) { int ret; /* enable clock */ ret = clk_enable(p->clk); if (ret) { dev_err(&p->pdev->dev, "cannot enable clock\n"); return ret; } /* make sure channel is disabled */ sh_tmu_start_stop_ch(p, 0); /* maximum timeout */ sh_tmu_write(p, TCOR, 0xffffffff); sh_tmu_write(p, TCNT, 0xffffffff); /* configure channel to parent clock / 4, irq off */ p->rate = clk_get_rate(p->clk) / 4; sh_tmu_write(p, TCR, 0x0000); /* enable channel */ sh_tmu_start_stop_ch(p, 1); return 0; }
static int sh_tmu_enable(struct sh_tmu_priv *p) { struct sh_timer_config *cfg = p->pdev->dev.platform_data; int ret; /* enable clock */ ret = clk_enable(p->clk); if (ret) { pr_err("sh_tmu: cannot enable clock \"%s\"\n", cfg->clk); return ret; } /* make sure channel is disabled */ sh_tmu_start_stop_ch(p, 0); /* maximum timeout */ sh_tmu_write(p, TCOR, 0xffffffff); sh_tmu_write(p, TCNT, 0xffffffff); /* configure channel to parent clock / 4, irq off */ p->rate = clk_get_rate(p->clk) / 4; sh_tmu_write(p, TCR, 0x0000); /* enable channel */ sh_tmu_start_stop_ch(p, 1); return 0; }
static void sh_timer_stop(void *priv) { struct sh_tmu_priv *p = priv; sh_tmu_start_stop_ch(p, 0); sh_tmu_write(p, TCR, 0x0000); }
static void __sh_tmu_disable(struct sh_tmu_channel *ch) { /* disable channel */ sh_tmu_start_stop_ch(ch, 0); /* disable interrupts in TMU block */ sh_tmu_write(ch, TCR, TCR_TPSC_CLK4); /* stop clock */ clk_disable(ch->tmu->clk); }
static void sh_tmu_disable(struct sh_tmu_priv *p) { /* disable channel */ sh_tmu_start_stop_ch(p, 0); /* disable interrupts in TMU block */ sh_tmu_write(p, TCR, 0x0000); /* stop clock */ clk_disable(p->clk); }
static void sh_tmu_set_next(struct sh_tmu_channel *ch, unsigned long delta, int periodic) { /* stop timer */ sh_tmu_start_stop_ch(ch, 0); /* acknowledge interrupt */ sh_tmu_read(ch, TCR); /* enable interrupt */ sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4); /* reload delta value in case of periodic timer */ if (periodic) sh_tmu_write(ch, TCOR, delta); else sh_tmu_write(ch, TCOR, 0xffffffff); sh_tmu_write(ch, TCNT, delta); /* start timer */ sh_tmu_start_stop_ch(ch, 1); }
static void sh_tmu_set_next(struct sh_tmu_priv *p, unsigned long delta, int periodic) { /* stop timer */ sh_tmu_start_stop_ch(p, 0); /* acknowledge interrupt */ sh_tmu_read(p, TCR); /* enable interrupt */ sh_tmu_write(p, TCR, 0x0020); /* reload delta value in case of periodic timer */ if (periodic) sh_tmu_write(p, TCOR, delta); else sh_tmu_write(p, TCOR, 0xffffffff); sh_tmu_write(p, TCNT, delta); /* start timer */ sh_tmu_start_stop_ch(p, 1); }