float64 syst_float64_div( float64 a, float64 b )
{
float64 z;
sim_fpu A;
sim_fpu B;
sim_fpu ans;
sim_fpu_64to (&A, a);
sim_fpu_64to (&B, b);
#if 0
sim_fpu_print_fpu (&A, (sim_fpu_print_func*) fprintf, stdout);
fprintf (stdout, " + ");
sim_fpu_print_fpu (&B, (sim_fpu_print_func*) fprintf, stdout);
fprintf (stdout, " = ");
#endif
flags |= sim_fpu_div (&ans, &A, &B);
#if 0
sim_fpu_print_fpu (&ans, (sim_fpu_print_func*) fprintf, stdout);
#endif
flags |= sim_fpu_round_64 (&ans, rounding_mode, 0);
#if 0
sim_fpu_print_status (flags, (sim_fpu_print_func*) fprintf, stdout);
fprintf (stdout, "\n");
#endif
sim_fpu_to64 (&z, &ans);
return z;
}
/* Implement a 32/64 bit FP div, setting FP exception bits when
appropriate. */
void
fpu_div (SIM_DESC sd, sim_cpu *cpu, sim_cia cia,
const void *reg_in1, const void *reg_in2,
void *reg_out, const struct fp_prec_t *ops)
{
sim_fpu m, n, r;
REG2VAL (reg_in1, &m);
REG2VAL (reg_in2, &n);
ROUND (&m);
ROUND (&n);
FPCR &= ~ EC_MASK;
if (sim_fpu_is_snan (&m) || sim_fpu_is_snan (&n)
|| (sim_fpu_is_infinity (&m) && sim_fpu_is_infinity (&n))
|| (sim_fpu_is_zero (&m) && sim_fpu_is_zero (&n)))
{
if (FPCR & EE_V)
FPCR |= EC_V;
else
VAL2REG (&sim_fpu_qnan, reg_out);
}
else if (sim_fpu_is_number (&m) && sim_fpu_is_zero (&n)
&& (FPCR & EE_Z))
FPCR |= EC_Z;
else
{
sim_fpu_status stat = sim_fpu_div (&r, &m, &n);
stat |= ROUND (&r);
if (fpu_status_ok (stat))
VAL2REG (&r, reg_out);
}
fpu_check_signal_exception (sd, cpu, cia);
}
SF
sh64_fdivs(SIM_CPU *current_cpu, SF frg, SF frh)
{
SF result;
sim_fpu f1, f2, fres;
sim_fpu_32to (&f1, frg);
sim_fpu_32to (&f2, frh);
sim_fpu_div (&fres, &f1, &f2);
sim_fpu_to32 (&result, &fres);
return result;
}
DF
sh64_fdivd(SIM_CPU *current_cpu, DF drg, DF drh)
{
DF result;
sim_fpu f1, f2, fres;
sim_fpu_64to (&f1, drg);
sim_fpu_64to (&f2, drh);
sim_fpu_div (&fres, &f1, &f2);
sim_fpu_to64 (&result, &fres);
return result;
}
float32 syst_float32_div( float32 a, float32 b )
{
float32 z;
sim_fpu A;
sim_fpu B;
sim_fpu ans;
sim_fpu_32to (&A, a);
sim_fpu_32to (&B, b);
flags |= sim_fpu_div (&ans, &A, &B);
flags |= sim_fpu_round_32 (&ans, rounding_mode, 0);
sim_fpu_to32 (&z, &ans);
return z;
}
static SF
divsf (CGEN_FPU* fpu, SF x, SF y)
{
sim_fpu op1;
sim_fpu op2;
sim_fpu ans;
unsigned32 res;
sim_fpu_status status;
sim_fpu_32to (&op1, x);
sim_fpu_32to (&op2, y);
status = sim_fpu_div (&ans, &op1, &op2);
if (status != 0)
(*fpu->ops->error) (fpu, status);
sim_fpu_to32 (&res, &ans);
return res;
}
static DF
divdf (CGEN_FPU* fpu, DF x, DF y)
{
sim_fpu op1;
sim_fpu op2;
sim_fpu ans;
unsigned64 res;
sim_fpu_status status;
sim_fpu_64to (&op1, x);
sim_fpu_64to (&op2, y);
status = sim_fpu_div (&ans, &op1, &op2);
if (status != 0)
(*fpu->ops->error) (fpu, status);
sim_fpu_to64 (&res, &ans);
return res;
}