void sim_board_reset (SIM_DESC sd) { struct hw *hw_cpu; sim_cpu *cpu; const struct bfd_arch_info *arch; const char *cpu_type; cpu = STATE_CPU (sd, 0); arch = STATE_ARCHITECTURE (sd); /* hw_cpu = sim_hw_parse (sd, "/"); */ if (arch->arch == bfd_arch_m68hc11) { cpu->cpu_type = CPU_M6811; cpu_type = "/m68hc11"; } else { cpu->cpu_type = CPU_M6812; cpu_type = "/m68hc12"; } hw_cpu = sim_hw_parse (sd, cpu_type); if (hw_cpu == 0) { sim_io_eprintf (sd, "%s cpu not found in device tree.", cpu_type); return; } cpu_reset (cpu); hw_port_event (hw_cpu, 3, 0); cpu_restart (cpu); }
/* Give some information about the simulator. */ static void sim_get_info (SIM_DESC sd, char *cmd) { sim_cpu *cpu; cpu = STATE_CPU (sd, 0); if (cmd != 0 && (cmd[0] == ' ' || cmd[0] == '-')) { int i; struct hw *hw_dev; struct sim_info_list *dev_list; const struct bfd_arch_info *arch; arch = STATE_ARCHITECTURE (sd); cmd++; if (arch->arch == bfd_arch_m68hc11) dev_list = dev_list_68hc11; else dev_list = dev_list_68hc12; for (i = 0; dev_list[i].name; i++) if (strcmp (cmd, dev_list[i].name) == 0) break; if (dev_list[i].name == 0) { sim_io_eprintf (sd, "Device '%s' not found.\n", cmd); sim_io_eprintf (sd, "Valid devices: cpu timer sio eeprom\n"); return; } hw_dev = sim_hw_parse (sd, dev_list[i].device); if (hw_dev == 0) { sim_io_eprintf (sd, "Device '%s' not found\n", dev_list[i].device); return; } hw_ioctl (hw_dev, 23, 0); return; } cpu_info (sd, cpu); interrupts_info (sd, &cpu->cpu_interrupts); }
static int sim_hw_configure (SIM_DESC sd) { const struct bfd_arch_info *arch; struct hw *device_tree; sim_cpu *cpu; arch = STATE_ARCHITECTURE (sd); if (arch == 0) return 0; cpu = STATE_CPU (sd, 0); cpu->cpu_configured_arch = arch; device_tree = sim_hw_parse (sd, "/"); if (arch->arch == bfd_arch_m68hc11) { cpu->cpu_interpretor = cpu_interp_m6811; if (hw_tree_find_property (device_tree, "/m68hc11/reg") == 0) { /* Allocate core managed memory */ /* the monitor */ sim_do_commandf (sd, "memory region 0x%lx@%d,0x%lx", /* MONITOR_BASE, MONITOR_SIZE */ 0x8000, M6811_RAM_LEVEL, 0x8000); sim_do_commandf (sd, "memory region 0x000@%d,0x8000", M6811_RAM_LEVEL); sim_hw_parse (sd, "/m68hc11/reg 0x1000 0x03F"); if (cpu->bank_start < cpu->bank_end) { sim_do_commandf (sd, "memory region 0x%lx@%d,0x100000", cpu->bank_virtual, M6811_RAM_LEVEL); sim_hw_parse (sd, "/m68hc11/use_bank 1"); } } if (cpu->cpu_start_mode) { sim_hw_parse (sd, "/m68hc11/mode %s", cpu->cpu_start_mode); } if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11sio/reg") == 0) { sim_hw_parse (sd, "/m68hc11/m68hc11sio/reg 0x2b 0x5"); sim_hw_parse (sd, "/m68hc11/m68hc11sio/backend stdio"); sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11sio"); } if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11tim/reg") == 0) { /* M68hc11 Timer configuration. */ sim_hw_parse (sd, "/m68hc11/m68hc11tim/reg 0x1b 0x5"); sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11tim"); sim_hw_parse (sd, "/m68hc11 > capture capture /m68hc11/m68hc11tim"); } /* Create the SPI device. */ if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11spi/reg") == 0) { sim_hw_parse (sd, "/m68hc11/m68hc11spi/reg 0x28 0x3"); sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11spi"); } if (hw_tree_find_property (device_tree, "/m68hc11/nvram/reg") == 0) { /* M68hc11 persistent ram configuration. */ sim_hw_parse (sd, "/m68hc11/nvram/reg 0x0 256"); sim_hw_parse (sd, "/m68hc11/nvram/file m68hc11.ram"); sim_hw_parse (sd, "/m68hc11/nvram/mode save-modified"); /*sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/pram"); */ } if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11eepr/reg") == 0) { sim_hw_parse (sd, "/m68hc11/m68hc11eepr/reg 0xb000 512"); sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11eepr"); } sim_hw_parse (sd, "/m68hc11 > port-a cpu-write-port /m68hc11"); sim_hw_parse (sd, "/m68hc11 > port-b cpu-write-port /m68hc11"); sim_hw_parse (sd, "/m68hc11 > port-c cpu-write-port /m68hc11"); sim_hw_parse (sd, "/m68hc11 > port-d cpu-write-port /m68hc11"); cpu->hw_cpu = sim_hw_parse (sd, "/m68hc11"); } else { cpu->cpu_interpretor = cpu_interp_m6812; if (hw_tree_find_property (device_tree, "/m68hc12/reg") == 0) { /* Allocate core external memory. */ sim_do_commandf (sd, "memory region 0x%lx@%d,0x%lx", 0x8000, M6811_RAM_LEVEL, 0x8000); sim_do_commandf (sd, "memory region 0x000@%d,0x8000", M6811_RAM_LEVEL); if (cpu->bank_start < cpu->bank_end) { sim_do_commandf (sd, "memory region 0x%lx@%d,0x100000", cpu->bank_virtual, M6811_RAM_LEVEL); sim_hw_parse (sd, "/m68hc12/use_bank 1"); } sim_hw_parse (sd, "/m68hc12/reg 0x0 0x3FF"); } if (!hw_tree_find_property (device_tree, "/m68hc12/m68hc12sio@1/reg")) { sim_hw_parse (sd, "/m68hc12/m68hc12sio@1/reg 0xC0 0x8"); sim_hw_parse (sd, "/m68hc12/m68hc12sio@1/backend stdio"); sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12sio@1"); } if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12tim/reg") == 0) { /* M68hc11 Timer configuration. */ sim_hw_parse (sd, "/m68hc12/m68hc12tim/reg 0x1b 0x5"); sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12tim"); sim_hw_parse (sd, "/m68hc12 > capture capture /m68hc12/m68hc12tim"); } /* Create the SPI device. */ if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12spi/reg") == 0) { sim_hw_parse (sd, "/m68hc12/m68hc12spi/reg 0x28 0x3"); sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12spi"); } if (hw_tree_find_property (device_tree, "/m68hc12/nvram/reg") == 0) { /* M68hc11 persistent ram configuration. */ sim_hw_parse (sd, "/m68hc12/nvram/reg 0x2000 8192"); sim_hw_parse (sd, "/m68hc12/nvram/file m68hc12.ram"); sim_hw_parse (sd, "/m68hc12/nvram/mode save-modified"); } if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12eepr/reg") == 0) { sim_hw_parse (sd, "/m68hc12/m68hc12eepr/reg 0x0800 2048"); sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12eepr"); } sim_hw_parse (sd, "/m68hc12 > port-a cpu-write-port /m68hc12"); sim_hw_parse (sd, "/m68hc12 > port-b cpu-write-port /m68hc12"); sim_hw_parse (sd, "/m68hc12 > port-c cpu-write-port /m68hc12"); sim_hw_parse (sd, "/m68hc12 > port-d cpu-write-port /m68hc12"); cpu->hw_cpu = sim_hw_parse (sd, "/m68hc12"); } return 1; }
SIM_DESC sim_open (SIM_OPEN_KIND kind, host_callback *cb, struct bfd *abfd, char **argv) { int i; SIM_DESC sd = sim_state_alloc (kind, cb); mn10300_callback = cb; SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); /* The cpu data is kept in a separately allocated chunk of memory. */ if (sim_cpu_alloc_all (sd, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK) return 0; /* for compatibility */ simulator = sd; /* FIXME: should be better way of setting up interrupts. For moment, only support watchpoints causing a breakpoint (gdb halt). */ STATE_WATCHPOINTS (sd)->pc = &(PC); STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC); STATE_WATCHPOINTS (sd)->interrupt_handler = NULL; STATE_WATCHPOINTS (sd)->interrupt_names = NULL; if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) return 0; sim_add_option_table (sd, NULL, mn10300_options); /* Allocate core managed memory */ sim_do_command (sd, "memory region 0,0x100000"); sim_do_command (sd, "memory region 0x40000000,0x200000"); /* getopt will print the error message so we just have to exit if this fails. FIXME: Hmmm... in the case of gdb we need getopt to call print_filtered. */ if (sim_parse_args (sd, argv) != SIM_RC_OK) { /* Uninstall the modules to avoid memory leaks, file descriptor leaks, etc. */ sim_module_uninstall (sd); return 0; } if ( NULL != board && (strcmp(board, BOARD_AM32) == 0 ) ) { /* environment */ STATE_ENVIRONMENT (sd) = OPERATING_ENVIRONMENT; sim_do_command (sd, "memory region 0x44000000,0x40000"); sim_do_command (sd, "memory region 0x48000000,0x400000"); /* device support for mn1030002 */ /* interrupt controller */ sim_hw_parse (sd, "/mn103int@0x34000100/reg 0x34000100 0x7C 0x34000200 0x8 0x34000280 0x8"); /* DEBUG: NMI input's */ sim_hw_parse (sd, "/glue@0x30000000/reg 0x30000000 12"); sim_hw_parse (sd, "/glue@0x30000000 > int0 nmirq /mn103int"); sim_hw_parse (sd, "/glue@0x30000000 > int1 watchdog /mn103int"); sim_hw_parse (sd, "/glue@0x30000000 > int2 syserr /mn103int"); /* DEBUG: ACK input */ sim_hw_parse (sd, "/glue@0x30002000/reg 0x30002000 4"); sim_hw_parse (sd, "/glue@0x30002000 > int ack /mn103int"); /* DEBUG: LEVEL output */ sim_hw_parse (sd, "/glue@0x30004000/reg 0x30004000 8"); sim_hw_parse (sd, "/mn103int > nmi int0 /glue@0x30004000"); sim_hw_parse (sd, "/mn103int > level int1 /glue@0x30004000"); /* DEBUG: A bunch of interrupt inputs */ sim_hw_parse (sd, "/glue@0x30006000/reg 0x30006000 32"); sim_hw_parse (sd, "/glue@0x30006000 > int0 irq-0 /mn103int"); sim_hw_parse (sd, "/glue@0x30006000 > int1 irq-1 /mn103int"); sim_hw_parse (sd, "/glue@0x30006000 > int2 irq-2 /mn103int"); sim_hw_parse (sd, "/glue@0x30006000 > int3 irq-3 /mn103int"); sim_hw_parse (sd, "/glue@0x30006000 > int4 irq-4 /mn103int"); sim_hw_parse (sd, "/glue@0x30006000 > int5 irq-5 /mn103int"); sim_hw_parse (sd, "/glue@0x30006000 > int6 irq-6 /mn103int"); sim_hw_parse (sd, "/glue@0x30006000 > int7 irq-7 /mn103int"); /* processor interrupt device */ /* the device */ sim_hw_parse (sd, "/mn103cpu@0x20000000"); sim_hw_parse (sd, "/mn103cpu@0x20000000/reg 0x20000000 0x42"); /* DEBUG: ACK output wired upto a glue device */ sim_hw_parse (sd, "/glue@0x20002000"); sim_hw_parse (sd, "/glue@0x20002000/reg 0x20002000 4"); sim_hw_parse (sd, "/mn103cpu > ack int0 /glue@0x20002000"); /* DEBUG: RESET/NMI/LEVEL wired up to a glue device */ sim_hw_parse (sd, "/glue@0x20004000"); sim_hw_parse (sd, "/glue@0x20004000/reg 0x20004000 12"); sim_hw_parse (sd, "/glue@0x20004000 > int0 reset /mn103cpu"); sim_hw_parse (sd, "/glue@0x20004000 > int1 nmi /mn103cpu"); sim_hw_parse (sd, "/glue@0x20004000 > int2 level /mn103cpu"); /* REAL: The processor wired up to the real interrupt controller */ sim_hw_parse (sd, "/mn103cpu > ack ack /mn103int"); sim_hw_parse (sd, "/mn103int > level level /mn103cpu"); sim_hw_parse (sd, "/mn103int > nmi nmi /mn103cpu"); /* PAL */ /* the device */ sim_hw_parse (sd, "/pal@0x31000000"); sim_hw_parse (sd, "/pal@0x31000000/reg 0x31000000 64"); sim_hw_parse (sd, "/pal@0x31000000/poll? true"); /* DEBUG: PAL wired up to a glue device */ sim_hw_parse (sd, "/glue@0x31002000"); sim_hw_parse (sd, "/glue@0x31002000/reg 0x31002000 16"); sim_hw_parse (sd, "/pal@0x31000000 > countdown int0 /glue@0x31002000"); sim_hw_parse (sd, "/pal@0x31000000 > timer int1 /glue@0x31002000"); sim_hw_parse (sd, "/pal@0x31000000 > int int2 /glue@0x31002000"); sim_hw_parse (sd, "/glue@0x31002000 > int0 int3 /glue@0x31002000"); sim_hw_parse (sd, "/glue@0x31002000 > int1 int3 /glue@0x31002000"); sim_hw_parse (sd, "/glue@0x31002000 > int2 int3 /glue@0x31002000"); /* REAL: The PAL wired up to the real interrupt controller */ sim_hw_parse (sd, "/pal@0x31000000 > countdown irq-0 /mn103int"); sim_hw_parse (sd, "/pal@0x31000000 > timer irq-1 /mn103int"); sim_hw_parse (sd, "/pal@0x31000000 > int irq-2 /mn103int"); /* 8 and 16 bit timers */ sim_hw_parse (sd, "/mn103tim@0x34001000/reg 0x34001000 36 0x34001080 100 0x34004000 16"); /* Hook timer interrupts up to interrupt controller */ sim_hw_parse (sd, "/mn103tim > timer-0-underflow timer-0-underflow /mn103int"); sim_hw_parse (sd, "/mn103tim > timer-1-underflow timer-1-underflow /mn103int"); sim_hw_parse (sd, "/mn103tim > timer-2-underflow timer-2-underflow /mn103int"); sim_hw_parse (sd, "/mn103tim > timer-3-underflow timer-3-underflow /mn103int"); sim_hw_parse (sd, "/mn103tim > timer-4-underflow timer-4-underflow /mn103int"); sim_hw_parse (sd, "/mn103tim > timer-5-underflow timer-5-underflow /mn103int"); sim_hw_parse (sd, "/mn103tim > timer-6-underflow timer-6-underflow /mn103int"); sim_hw_parse (sd, "/mn103tim > timer-6-compare-a timer-6-compare-a /mn103int"); sim_hw_parse (sd, "/mn103tim > timer-6-compare-b timer-6-compare-b /mn103int"); /* Serial devices 0,1,2 */ sim_hw_parse (sd, "/mn103ser@0x34000800/reg 0x34000800 48"); sim_hw_parse (sd, "/mn103ser@0x34000800/poll? true"); /* Hook serial interrupts up to interrupt controller */ sim_hw_parse (sd, "/mn103ser > serial-0-receive serial-0-receive /mn103int"); sim_hw_parse (sd, "/mn103ser > serial-0-transmit serial-0-transmit /mn103int"); sim_hw_parse (sd, "/mn103ser > serial-1-receive serial-1-receive /mn103int"); sim_hw_parse (sd, "/mn103ser > serial-1-transmit serial-1-transmit /mn103int"); sim_hw_parse (sd, "/mn103ser > serial-2-receive serial-2-receive /mn103int"); sim_hw_parse (sd, "/mn103ser > serial-2-transmit serial-2-transmit /mn103int"); sim_hw_parse (sd, "/mn103iop@0x36008000/reg 0x36008000 8 0x36008020 8 0x36008040 0xc 0x36008060 8 0x36008080 8"); /* Memory control registers */ sim_do_command (sd, "memory region 0x32000020,0x30"); /* Cache control register */ sim_do_command (sd, "memory region 0x20000070,0x4"); /* Cache purge regions */ sim_do_command (sd, "memory region 0x28400000,0x800"); sim_do_command (sd, "memory region 0x28401000,0x800"); /* DMA registers */ sim_do_command (sd, "memory region 0x32000100,0xF"); sim_do_command (sd, "memory region 0x32000200,0xF"); sim_do_command (sd, "memory region 0x32000400,0xF"); sim_do_command (sd, "memory region 0x32000800,0xF"); } else { if (board != NULL) { sim_io_eprintf (sd, "Error: Board `%s' unknown.\n", board); return 0; } } /* check for/establish the a reference program image */ if (sim_analyze_program (sd, (STATE_PROG_ARGV (sd) != NULL ? *STATE_PROG_ARGV (sd) : NULL), abfd) != SIM_RC_OK) { sim_module_uninstall (sd); return 0; } /* establish any remaining configuration options */ if (sim_config (sd) != SIM_RC_OK) { sim_module_uninstall (sd); return 0; } if (sim_post_argv_init (sd) != SIM_RC_OK) { /* Uninstall the modules to avoid memory leaks, file descriptor leaks, etc. */ sim_module_uninstall (sd); return 0; } /* set machine specific configuration */ /* STATE_CPU (sd, 0)->psw_mask = (PSW_NP | PSW_EP | PSW_ID | PSW_SAT */ /* | PSW_CY | PSW_OV | PSW_S | PSW_Z); */ /* CPU specific initialization. */ for (i = 0; i < MAX_NR_PROCESSORS; ++i) { SIM_CPU *cpu = STATE_CPU (sd, i); CPU_PC_FETCH (cpu) = mn10300_pc_get; CPU_PC_STORE (cpu) = mn10300_pc_set; } return sd; }