void
mn10300_core_signal (SIM_DESC sd,
sim_cpu *cpu,
sim_cia cia,
unsigned map,
int nr_bytes,
address_word addr,
transfer_type transfer,
sim_core_signals sig)
{
const char *copy = (transfer == read_transfer ? "read" : "write");
address_word ip = CIA_ADDR (cia);
switch (sig)
{
case sim_core_unmapped_signal:
sim_io_eprintf (sd, "mn10300-core: %d byte %s to unmapped address 0x%lx at 0x%lx\n",
nr_bytes, copy,
(unsigned long) addr, (unsigned long) ip);
program_interrupt(sd, cpu, cia, SIM_SIGSEGV);
break;
case sim_core_unaligned_signal:
sim_io_eprintf (sd, "mn10300-core: %d byte %s to unaligned address 0x%lx at 0x%lx\n",
nr_bytes, copy,
(unsigned long) addr, (unsigned long) ip);
program_interrupt(sd, cpu, cia, SIM_SIGBUS);
break;
default:
sim_engine_abort (sd, cpu, cia,
"mn10300_core_signal - internal error - bad switch");
}
}
void
sim_do_command (SIM_DESC sd, char *cmd)
{
char *mm_cmd = "memory-map";
char *int_cmd = "interrupt";
sim_cpu *cpu;
cpu = STATE_CPU (sd, 0);
/* Commands available from GDB: */
if (sim_args_command (sd, cmd) != SIM_RC_OK)
{
if (strncmp (cmd, "info", sizeof ("info") - 1) == 0)
sim_get_info (sd, &cmd[4]);
else if (strncmp (cmd, mm_cmd, strlen (mm_cmd) == 0))
sim_io_eprintf (sd,
"`memory-map' command replaced by `sim memory'\n");
else if (strncmp (cmd, int_cmd, strlen (int_cmd)) == 0)
sim_io_eprintf (sd, "`interrupt' command replaced by `sim watch'\n");
else
sim_io_eprintf (sd, "Unknown command `%s'\n", cmd);
}
/* If the architecture changed, re-configure. */
if (STATE_ARCHITECTURE (sd) != cpu->cpu_configured_arch)
sim_hw_configure (sd);
}
void
sim_engine_vabort (SIM_DESC sd,
sim_cpu *cpu,
sim_cia cia,
const char *fmt,
va_list ap)
{
ASSERT (sd == NULL || STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
if (sd == NULL)
{
vfprintf (stderr, fmt, ap);
fprintf (stderr, "\nQuit\n");
abort ();
}
else if (STATE_ENGINE (sd)->jmpbuf == NULL)
{
sim_io_evprintf (sd, fmt, ap);
sim_io_eprintf (sd, "\n");
sim_io_error (sd, "Quit Simulator");
abort ();
}
else
{
sim_io_evprintf (sd, fmt, ap);
sim_io_eprintf (sd, "\n");
sim_engine_halt (sd, cpu, NULL, cia, sim_stopped, SIM_SIGABRT);
}
}
void
mn10300_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception)
{
ASSERT(cpu != NULL);
if(exception == 0 && State.exc_suspended > 0)
{
if(State.exc_suspended != SIGTRAP) /* warn not for breakpoints */
sim_io_eprintf(sd, "Warning, resuming but ignoring pending exception signal (%d)\n",
State.exc_suspended);
}
else if(exception != 0 && State.exc_suspended > 0)
{
if(exception != State.exc_suspended)
sim_io_eprintf(sd, "Warning, resuming with mismatched exception signal (%d vs %d)\n",
State.exc_suspended, exception);
memcpy(State.regs, State.exc_suspend_regs, sizeof(State.regs));
CPU_PC_SET (cpu, PC); /* copy PC back from new State.regs */
}
else if(exception != 0 && State.exc_suspended == 0)
{
sim_io_eprintf(sd, "Warning, ignoring spontanous exception signal (%d)\n", exception);
}
State.exc_suspended = 0;
}
static SIM_RC
sim_model_init (SIM_DESC sd)
{
SIM_CPU *cpu;
/* If both cpu model and state architecture are set, ensure they're
compatible. If only one is set, set the other. If neither are set,
use the default model. STATE_ARCHITECTURE is the bfd_arch_info data
for the selected "mach" (bfd terminology). */
/* Only check cpu 0. STATE_ARCHITECTURE is for that one only. */
/* ??? At present this only supports homogeneous multiprocessors. */
cpu = STATE_CPU (sd, 0);
if (! STATE_ARCHITECTURE (sd)
&& ! CPU_MACH (cpu))
{
/* Set the default model. */
const MODEL *model = sim_model_lookup (WITH_DEFAULT_MODEL);
sim_model_set (sd, NULL, model);
}
if (STATE_ARCHITECTURE (sd)
&& CPU_MACH (cpu))
{
if (strcmp (STATE_ARCHITECTURE (sd)->printable_name,
MACH_BFD_NAME (CPU_MACH (cpu))) != 0)
{
sim_io_eprintf (sd, "invalid model `%s' for `%s'\n",
MODEL_NAME (CPU_MODEL (cpu)),
STATE_ARCHITECTURE (sd)->printable_name);
return SIM_RC_FAIL;
}
}
else if (STATE_ARCHITECTURE (sd))
{
/* Use the default model for the selected machine.
The default model is the first one in the list. */
const MACH *mach = sim_mach_lookup_bfd_name (STATE_ARCHITECTURE (sd)->printable_name);
if (mach == NULL)
{
sim_io_eprintf (sd, "unsupported machine `%s'\n",
STATE_ARCHITECTURE (sd)->printable_name);
return SIM_RC_FAIL;
}
sim_model_set (sd, NULL, MACH_MODELS (mach));
}
else
{
STATE_ARCHITECTURE (sd) = bfd_scan_arch (MACH_BFD_NAME (CPU_MACH (cpu)));
}
return SIM_RC_OK;
}
/* Get the memory bank parameters by looking at the global symbols
defined by the linker. */
static int
sim_get_bank_parameters (SIM_DESC sd, bfd* abfd)
{
sim_cpu *cpu;
long symsize;
long symbol_count, i;
unsigned size;
asymbol** asymbols;
asymbol** current;
cpu = STATE_CPU (sd, 0);
symsize = bfd_get_symtab_upper_bound (abfd);
if (symsize < 0)
{
sim_io_eprintf (sd, "Cannot read symbols of program");
return 0;
}
asymbols = (asymbol **) xmalloc (symsize);
symbol_count = bfd_canonicalize_symtab (abfd, asymbols);
if (symbol_count < 0)
{
sim_io_eprintf (sd, "Cannot read symbols of program");
return 0;
}
size = 0;
for (i = 0, current = asymbols; i < symbol_count; i++, current++)
{
const char* name = bfd_asymbol_name (*current);
if (strcmp (name, BFD_M68HC11_BANK_START_NAME) == 0)
{
cpu->bank_start = bfd_asymbol_value (*current);
}
else if (strcmp (name, BFD_M68HC11_BANK_SIZE_NAME) == 0)
{
size = bfd_asymbol_value (*current);
}
else if (strcmp (name, BFD_M68HC11_BANK_VIRTUAL_NAME) == 0)
{
cpu->bank_virtual = bfd_asymbol_value (*current);
}
}
free (asymbols);
cpu->bank_end = cpu->bank_start + size;
cpu->bank_shift = 0;
for (; size > 1; size >>= 1)
cpu->bank_shift++;
return 0;
}
void
hw_trace (struct hw *me,
const char *fmt,
...)
{
if (hw_trace_p (me)) /* to be sure, to be sure */
{
va_list ap;
va_start (ap, fmt);
sim_io_eprintf (hw_system (me), "%s: ", hw_path (me));
sim_io_evprintf (hw_system (me), fmt, ap);
sim_io_eprintf (hw_system (me), "\n");
va_end (ap);
}
}
static void
bfin_mmr_invalid (struct hw *me, address_word addr,
unsigned nr_bytes, bool write, bool missing)
{
SIM_CPU *cpu = hw_system_cpu (me);
const char *rw = write ? "write" : "read";
const char *reason =
missing ? "no such register" :
(addr & 3) ? "must be 32-bit aligned" : "invalid length";
/* Only throw a fit if the cpu is doing the access. DMA/GDB simply
go unnoticed. Not exactly hardware behavior, but close enough. */
if (!cpu)
{
sim_io_eprintf (hw_system (me),
"%s: invalid MMR %s at %#x length %u: %s\n",
hw_path (me), rw, addr, nr_bytes, reason);
return;
}
HW_TRACE ((me, "invalid MMR %s at %#x length %u: %s",
rw, addr, nr_bytes, reason));
/* XXX: is this what hardware does ? What about priority of unaligned vs
wrong length vs missing register ? What about system-vs-core ? */
/* XXX: We should move this addr check to a model property so we get the
same behavior regardless of where we map the model. */
if (addr >= BFIN_CORE_MMR_BASE)
/* XXX: This should be setting up CPLB fault addrs ? */
mmu_process_fault (cpu, addr, write, false, false, true);
else
/* XXX: Newer parts set up an interrupt from EBIU and program
EBIU_ERRADDR with the address. */
cec_hwerr (cpu, HWERR_SYSTEM_MMR);
}
static SIM_RC
do_memopt_delete (SIM_DESC sd,
int level,
int space,
address_word addr)
{
sim_memopt **entry = &STATE_MEMOPT (sd);
sim_memopt *alias;
while ((*entry) != NULL
&& ((*entry)->level != level
|| (*entry)->space != space
|| (*entry)->addr != addr))
entry = &(*entry)->next;
if ((*entry) == NULL)
{
sim_io_eprintf (sd, "Memory at 0x%lx not found, not deleted\n",
(long) addr);
return SIM_RC_FAIL;
}
/* delete any buffer */
if ((*entry)->buffer != NULL)
zfree ((*entry)->buffer);
/* delete it and its aliases */
alias = *entry;
*entry = (*entry)->next;
while (alias != NULL)
{
sim_memopt *dead = alias;
alias = alias->alias;
sim_core_detach (sd, NULL, dead->level, dead->space, dead->addr);
zfree (dead);
}
return SIM_RC_OK;
}
void
sim_board_reset (SIM_DESC sd)
{
struct hw *hw_cpu;
sim_cpu *cpu;
const struct bfd_arch_info *arch;
const char *cpu_type;
cpu = STATE_CPU (sd, 0);
arch = STATE_ARCHITECTURE (sd);
/* hw_cpu = sim_hw_parse (sd, "/"); */
if (arch->arch == bfd_arch_m68hc11)
{
cpu->cpu_type = CPU_M6811;
cpu_type = "/m68hc11";
}
else
{
cpu->cpu_type = CPU_M6812;
cpu_type = "/m68hc12";
}
hw_cpu = sim_hw_parse (sd, cpu_type);
if (hw_cpu == 0)
{
sim_io_eprintf (sd, "%s cpu not found in device tree.", cpu_type);
return;
}
cpu_reset (cpu);
hw_port_event (hw_cpu, 3, 0);
cpu_restart (cpu);
}
static void
bfin_mmr_invalid (struct hw *me, SIM_CPU *cpu, address_word addr,
unsigned nr_bytes, bool write)
{
if (!cpu)
cpu = hw_system_cpu (me);
/* Only throw a fit if the cpu is doing the access. DMA/GDB simply
go unnoticed. Not exactly hardware behavior, but close enough. */
if (!cpu)
{
sim_io_eprintf (hw_system (me), "%s: invalid MMR access @ %#x\n",
hw_path (me), addr);
return;
}
HW_TRACE ((me, "invalid MMR %s to 0x%08lx length %u",
write ? "write" : "read", (unsigned long) addr, nr_bytes));
/* XXX: is this what hardware does ? */
if (addr >= BFIN_CORE_MMR_BASE)
/* XXX: This should be setting up CPLB fault addrs ? */
mmu_process_fault (cpu, addr, write, false, false, true);
else
/* XXX: Newer parts set up an interrupt from EBIU and program
EBIU_ERRADDR with the address. */
cec_hwerr (cpu, HWERR_SYSTEM_MMR);
}
void
sim_do_command (SIM_DESC sd, const char *cmd)
{
if (sim_args_command (sd, cmd) != SIM_RC_OK)
sim_io_eprintf (sd, "Unknown sim command: \"%s\". Try \"sim help\".\n",
cmd);
}
/* Give some information about the simulator. */
static void
sim_get_info (SIM_DESC sd, char *cmd)
{
sim_cpu *cpu;
cpu = STATE_CPU (sd, 0);
if (cmd != 0 && (cmd[0] == ' ' || cmd[0] == '-'))
{
int i;
struct hw *hw_dev;
struct sim_info_list *dev_list;
const struct bfd_arch_info *arch;
arch = STATE_ARCHITECTURE (sd);
cmd++;
if (arch->arch == bfd_arch_m68hc11)
dev_list = dev_list_68hc11;
else
dev_list = dev_list_68hc12;
for (i = 0; dev_list[i].name; i++)
if (strcmp (cmd, dev_list[i].name) == 0)
break;
if (dev_list[i].name == 0)
{
sim_io_eprintf (sd, "Device '%s' not found.\n", cmd);
sim_io_eprintf (sd, "Valid devices: cpu timer sio eeprom\n");
return;
}
hw_dev = sim_hw_parse (sd, dev_list[i].device);
if (hw_dev == 0)
{
sim_io_eprintf (sd, "Device '%s' not found\n", dev_list[i].device);
return;
}
hw_ioctl (hw_dev, 23, 0);
return;
}
cpu_info (sd, cpu);
interrupts_info (sd, &cpu->cpu_interrupts);
}
static int
sim_prepare_for_program (SIM_DESC sd, bfd* abfd)
{
sim_cpu *cpu;
int elf_flags = 0;
cpu = STATE_CPU (sd, 0);
if (abfd != NULL)
{
asection *s;
if (bfd_get_flavour (abfd) == bfd_target_elf_flavour)
elf_flags = elf_elfheader (abfd)->e_flags;
cpu->cpu_elf_start = bfd_get_start_address (abfd);
/* See if any section sets the reset address */
cpu->cpu_use_elf_start = 1;
for (s = abfd->sections; s && cpu->cpu_use_elf_start; s = s->next)
{
if (s->flags & SEC_LOAD)
{
bfd_size_type size;
size = bfd_get_section_size (s);
if (size > 0)
{
bfd_vma lma;
if (STATE_LOAD_AT_LMA_P (sd))
lma = bfd_section_lma (abfd, s);
else
lma = bfd_section_vma (abfd, s);
if (lma <= 0xFFFE && lma+size >= 0x10000)
cpu->cpu_use_elf_start = 0;
}
}
}
if (elf_flags & E_M68HC12_BANKS)
{
if (sim_get_bank_parameters (sd, abfd) != 0)
sim_io_eprintf (sd, "Memory bank parameters are not initialized\n");
}
}
if (!sim_hw_configure (sd))
return SIM_RC_FAIL;
/* reset all state information */
sim_board_reset (sd);
return SIM_RC_OK;
}
int
sim_signal_to_host (SIM_DESC sd, SIM_SIGNAL sig)
{
switch (sig)
{
case SIM_SIGINT :
return SIGINT;
case SIM_SIGABRT :
return SIGABRT;
case SIM_SIGILL :
#ifdef SIGILL
return SIGILL;
#else
return SIGSEGV;
#endif
case SIM_SIGTRAP :
return SIGTRAP;
case SIM_SIGBUS :
#ifdef SIGBUS
return SIGBUS;
#else
return SIGSEGV;
#endif
case SIM_SIGSEGV :
return SIGSEGV;
case SIM_SIGXCPU :
#ifdef SIGXCPU
return SIGXCPU;
#endif
break;
case SIM_SIGFPE:
#ifdef SIGFPE
return SIGFPE;
#endif
break;
case SIM_SIGNONE:
return 0;
break;
}
sim_io_eprintf (sd, "sim_signal_to_host: unknown signal: %d\n", sig);
#ifdef SIGHUP
return SIGHUP; /* FIXME: Suggestions? */
#else
return 1;
#endif
}
void
sim_info (SIM_DESC sd, int verbose)
{
const char *cpu_type;
const struct bfd_arch_info *arch;
/* Nothing to do if there is no verbose flag set. */
if (verbose == 0 && STATE_VERBOSE_P (sd) == 0)
return;
arch = STATE_ARCHITECTURE (sd);
if (arch->arch == bfd_arch_m68hc11)
cpu_type = "68HC11";
else
cpu_type = "68HC12";
sim_io_eprintf (sd, "Simulator info:\n");
sim_io_eprintf (sd, " CPU Motorola %s\n", cpu_type);
sim_get_info (sd, 0);
sim_module_info (sd, verbose || STATE_VERBOSE_P (sd));
}
static address_word
check_pow2 (address_word value, char *argname, char *optname, SIM_DESC sd)
{
if ((value & (value - 1)) != 0)
{
sim_io_eprintf (sd, "%s argument to %s must be a power of 2\n",
argname, optname);
return 0; /* will enable default value. */
}
return value;
}
void
mn10300_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word cia)
{
ASSERT(cpu != NULL);
if(State.exc_suspended > 0)
sim_io_eprintf(sd, "Warning, nested exception triggered (%d)\n", State.exc_suspended);
CPU_PC_SET (cpu, cia);
memcpy(State.exc_trigger_regs, State.regs, sizeof(State.exc_trigger_regs));
State.exc_suspended = 0;
}
/* This is called at the end of any FP insns that may have triggered
FP exceptions. If no exception is enabled, it returns immediately.
Otherwise, it raises an exception code 0x1d0. */
void
fpu_check_signal_exception (SIM_DESC sd, sim_cpu *cpu, sim_cia cia)
{
if ((FPCR & EC_MASK) == 0)
return;
sim_io_eprintf(sd, "FPU %s%s%s%s%s exception\n",
(FPCR & EC_V) ? "V" : "",
(FPCR & EC_Z) ? "Z" : "",
(FPCR & EC_O) ? "O" : "",
(FPCR & EC_U) ? "U" : "",
(FPCR & EC_I) ? "I" : "");
program_interrupt (sd, cpu, cia, SIM_SIGFPE);
}
void
mn10300_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception)
{
ASSERT(cpu != NULL);
if(State.exc_suspended > 0)
sim_io_eprintf(sd, "Warning, nested exception signal (%d then %d)\n",
State.exc_suspended, exception);
memcpy(State.exc_suspend_regs, State.regs, sizeof(State.exc_suspend_regs));
memcpy(State.regs, State.exc_trigger_regs, sizeof(State.regs));
CPU_PC_SET (cpu, PC); /* copy PC back from new State.regs */
State.exc_suspended = exception;
}
static int
connected_p (SIM_DESC sd)
{
int numfds,flags;
struct timeval tv;
fd_set readfds;
struct sockaddr sockaddr;
int addrlen;
if (sockser_listen_fd == -1)
return 0;
if (sockser_fd >= 0)
{
/* FIXME: has client gone away? */
return 1;
}
/* Not connected. Connect with a client if there is one. */
FD_ZERO (&readfds);
FD_SET (sockser_listen_fd, &readfds);
/* ??? One can certainly argue this should be done differently,
but for now this is sufficient. */
tv.tv_sec = 0;
tv.tv_usec = sockser_timeout;
numfds = select (sockser_listen_fd + 1, &readfds, 0, 0, &tv);
if (numfds <= 0)
return 0;
addrlen = sizeof (sockaddr);
sockser_fd = accept (sockser_listen_fd, &sockaddr, &addrlen);
if (sockser_fd < 0)
return 0;
/* Set non-blocking i/o. */
flags = fcntl (sockser_fd, F_GETFL);
flags |= O_NONBLOCK | O_NDELAY;
if (fcntl (sockser_fd, F_SETFL, flags) == -1)
{
sim_io_eprintf (sd, "unable to set nonblocking i/o");
close (sockser_fd);
sockser_fd = -1;
return 0;
}
return 1;
}
uint64_t
aarch64_get_heap_start (sim_cpu *cpu)
{
uint64_t heap = aarch64_get_sym_value ("end");
if (heap == 0)
heap = aarch64_get_sym_value ("_end");
if (heap == 0)
{
heap = STACK_TOP - 0x100000;
sim_io_eprintf (CPU_STATE (cpu),
"Unable to find 'end' symbol - using addr based "
"upon stack instead %" PRIx64 "\n",
heap);
}
return heap;
}
static SIM_RC
model_option_handler (SIM_DESC sd, sim_cpu *cpu, int opt,
char *arg, int is_command)
{
switch (opt)
{
case OPTION_MODEL :
{
const MODEL *model = sim_model_lookup (arg);
if (! model)
{
sim_io_eprintf (sd, "unknown model `%s'", arg);
return SIM_RC_FAIL;
}
sim_model_set (sd, cpu, model);
break;
}
}
return SIM_RC_OK;
}
enum gdb_signal
sim_signal_to_gdb_signal (SIM_DESC sd, SIM_SIGNAL sig)
{
switch (sig)
{
case SIM_SIGINT :
return GDB_SIGNAL_INT;
case SIM_SIGABRT :
return GDB_SIGNAL_ABRT;
case SIM_SIGILL :
return GDB_SIGNAL_ILL;
case SIM_SIGTRAP :
return GDB_SIGNAL_TRAP;
case SIM_SIGBUS :
return GDB_SIGNAL_BUS;
case SIM_SIGSEGV :
return GDB_SIGNAL_SEGV;
case SIM_SIGXCPU :
return GDB_SIGNAL_XCPU;
case SIM_SIGFPE:
return GDB_SIGNAL_FPE;
break;
case SIM_SIGNONE:
return GDB_SIGNAL_0;
break;
}
sim_io_eprintf (sd, "sim_signal_to_host: unknown signal: %d\n", sig);
return GDB_SIGNAL_HUP;
}
static SIM_RC
model_option_handler (SIM_DESC sd, sim_cpu *cpu, int opt,
char *arg, int is_command)
{
switch (opt)
{
case OPTION_MODEL :
{
const MODEL *model = sim_model_lookup (arg);
if (! model)
{
sim_io_eprintf (sd, "unknown model `%s'\n", arg);
return SIM_RC_FAIL;
}
sim_model_set (sd, cpu, model);
break;
}
case OPTION_MODEL_INFO :
{
const MACH **machp;
const MODEL *model;
for (machp = & sim_machs[0]; *machp != NULL; ++machp)
{
sim_io_printf (sd, "Models for architecture `%s':\n",
MACH_NAME (*machp));
for (model = MACH_MODELS (*machp); MODEL_NAME (model) != NULL;
++model)
sim_io_printf (sd, " %s", MODEL_NAME (model));
sim_io_printf (sd, "\n");
}
break;
}
}
return SIM_RC_OK;
}
static SIM_RC
scache_option_handler (SIM_DESC sd, sim_cpu *cpu, int opt,
char *arg, int is_command)
{
switch (opt)
{
case 'c' :
if (WITH_SCACHE)
{
if (arg != NULL)
{
unsigned int n = (unsigned int) strtoul (arg, NULL, 0);
if (n < MIN_SCACHE_SIZE)
{
sim_io_eprintf (sd, "invalid scache size `%u', must be at least %u",
n, MIN_SCACHE_SIZE);
return SIM_RC_FAIL;
}
/* Ensure it's a multiple of 2. */
if ((n & (n - 1)) != 0)
{
unsigned int i;
sim_io_eprintf (sd, "scache size `%u' not a multiple of 2\n", n);
/* Round up to nearest multiple of 2. */
for (i = 1; i && i < n; i <<= 1)
continue;
if (i)
{
n = i;
sim_io_eprintf (sd, "rounding scache size up to %u\n", n);
}
}
if (cpu == NULL)
STATE_SCACHE_SIZE (sd) = n;
else
CPU_SCACHE_SIZE (cpu) = n;
}
else
{
if (cpu == NULL)
STATE_SCACHE_SIZE (sd) = SCACHE_DEFAULT_CACHE_SIZE;
else
CPU_SCACHE_SIZE (cpu) = SCACHE_DEFAULT_CACHE_SIZE;
}
}
else
sim_io_eprintf (sd, "Simulator execution cache not enabled, `--scache-size' ignored\n");
break;
case OPTION_PROFILE_SCACHE :
if (WITH_SCACHE && WITH_PROFILE_SCACHE_P)
{
/* FIXME: handle cpu != NULL. */
return sim_profile_set_option (sd, "-scache", PROFILE_SCACHE_IDX,
arg);
}
else
sim_io_eprintf (sd, "Simulator cache profiling not compiled in, `--profile-scache' ignored\n");
break;
}
return SIM_RC_OK;
}
static SIM_RC
standard_option_handler (SIM_DESC sd, sim_cpu *cpu, int opt,
char *arg, int is_command)
{
int i,n;
switch ((STANDARD_OPTIONS) opt)
{
case OPTION_VERBOSE:
STATE_VERBOSE_P (sd) = 1;
break;
#ifdef SIM_HAVE_BIENDIAN
case OPTION_ENDIAN:
if (strcmp (arg, "big") == 0)
{
if (WITH_TARGET_BYTE_ORDER == LITTLE_ENDIAN)
{
sim_io_eprintf (sd, "Simulator compiled for little endian only.\n");
return SIM_RC_FAIL;
}
/* FIXME:wip: Need to set something in STATE_CONFIG. */
current_target_byte_order = BIG_ENDIAN;
}
else if (strcmp (arg, "little") == 0)
{
if (WITH_TARGET_BYTE_ORDER == BIG_ENDIAN)
{
sim_io_eprintf (sd, "Simulator compiled for big endian only.\n");
return SIM_RC_FAIL;
}
/* FIXME:wip: Need to set something in STATE_CONFIG. */
current_target_byte_order = LITTLE_ENDIAN;
}
else
{
sim_io_eprintf (sd, "Invalid endian specification `%s'\n", arg);
return SIM_RC_FAIL;
}
break;
#endif
case OPTION_ENVIRONMENT:
if (strcmp (arg, "user") == 0)
STATE_ENVIRONMENT (sd) = USER_ENVIRONMENT;
else if (strcmp (arg, "virtual") == 0)
STATE_ENVIRONMENT (sd) = VIRTUAL_ENVIRONMENT;
else if (strcmp (arg, "operating") == 0)
STATE_ENVIRONMENT (sd) = OPERATING_ENVIRONMENT;
else
{
sim_io_eprintf (sd, "Invalid environment specification `%s'\n", arg);
return SIM_RC_FAIL;
}
if (WITH_ENVIRONMENT != ALL_ENVIRONMENT
&& WITH_ENVIRONMENT != STATE_ENVIRONMENT (sd))
{
char *type;
switch (WITH_ENVIRONMENT)
{
case USER_ENVIRONMENT: type = "user"; break;
case VIRTUAL_ENVIRONMENT: type = "virtual"; break;
case OPERATING_ENVIRONMENT: type = "operating"; break;
}
sim_io_eprintf (sd, "Simulator compiled for the %s environment only.\n",
type);
return SIM_RC_FAIL;
}
break;
case OPTION_ALIGNMENT:
if (strcmp (arg, "strict") == 0)
{
if (WITH_ALIGNMENT == 0 || WITH_ALIGNMENT == STRICT_ALIGNMENT)
{
current_alignment = STRICT_ALIGNMENT;
break;
}
}
else if (strcmp (arg, "nonstrict") == 0)
{
if (WITH_ALIGNMENT == 0 || WITH_ALIGNMENT == NONSTRICT_ALIGNMENT)
{
current_alignment = NONSTRICT_ALIGNMENT;
break;
}
}
else if (strcmp (arg, "forced") == 0)
{
if (WITH_ALIGNMENT == 0 || WITH_ALIGNMENT == FORCED_ALIGNMENT)
{
current_alignment = FORCED_ALIGNMENT;
break;
}
}
else
{
sim_io_eprintf (sd, "Invalid alignment specification `%s'\n", arg);
return SIM_RC_FAIL;
}
switch (WITH_ALIGNMENT)
{
case STRICT_ALIGNMENT:
sim_io_eprintf (sd, "Simulator compiled for strict alignment only.\n");
break;
case NONSTRICT_ALIGNMENT:
sim_io_eprintf (sd, "Simulator compiled for nonstrict alignment only.\n");
break;
case FORCED_ALIGNMENT:
sim_io_eprintf (sd, "Simulator compiled for forced alignment only.\n");
break;
}
return SIM_RC_FAIL;
case OPTION_DEBUG:
if (! WITH_DEBUG)
sim_io_eprintf (sd, "Debugging not compiled in, `-D' ignored\n");
else
{
for (n = 0; n < MAX_NR_PROCESSORS; ++n)
for (i = 0; i < MAX_DEBUG_VALUES; ++i)
CPU_DEBUG_FLAGS (STATE_CPU (sd, n))[i] = 1;
}
break;
case OPTION_DEBUG_INSN :
if (! WITH_DEBUG)
sim_io_eprintf (sd, "Debugging not compiled in, `--debug-insn' ignored\n");
else
{
for (n = 0; n < MAX_NR_PROCESSORS; ++n)
CPU_DEBUG_FLAGS (STATE_CPU (sd, n))[DEBUG_INSN_IDX] = 1;
}
break;
case OPTION_DEBUG_FILE :
if (! WITH_DEBUG)
sim_io_eprintf (sd, "Debugging not compiled in, `--debug-file' ignored\n");
else
{
FILE *f = fopen (arg, "w");
if (f == NULL)
{
sim_io_eprintf (sd, "Unable to open debug output file `%s'\n", arg);
return SIM_RC_FAIL;
}
for (n = 0; n < MAX_NR_PROCESSORS; ++n)
CPU_DEBUG_FILE (STATE_CPU (sd, n)) = f;
}
break;
#ifdef SIM_H8300 /* FIXME: Can be moved to h8300 dir. */
case OPTION_H8300:
set_h8300h (1,0);
break;
case OPTION_H8300S:
set_h8300h (1,1);
break;
#endif
#ifdef SIM_HAVE_FLATMEM
case OPTION_MEM_SIZE:
{
unsigned long ul = strtol (arg, NULL, 0);
/* 16384: some minimal amount */
if (! isdigit (arg[0]) || ul < 16384)
{
sim_io_eprintf (sd, "Invalid memory size `%s'", arg);
return SIM_RC_FAIL;
}
STATE_MEM_SIZE (sd) = ul;
}
break;
#endif
case OPTION_DO_COMMAND:
sim_do_command (sd, arg);
break;
case OPTION_ARCHITECTURE:
{
const struct bfd_arch_info *ap = bfd_scan_arch (arg);
if (ap == NULL)
{
sim_io_eprintf (sd, "Architecture `%s' unknown\n", arg);
return SIM_RC_FAIL;
}
STATE_ARCHITECTURE (sd) = ap;
break;
}
case OPTION_ARCHITECTURE_INFO:
{
const char **list = bfd_arch_list();
const char **lp;
if (list == NULL)
abort ();
sim_io_printf (sd, "Possible architectures:");
for (lp = list; *lp != NULL; lp++)
sim_io_printf (sd, " %s", *lp);
sim_io_printf (sd, "\n");
free (list);
break;
}
case OPTION_TARGET:
{
STATE_TARGET (sd) = xstrdup (arg);
break;
}
case OPTION_LOAD_LMA:
{
STATE_LOAD_AT_LMA_P (sd) = 1;
break;
}
case OPTION_LOAD_VMA:
{
STATE_LOAD_AT_LMA_P (sd) = 0;
break;
}
case OPTION_HELP:
sim_print_help (sd, is_command);
if (STATE_OPEN_KIND (sd) == SIM_OPEN_STANDALONE)
exit (0);
/* FIXME: 'twould be nice to do something similar if gdb. */
break;
}
return SIM_RC_OK;
}
static SIM_RC
frv_option_handler (SIM_DESC sd, sim_cpu *current_cpu, int opt,
char *arg, int is_command)
{
switch (opt)
{
case 'p' :
if (! WITH_PROFILE)
sim_io_eprintf (sd, "Profiling not compiled in, `-p' ignored\n");
else
{
unsigned mask = PROFILE_USEFUL_MASK;
if (WITH_PROFILE_CACHE_P)
mask |= (1 << PROFILE_CACHE_IDX);
if (WITH_PROFILE_PARALLEL_P)
mask |= (1 << PROFILE_PARALLEL_IDX);
return set_profile_option_mask (sd, "profile", mask, arg);
}
break;
case OPTION_FRV_DATA_CACHE:
parse_cache_option (sd, arg, "data_cache", 1/*is_data_cache*/);
return SIM_RC_OK;
case OPTION_FRV_INSN_CACHE:
parse_cache_option (sd, arg, "insn_cache", 0/*is_data_cache*/);
return SIM_RC_OK;
case OPTION_FRV_PROFILE_CACHE:
if (WITH_PROFILE_CACHE_P)
return sim_profile_set_option (sd, "-cache", PROFILE_CACHE_IDX, arg);
else
sim_io_eprintf (sd, "Cache profiling not compiled in, `--profile-cache' ignored\n");
break;
case OPTION_FRV_PROFILE_PARALLEL:
if (WITH_PROFILE_PARALLEL_P)
{
unsigned mask
= (1 << PROFILE_MODEL_IDX) | (1 << PROFILE_PARALLEL_IDX);
return set_profile_option_mask (sd, "-parallel", mask, arg);
}
else
sim_io_eprintf (sd, "Parallel profiling not compiled in, `--profile-parallel' ignored\n");
break;
case OPTION_FRV_TIMER:
{
char *chp = arg;
address_word cycles, interrupt;
chp = parse_size (chp, &cycles);
if (chp == arg)
{
sim_io_eprintf (sd, "Cycle count required for --timer\n");
return SIM_RC_FAIL;
}
if (*chp != ',')
{
sim_io_eprintf (sd, "Interrupt number required for --timer\n");
return SIM_RC_FAIL;
}
chp = parse_size (chp + 1, &interrupt);
if (interrupt < 1 || interrupt > 15)
{
sim_io_eprintf (sd, "Interrupt number for --timer must be greater than 0 and less that 16\n");
return SIM_RC_FAIL;
}
frv_interrupt_state.timer.enabled = 1;
frv_interrupt_state.timer.value = cycles;
frv_interrupt_state.timer.current = 0;
frv_interrupt_state.timer.interrupt =
FRV_INTERRUPT_LEVEL_1 + interrupt - 1;
}
return SIM_RC_OK;
case OPTION_FRV_MEMORY_LATENCY:
{
int i;
char *chp = arg;
address_word cycles;
chp = parse_size (chp, &cycles);
if (chp == arg)
{
sim_io_eprintf (sd, "Cycle count required for --memory-latency\n");
return SIM_RC_FAIL;
}
for (i = 0; i < MAX_NR_PROCESSORS; ++i)
{
SIM_CPU *current_cpu = STATE_CPU (sd, i);
FRV_CACHE *insn_cache = CPU_INSN_CACHE (current_cpu);
FRV_CACHE *data_cache = CPU_DATA_CACHE (current_cpu);
insn_cache->memory_latency = cycles;
data_cache->memory_latency = cycles;
}
}
return SIM_RC_OK;
default:
sim_io_eprintf (sd, "Unknown FRV option %d\n", opt);
return SIM_RC_FAIL;
}
return SIM_RC_FAIL;
}
static SIM_RC
interrupt_option_handler (SIM_DESC sd, sim_cpu *cpu,
int opt, char *arg, int is_command)
{
char *p;
int mode;
int id;
struct interrupts *interrupts;
if (cpu == 0)
cpu = STATE_CPU (sd, 0);
interrupts = &cpu->cpu_interrupts;
switch (opt)
{
case OPTION_INTERRUPT_INFO:
for (id = 0; id < M6811_INT_NUMBER; id++)
{
sim_io_eprintf (sd, "%-10.10s ", interrupt_names[id]);
switch (interrupts->interrupts[id].stop_mode)
{
case SIM_STOP_WHEN_RAISED:
sim_io_eprintf (sd, "catch raised ");
break;
case SIM_STOP_WHEN_TAKEN:
sim_io_eprintf (sd, "catch taken ");
break;
case SIM_STOP_WHEN_RAISED | SIM_STOP_WHEN_TAKEN:
sim_io_eprintf (sd, "catch all ");
break;
default:
sim_io_eprintf (sd, " ");
break;
}
sim_io_eprintf (sd, "%ld\n",
interrupts->interrupts[id].raised_count);
}
break;
case OPTION_INTERRUPT_CATCH:
p = strchr (arg, ',');
if (p)
*p++ = 0;
mode = SIM_STOP_WHEN_RAISED;
id = find_interrupt (arg);
if (id < 0)
sim_io_eprintf (sd, "Interrupt name not recognized: %s\n", arg);
if (p && strcasecmp (p, "raised") == 0)
mode = SIM_STOP_WHEN_RAISED;
else if (p && strcasecmp (p, "taken") == 0)
mode = SIM_STOP_WHEN_TAKEN;
else if (p && strcasecmp (p, "all") == 0)
mode = SIM_STOP_WHEN_RAISED | SIM_STOP_WHEN_TAKEN;
else if (p)
{
sim_io_eprintf (sd, "Invalid argument: %s\n", p);
break;
}
if (id >= 0)
interrupts->interrupts[id].stop_mode = mode;
break;
case OPTION_INTERRUPT_CLEAR:
mode = SIM_STOP_WHEN_RAISED;
id = find_interrupt (arg);
if (id < 0)
sim_io_eprintf (sd, "Interrupt name not recognized: %s\n", arg);
else
interrupts->interrupts[id].stop_mode = 0;
break;
}
return SIM_RC_OK;
}
static SIM_RC
watchpoint_option_handler (SIM_DESC sd, sim_cpu *cpu, int opt,
char *arg, int is_command)
{
if (opt >= OPTION_WATCH_OP)
return do_watchpoint_create (sd, clock_watchpoint, opt, arg);
else
switch (opt)
{
case OPTION_WATCH_DELETE:
if (isdigit ((int) arg[0]))
{
int ident = strtol (arg, NULL, 0);
if (do_watchpoint_delete (sd, ident, invalid_watchpoint)
!= SIM_RC_OK)
{
sim_io_eprintf (sd, "Watchpoint %d not found\n", ident);
return SIM_RC_FAIL;
}
return SIM_RC_OK;
}
else if (strcasecmp (arg, "all") == 0)
{
watchpoint_type type;
for (type = invalid_watchpoint + 1;
type < nr_watchpoint_types;
type++)
{
do_watchpoint_delete (sd, 0, type);
}
return SIM_RC_OK;
}
else if (strcasecmp (arg, "pc") == 0)
{
if (do_watchpoint_delete (sd, 0, pc_watchpoint)
!= SIM_RC_OK)
{
sim_io_eprintf (sd, "No PC watchpoints found\n");
return SIM_RC_FAIL;
}
return SIM_RC_OK;
}
else if (strcasecmp (arg, "clock") == 0)
{
if (do_watchpoint_delete (sd, 0, clock_watchpoint) != SIM_RC_OK)
{
sim_io_eprintf (sd, "No CLOCK watchpoints found\n");
return SIM_RC_FAIL;
}
return SIM_RC_OK;
}
else if (strcasecmp (arg, "cycles") == 0)
{
if (do_watchpoint_delete (sd, 0, cycles_watchpoint) != SIM_RC_OK)
{
sim_io_eprintf (sd, "No CYCLES watchpoints found\n");
return SIM_RC_FAIL;
}
return SIM_RC_OK;
}
sim_io_eprintf (sd, "Unknown watchpoint type `%s'\n", arg);
return SIM_RC_FAIL;
case OPTION_WATCH_INFO:
{
do_watchpoint_info (sd);
return SIM_RC_OK;
}
default:
sim_io_eprintf (sd, "Unknown watch option %d\n", opt);
return SIM_RC_FAIL;
}
}
