void HELPER(gvec_fcmlad)(void *vd, void *vn, void *vm, void *vfpst, uint32_t desc) { uintptr_t opr_sz = simd_oprsz(desc); float64 *d = vd; float64 *n = vn; float64 *m = vm; float_status *fpst = vfpst; intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1); uint64_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1); uint64_t neg_real = flip ^ neg_imag; uintptr_t i; /* Shift boolean to the sign bit so we can xor to negate. */ neg_real <<= 63; neg_imag <<= 63; for (i = 0; i < opr_sz / 8; i += 2) { float64 e2 = n[i + flip]; float64 e1 = m[i + flip] ^ neg_real; float64 e4 = e2; float64 e3 = m[i + 1 - flip] ^ neg_imag; d[i] = float64_muladd(e2, e1, d[i], 0, fpst); d[i + 1] = float64_muladd(e4, e3, d[i + 1], 0, fpst); } clear_tail(d, opr_sz, simd_maxsz(desc)); }
void HELPER(gvec_fcmlas_idx)(void *vd, void *vn, void *vm, void *vfpst, uint32_t desc) { uintptr_t opr_sz = simd_oprsz(desc); float32 *d = vd; float32 *n = vn; float32 *m = vm; float_status *fpst = vfpst; intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1); uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1); uint32_t neg_real = flip ^ neg_imag; uintptr_t i; float32 e1 = m[H4(flip)]; float32 e3 = m[H4(1 - flip)]; /* Shift boolean to the sign bit so we can xor to negate. */ neg_real <<= 31; neg_imag <<= 31; e1 ^= neg_real; e3 ^= neg_imag; for (i = 0; i < opr_sz / 4; i += 2) { float32 e2 = n[H4(i + flip)]; float32 e4 = e2; d[H4(i)] = float32_muladd(e2, e1, d[H4(i)], 0, fpst); d[H4(i + 1)] = float32_muladd(e4, e3, d[H4(i + 1)], 0, fpst); } clear_tail(d, opr_sz, simd_maxsz(desc)); }
void HELPER(gvec_fcaddd)(void *vd, void *vn, void *vm, void *vfpst, uint32_t desc) { uintptr_t opr_sz = simd_oprsz(desc); float64 *d = vd; float64 *n = vn; float64 *m = vm; float_status *fpst = vfpst; uint64_t neg_real = extract64(desc, SIMD_DATA_SHIFT, 1); uint64_t neg_imag = neg_real ^ 1; uintptr_t i; /* Shift boolean to the sign bit so we can xor to negate. */ neg_real <<= 63; neg_imag <<= 63; for (i = 0; i < opr_sz / 8; i += 2) { float64 e0 = n[i]; float64 e1 = m[i + 1] ^ neg_imag; float64 e2 = n[i + 1]; float64 e3 = m[i] ^ neg_real; d[i] = float64_add(e0, e1, fpst); d[i + 1] = float64_add(e2, e3, fpst); } clear_tail(d, opr_sz, simd_maxsz(desc)); }
void HELPER(gvec_fcadds)(void *vd, void *vn, void *vm, void *vfpst, uint32_t desc) { uintptr_t opr_sz = simd_oprsz(desc); float32 *d = vd; float32 *n = vn; float32 *m = vm; float_status *fpst = vfpst; uint32_t neg_real = extract32(desc, SIMD_DATA_SHIFT, 1); uint32_t neg_imag = neg_real ^ 1; uintptr_t i; /* Shift boolean to the sign bit so we can xor to negate. */ neg_real <<= 31; neg_imag <<= 31; for (i = 0; i < opr_sz / 4; i += 2) { float32 e0 = n[H4(i)]; float32 e1 = m[H4(i + 1)] ^ neg_imag; float32 e2 = n[H4(i + 1)]; float32 e3 = m[H4(i)] ^ neg_real; d[H4(i)] = float32_add(e0, e1, fpst); d[H4(i + 1)] = float32_add(e2, e3, fpst); } clear_tail(d, opr_sz, simd_maxsz(desc)); }
static inline void clear_high(void *d, intptr_t oprsz, uint32_t desc) { intptr_t maxsz = simd_maxsz(desc); intptr_t i; if (unlikely(maxsz > oprsz)) { for (i = oprsz; i < maxsz; i += sizeof(uint64_t)) { *(uint64_t *)(d + i) = 0; } } }
void HELPER(gvec_qrdmlah_s16)(void *vd, void *vn, void *vm, void *ve, uint32_t desc) { uintptr_t opr_sz = simd_oprsz(desc); int16_t *d = vd; int16_t *n = vn; int16_t *m = vm; CPUARMState *env = ve; uintptr_t i; for (i = 0; i < opr_sz / 2; ++i) { d[i] = inl_qrdmlah_s16(env, n[i], m[i], d[i]); } clear_tail(d, opr_sz, simd_maxsz(desc)); }
void HELPER(gvec_qrdmlsh_s32)(void *vd, void *vn, void *vm, void *ve, uint32_t desc) { uintptr_t opr_sz = simd_oprsz(desc); int32_t *d = vd; int32_t *n = vn; int32_t *m = vm; CPUARMState *env = ve; uintptr_t i; for (i = 0; i < opr_sz / 4; ++i) { d[i] = helper_neon_qrdmlsh_s32(env, n[i], m[i], d[i]); } clear_tail(d, opr_sz, simd_maxsz(desc)); }