static void sirfsoc_set_sleep_mode(u32 mode)
{
u32 sleep_mode = sirfsoc_rtc_iobrg_readl(sirfsoc_pwrc_base +
SIRFSOC_PWRC_PDN_CTRL);
sleep_mode &= ~(SIRFSOC_SLEEP_MODE_MASK << 1);
sleep_mode |= mode << 1;
sirfsoc_rtc_iobrg_writel(sleep_mode, sirfsoc_pwrc_base +
SIRFSOC_PWRC_PDN_CTRL);
}
static void sirfsoc_set_wakeup_source(void)
{
u32 pwr_trigger_en_reg;
pwr_trigger_en_reg = sirfsoc_rtc_iobrg_readl(sirfsoc_pwrc_base +
SIRFSOC_PWRC_TRIGGER_EN);
#define X_ON_KEY_B (1 << 0)
sirfsoc_rtc_iobrg_writel(pwr_trigger_en_reg | X_ON_KEY_B,
sirfsoc_pwrc_base + SIRFSOC_PWRC_TRIGGER_EN);
}
static void sirfsoc_pwrc_toggle_interrupts(struct sirfsoc_pwrc_drvdata *pwrcdrv,
bool enable)
{
u32 int_mask;
int_mask = sirfsoc_rtc_iobrg_readl(pwrcdrv->pwrc_base + PWRC_INT_MASK);
if (enable)
int_mask |= PWRC_ON_KEY_BIT;
else
int_mask &= ~PWRC_ON_KEY_BIT;
sirfsoc_rtc_iobrg_writel(int_mask, pwrcdrv->pwrc_base + PWRC_INT_MASK);
}
static irqreturn_t sirfsoc_pwrc_isr(int irq, void *dev_id)
{
struct sirfsoc_pwrc_drvdata *pwrcdrv = dev_id;
u32 int_status;
int_status = sirfsoc_rtc_iobrg_readl(pwrcdrv->pwrc_base +
PWRC_INT_STATUS);
sirfsoc_rtc_iobrg_writel(int_status & ~PWRC_ON_KEY_BIT,
pwrcdrv->pwrc_base + PWRC_INT_STATUS);
input_event(pwrcdrv->input, EV_KEY, KEY_POWER, 1);
input_sync(pwrcdrv->input);
schedule_delayed_work(&pwrcdrv->work,
msecs_to_jiffies(PWRC_KEY_DETECT_UP_TIME));
return IRQ_HANDLED;
}
static int sirfsoc_pwrc_is_on_key_down(struct sirfsoc_pwrc_drvdata *pwrcdrv)
{
u32 state = sirfsoc_rtc_iobrg_readl(pwrcdrv->pwrc_base +
PWRC_PIN_STATUS);
return !(state & PWRC_ON_KEY_BIT); /* ON_KEY is active low */
}
static int regmap_iobg_regread(void *context, unsigned int reg,
unsigned int *val)
{
*val = (u32)sirfsoc_rtc_iobrg_readl(reg);
return 0;
}
