static int smbus_read_byte(unsigned device, unsigned address) { unsigned char global_status_register; unsigned char byte; /* print_err("smbus_read_byte\n"); */ if (smbus_wait_until_ready() < 0) { print_err("SMBUS not ready (-2)\n"); return -2; } /* setup transaction */ /* disable interrupts */ outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xfe, SMBUS_IO_BASE + SMBHSTCTL); /* set the device I'm talking too */ outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBXMITADD); /* set the command/address... */ outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD); /* set up for a byte data read */ outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2 << 2), SMBUS_IO_BASE + SMBHSTCTL); /* clear any lingering errors, so the transaction will run */ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); /* clear the data byte... */ outb(0, SMBUS_IO_BASE + SMBHSTDAT0); /* start a byte read, with interrupts disabled */ outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL); /* poll for it to start */ if (smbus_wait_until_active() < 0) { print_err("SMBUS not active (-4)\n"); return -4; } /* poll for transaction completion */ if (smbus_wait_until_done() < 0) { print_err("SMBUS not completed (-3)\n"); return -3; } global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT) & ~(1 << 6); /* Ignore the In Use Status... */ /* read results of transaction */ byte = inb(SMBUS_IO_BASE + SMBHSTDAT0); if (global_status_register != 2) { //print_spew("%s: no device (%02x, %02x)\n", __func__, device, address); return -1; } //print_debug("%s: %02x@%02x = %02x\n", __func__, device, address, byte); return byte; }
/* * Copied from intel/i82801dbm early smbus code - suggested by rgm. * Modifications/check against i2c-viapro driver code from linux-2.4.22 * and VT8231 Reference Docs - mw. */ static int smbus_read_byte(unsigned device, unsigned address) { unsigned char global_status_register; unsigned char byte; if (smbus_wait_until_ready() < 0) { outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); if (smbus_wait_until_ready() < 0) { return -2; } } /* setup transaction */ /* disable interrupts */ outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xfe, SMBUS_IO_BASE + SMBHSTCTL); /* set the device I'm talking too */ outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBXMITADD); /* set the command/address... */ outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD); /* set up for a byte data read */ outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2 << 2), SMBUS_IO_BASE + SMBHSTCTL); /* clear any lingering errors, so the transaction will run */ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); /* clear the data byte... */ outb(0, SMBUS_IO_BASE + SMBHSTDAT0); /* start a byte read, with interrupts disabled */ outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL); /* poll for it to start */ if (smbus_wait_until_active() < 0) { return -4; } /* poll for transaction completion */ if (smbus_wait_until_done() < 0) { return -3; } /* Ignore the Host Busy & Command Complete ? */ global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT) & ~((1 << 1) | (1 << 0)); /* read results of transaction */ byte = inb(SMBUS_IO_BASE + SMBHSTDAT0); if (global_status_register != 0) { return -1; } return byte; }