static void smi_ir_stop(struct smi_rc *ir)
{
struct smi_dev *dev = ir->dev;
smi_ir_disableInterrupt(ir);
smi_clear(IR_Init_Reg, 0x80);
}
static int smi_hw_init(struct smi_dev *dev)
{
u32 port_mux, port_ctrl, int_stat;
dprintk("%s\n", __func__);
/* set port mux.*/
port_mux = smi_read(MUX_MODE_CTRL);
port_mux &= ~(rbPaMSMask);
port_mux |= rbPaMSDtvNoGpio;
port_mux &= ~(rbPbMSMask);
port_mux |= rbPbMSDtvNoGpio;
port_mux &= ~(0x0f0000);
port_mux |= 0x50000;
smi_write(MUX_MODE_CTRL, port_mux);
/* set DTV register.*/
/* Port A */
port_ctrl = smi_read(VIDEO_CTRL_STATUS_A);
port_ctrl &= ~0x01;
smi_write(VIDEO_CTRL_STATUS_A, port_ctrl);
port_ctrl = smi_read(MPEG2_CTRL_A);
port_ctrl &= ~0x40;
port_ctrl |= 0x80;
smi_write(MPEG2_CTRL_A, port_ctrl);
/* Port B */
port_ctrl = smi_read(VIDEO_CTRL_STATUS_B);
port_ctrl &= ~0x01;
smi_write(VIDEO_CTRL_STATUS_B, port_ctrl);
port_ctrl = smi_read(MPEG2_CTRL_B);
port_ctrl &= ~0x40;
port_ctrl |= 0x80;
smi_write(MPEG2_CTRL_B, port_ctrl);
/* disable and clear interrupt.*/
smi_write(MSI_INT_ENA_CLR, ALL_INT);
int_stat = smi_read(MSI_INT_STATUS);
smi_write(MSI_INT_STATUS_CLR, int_stat);
/* reset demod.*/
smi_clear(PERIPHERAL_CTRL, 0x0303);
msleep(50);
smi_set(PERIPHERAL_CTRL, 0x0101);
return 0;
}
