コード例 #1
0
ファイル: post.c プロジェクト: jibaron/q35-seabios
// Main setup code.
static void
maininit(void)
{
    // Setup romfile items.
    qemu_cfg_romfile_setup();
    coreboot_cbfs_setup();

    // Setup ivt/bda/ebda
    init_ivt();
    init_bda();

    // Init base pc hardware.
    pic_setup();
    timer_setup();
    mathcp_setup();

    // Initialize pci
    pci_setup();
    smm_init();

    // Initialize mtrr
    mtrr_setup();

    // Setup Xen hypercalls
    xen_init_hypercalls();

    // Initialize internal tables
    boot_setup();

    // Start hardware initialization (if optionrom threading)
    if (CONFIG_THREADS && CONFIG_THREAD_OPTIONROMS)
        init_hw();

    // Find and initialize other cpus
    smp_probe();

    // Setup interfaces that option roms may need
    bios32_setup();
    pmm_setup();
    pnp_setup();
    kbd_setup();
    mouse_setup();
    init_bios_tables();

    // Run vga option rom
    vga_setup();

    // Do hardware initialization (if running synchronously)
    if (!CONFIG_THREADS || !CONFIG_THREAD_OPTIONROMS) {
        init_hw();
        wait_threads();
    }

    // Run option roms
    optionrom_setup();

    // Run BCVs and show optional boot menu
    boot_prep();

    // Finalize data structures before boot
    cdemu_setup();
    pmm_finalize();
    malloc_finalize();
    memmap_finalize();

    // Setup bios checksum.
    BiosChecksum -= checksum((u8*)BUILD_BIOS_ADDR, BUILD_BIOS_SIZE);

    // Write protect bios memory.
    make_bios_readonly();

    // Invoke int 19 to start boot process.
    startBoot();
}
コード例 #2
0
ファイル: lapic_cpu_init.c プロジェクト: lkundrak/coreboot
void initialize_cpus(struct bus *cpu_bus)
{
	struct device_path cpu_path;
	struct cpu_info *info;

	/* Find the info struct for this CPU */
	info = cpu_info();

	if (need_lapic_init()) {
		/* Ensure the local APIC is enabled */
		enable_lapic();

		/* Get the device path of the boot CPU */
		cpu_path.type           = DEVICE_PATH_APIC;
		cpu_path.apic.apic_id = lapicid();
	} else {
		/* Get the device path of the boot CPU */
		cpu_path.type = DEVICE_PATH_CPU;
		cpu_path.cpu.id       = 0;
	}

	/* Find the device structure for the boot CPU */
	info->cpu = alloc_find_dev(cpu_bus, &cpu_path);

	// why here? In case some day we can start core1 in amd_sibling_init
	if (is_smp_boot())
		copy_secondary_start_to_lowest_1M();

	if (!IS_ENABLED(CONFIG_SERIALIZED_SMM_INITIALIZATION))
		smm_init();

	/* start all aps at first, so we can init ECC all together */
	if (is_smp_boot() && IS_ENABLED(CONFIG_PARALLEL_CPU_INIT))
		start_other_cpus(cpu_bus, info->cpu);

	/* Initialize the bootstrap processor */
	cpu_initialize(0);

	if (is_smp_boot() && !IS_ENABLED(CONFIG_PARALLEL_CPU_INIT)) {
		start_other_cpus(cpu_bus, info->cpu);

		/* Now wait the rest of the cpus stop*/
		wait_other_cpus_stop(cpu_bus);
	}

	if (IS_ENABLED(CONFIG_SERIALIZED_SMM_INITIALIZATION)) {
		/* At this point, all APs are sleeping:
		 * smm_init() will queue a pending SMI on all cpus
		 * and smm_other_cpus() will start them one by one */
		smm_init();

		if (is_smp_boot()) {
			last_cpu_index = 0;
			smm_other_cpus(cpu_bus, info->cpu);
		}
	}

	smm_init_completion();

	if (is_smp_boot())
		recover_lowest_1M();
}