void SMPCache::access(MemRequest *mreq)
{
PAddr addr;
IS(addr = mreq->getPAddr());
GMSG(mreq->getPAddr() < 1024,
"mreq dinst=0x%p paddr=0x%x vaddr=0x%x memOp=%d ignored",
mreq->getDInst(),
(unsigned int) mreq->getPAddr(),
(unsigned int) mreq->getVaddr(),
mreq->getMemOperation());
I(addr > 1024);
switch(mreq->getMemOperation()){
case MemRead: read(mreq); break;
case MemWrite: /*I(cache->findLine(mreq->getPAddr())); will be transformed
to MemReadW later */
case MemReadW: write(mreq); break;
case MemPush: I(0); break; // assumed write-through upperlevel
default: specialOp(mreq); break;
}
// for reqs coming from upper level:
// MemRead means "I want to read"
// MemReadW means "I want to write, and I missed"
// MemWrite means "I want to write, and I hit"
// MemPush means "I am writing data back"
// (this will never happen if upper level is write-through cache,
// which is what we are assuming)
}
void SMPSystemBus::access(MemRequest *mreq)
{
GMSG(mreq->getPAddr() < 1024,
"mreq dinst=0x%p paddr=0x%x vaddr=0x%x memOp=%d",
mreq->getDInst(),
(unsigned int) mreq->getPAddr(),
(unsigned int) mreq->getVaddr(),
mreq->getMemOperation());
I(mreq->getPAddr() > 1024);
#ifdef SESC_ENERGY
busEnergy->inc();
#endif
switch(mreq->getMemOperation()){
case MemRead: read(mreq); break;
case MemReadW:
case MemWrite: write(mreq); break;
case MemPush: push(mreq); break;
default: specialOp(mreq); break;
}
// for reqs coming from upper level:
// MemRead means I need to read the data, but I don't have it
// MemReadW means I need to write the data, but I don't have it
// MemWrite means I need to write the data, but I don't have permission
// MemPush means I don't have space to keep the data, send it to memory
}
