/**
* \brief Test SPI transfer.
*
* This test tests SPI read/write.
*
* \param test Current test case.
*/
static void run_spi_trans_test(const struct test_case *test)
{
spi_status_t rc;
uint16_t spi_data;
uint8_t spi_pcs;
spi_reset(CONF_TEST_SPI);
spi_set_lastxfer(CONF_TEST_SPI);
spi_set_master_mode(CONF_TEST_SPI);
spi_disable_mode_fault_detect(CONF_TEST_SPI);
spi_set_peripheral_chip_select_value(CONF_TEST_SPI, CONF_TEST_SPI_NPCS);
spi_set_clock_polarity(CONF_TEST_SPI,
CONF_TEST_SPI_NPCS, SPI_CLK_POLARITY);
spi_set_clock_phase(CONF_TEST_SPI, CONF_TEST_SPI_NPCS, SPI_CLK_PHASE);
spi_set_bits_per_transfer(CONF_TEST_SPI,
CONF_TEST_SPI_NPCS, SPI_CSR_BITS_8_BIT);
spi_set_baudrate_div(CONF_TEST_SPI,
CONF_TEST_SPI_NPCS,
(sysclk_get_cpu_hz() / TEST_CLOCK));
spi_set_transfer_delay(CONF_TEST_SPI,
CONF_TEST_SPI_NPCS, SPI_DLYBS, SPI_DLYBCT);
spi_set_variable_peripheral_select(CONF_TEST_SPI);
spi_enable_loopback(CONF_TEST_SPI);
/* Test read/write timeout: should return SPI_ERROR_TIMEOUT. */
rc = spi_write(CONF_TEST_SPI, TEST_PATTERN, TEST_PCS, 1);
test_assert_true(test, rc == SPI_ERROR_TIMEOUT,
"Test SPI Write timeout: return code should not be %d", rc);
rc = spi_read(CONF_TEST_SPI, &spi_data, &spi_pcs);
test_assert_true(test, rc == SPI_ERROR_TIMEOUT,
"Test SPI Read timeout: return code should not be %d", rc);
spi_enable(CONF_TEST_SPI);
spi_enable_interrupt(CONF_TEST_SPI, SPI_IER_TDRE|SPI_IER_RDRF);
NVIC_EnableIRQ((IRQn_Type)CONF_TEST_SPI_ID);
/* Test write: should return OK. */
rc = spi_write(CONF_TEST_SPI, TEST_PATTERN, TEST_PCS, 1);
test_assert_true(test, rc == SPI_OK,
"Test SPI Write: return code should not be %d", rc);
/* Test read: should return OK with what is sent. */
rc = spi_read(CONF_TEST_SPI, &spi_data, &spi_pcs);
test_assert_true(test, rc == SPI_OK,
"Test SPI Read: return code should not be %d", rc);
test_assert_true(test, spi_data == TEST_PATTERN,
"Unexpected SPI data: %x, should be %x",
spi_data, TEST_PATTERN);
test_assert_true(test, spi_pcs == TEST_PCS,
"Unexpected SPI PCS: %x, should be %x",
spi_pcs, TEST_PCS);
/* Check interrupts. */
test_assert_true(test, g_b_spi_interrupt_tx_ready,
"Test SPI TX interrupt not detected");
test_assert_true(test, g_b_spi_interrupt_rx_ready,
"Test SPI RX interrupt not detected");
/* Done, disable SPI and all interrupts. */
spi_disable_loopback(CONF_TEST_SPI);
spi_disable(CONF_TEST_SPI);
spi_disable_interrupt(CONF_TEST_SPI, 0xFFFFFFFF);
NVIC_DisableIRQ((IRQn_Type)CONF_TEST_SPI_ID);
}
void spi_selector_init(void) {
// Initialize ///////////////////////////////////////////
const spi_settings_t setting = { .delay_between_cs = 12, };
// initialize selector 0
spi_selector_settings_t selector_0;
selector_0.selector = SPI_SELECTOR_0;
selector_0.CPOL = SPI_POLARITY_LOW;
selector_0.NCPHA = SPI_PHASE_LOW;
selector_0.baud_rate = 255;
selector_0.bits_pr_transfer = SPI_BITS_8;
selector_0.delay_clk = 492; // 41*12ns = 492 ns
selector_0.delay_transfers = 381;
// initialize selector 1
spi_selector_settings_t selector_1;
selector_1.selector = SPI_SELECTOR_1;
selector_1.CPOL = SPI_POLARITY_HIGH;
selector_1.NCPHA = SPI_PHASE_HIGH;
selector_1.baud_rate = 128;
selector_1.bits_pr_transfer = SPI_BITS_9;
selector_1.delay_clk = 1000; // 41*12ns = 492 ns
selector_1.delay_transfers = 1000;
spi_init(SPI0, &setting);
spi_init_selector(SPI0, &selector_0);
spi_init_selector(SPI0, &selector_1);
spi_enable(SPI0);
spi_enable_loopback(SPI0);
spi_select_slave(SPI0, SPI_SELECTOR_1); // Slave 0
/////////////////////////////
}
void test_spi_after_init(void) {
spi_selector_init();
// Testing initial values of status register
TEST_ASSERT_TRUE(spi_enable_status(SPI0));
TEST_ASSERT_TRUE((SPI0->SPI_SR & SPI_SR_RDRF_MASK) == 0);
TEST_ASSERT_TRUE((SPI0->SPI_SR & SPI_SR_TDRF_MASK) >> 1 == 1);
TEST_ASSERT_TRUE((SPI0->SPI_SR & SPI_SR_TXEMPTY_MASK) >> 9 == 1);
TEST_ASSERT_TRUE((SPI0->SPI_SR & SPI_SR_SPIENS_MASK) >> 16 == 1);
// Testing initial values of mode register
TEST_ASSERT_TRUE((SPI0->SPI_MR & SPI_MR_PCS_MASK) >> 16 == 0b0001);
TEST_ASSERT_TRUE((SPI0->SPI_MR & SPI_MR_LLB_MASK) >> 7 == 1);
TEST_ASSERT_TRUE((SPI0->SPI_MR & SPI_MR_DLYBCS_MASK) >> 24 > 0);
// Testing initial values of selector 0
TEST_ASSERT_TRUE((SPI0->SPI_CSR0 & SPI_CSRx_CPOL_MASK) == SPI_POLARITY_LOW);
TEST_ASSERT_TRUE(
(SPI0->SPI_CSR0 & SPI_CSRx_NCPHA_MASK) >> 1 == SPI_PHASE_LOW);
TEST_ASSERT_TRUE((SPI0->SPI_CSR0 & SPI_CSRx_SCBR_MASK) >> 8 == 255);
TEST_ASSERT_TRUE((SPI0->SPI_CSR0 & SPI_CSRx_BITS_MASK) >> 4 == SPI_BITS_8);
TEST_ASSERT_TRUE((SPI0->SPI_CSR0 & SPI_CSRx_DLYBS_MASK) >> 16 > 0);
TEST_ASSERT_TRUE((SPI0->SPI_CSR0 & SPI_CSRx_DLYBCT_MASK) >> 24 > 0);
// Testing initial values of selector 1
TEST_ASSERT_TRUE(
(SPI0->SPI_CSR1 & SPI_CSRx_CPOL_MASK) >> 0 == SPI_POLARITY_HIGH);
TEST_ASSERT_TRUE(
(SPI0->SPI_CSR1 & SPI_CSRx_NCPHA_MASK) >> 1 == SPI_PHASE_HIGH);
TEST_ASSERT_TRUE((SPI0->SPI_CSR1 & SPI_CSRx_SCBR_MASK) >> 8 == 128);
TEST_ASSERT_TRUE((SPI0->SPI_CSR1 & SPI_CSRx_BITS_MASK) >> 4 == SPI_BITS_9);
TEST_ASSERT_TRUE((SPI0->SPI_CSR1 & SPI_CSRx_DLYBS_MASK) >> 16 > 0);
TEST_ASSERT_TRUE((SPI0->SPI_CSR1 & SPI_CSRx_DLYBCT_MASK) >> 24 > 0);
}
