void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
int spi_n = get_available_spi();
if (spi_n == -1) {
error("No available SPI");
}
obj->spi_n = spi_n;
spi_used |= (1 << spi_n);
obj->spi = (spi_n) ? (LPC_SPI_TypeDef *)(LPC_SPI1_BASE) : (LPC_SPI_TypeDef *)(LPC_SPI0_BASE);
const SWM_Map *swm;
uint32_t regVal;
swm = &SWM_SPI_SCLK[obj->spi_n];
regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
LPC_SWM->PINASSIGN[swm->n] = regVal | (sclk << swm->offset);
swm = &SWM_SPI_MOSI[obj->spi_n];
regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
LPC_SWM->PINASSIGN[swm->n] = regVal | (mosi << swm->offset);
swm = &SWM_SPI_MISO[obj->spi_n];
regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
LPC_SWM->PINASSIGN[swm->n] = regVal | (miso << swm->offset);
swm = &SWM_SPI_SSEL[obj->spi_n];
regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
LPC_SWM->PINASSIGN[swm->n] = regVal | (ssel << swm->offset);
// clear interrupts
obj->spi->INTENCLR = 0x3f;
// enable power and clocking
switch (obj->spi_n) {
case 0:
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<11);
LPC_SYSCON->PRESETCTRL &= ~(0x1<<0);
LPC_SYSCON->PRESETCTRL |= (0x1<<0);
break;
case 1:
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<12);
LPC_SYSCON->PRESETCTRL &= ~(0x1<<1);
LPC_SYSCON->PRESETCTRL |= (0x1<<1);
break;
}
// set default format and frequency
if (ssel == NC) {
spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
} else {
spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
}
spi_frequency(obj, 1000000);
// enable the ssp channel
ssp_enable(obj);
}
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
// determine the SPI to use
SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
obj->spi = (SPI_TypeDef*)pinmap_merge(spi_data, spi_cntl);
MBED_ASSERT((int)obj->spi != NC)
// enable power and clocking
switch ((int)obj->spi) {
case SPI_1:
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN;
RCC->APB2ENR |= RCC_APB2ENR_SPI1EN;
break;
case SPI_2:
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN | RCC_AHB1ENR_GPIOCEN;
RCC->APB1ENR |= RCC_APB1ENR_SPI2EN;
break;
case SPI_3:
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN | RCC_AHB1ENR_GPIOCEN;
RCC->APB1ENR |= RCC_APB1ENR_SPI3EN;
break;
}
// set default format and frequency
if (ssel == NC) {
spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
} else {
spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
}
spi_frequency(obj, 1000000);
// enable the ssp channel
ssp_enable(obj);
// pin out the spi pins
pinmap_pinout(mosi, PinMap_SPI_MOSI);
pinmap_pinout(miso, PinMap_SPI_MISO);
pinmap_pinout(sclk, PinMap_SPI_SCLK);
if (ssel != NC) {
pinmap_pinout(ssel, PinMap_SPI_SSEL);
}
else {
// Use software slave management
obj->spi->CR1 |= SPI_CR1_SSM | SPI_CR1_SSI;
}
}
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk) {
// determine the SPI to use
uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI);
uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO);
uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK);
uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso);
obj->spi.instance = pinmap_merge(spi_data, spi_sclk);
MBED_ASSERT((int)obj->spi.instance != NC);
CLOCK_SYS_EnableSpiClock(obj->spi.instance);
uint32_t spi_address[] = SPI_BASE_ADDRS;
obj->spi.address = spi_address[obj->spi.instance];
DSPI_HAL_Init(obj->spi.address);
DSPI_HAL_Disable(obj->spi.address);
// set default format and frequency
spi_format(obj, 8, 0, SPI_MSB); // 8 bits, mode 0
DSPI_HAL_SetDelay(obj->spi.address, kDspiCtar0, 0, 0, kDspiPcsToSck);
spi_frequency(obj, 1000000);
DSPI_HAL_Enable(obj->spi.address);
DSPI_HAL_StartTransfer(obj->spi.address);
// pin out the spi pins
pinmap_pinout(mosi, PinMap_SPI_MOSI);
pinmap_pinout(miso, PinMap_SPI_MISO);
pinmap_pinout(sclk, PinMap_SPI_SCLK);
}
// Note: Private function with no locking
void SPI::_acquire() {
if (_owner != this) {
spi_format(&_spi, _bits, _mode, 0);
spi_frequency(&_spi, _hz);
_owner = this;
}
}
SPISlave::SPISlave(PinName mosi, PinName miso, PinName sclk, PinName ssel) {
spi_init(&_spi, mosi, miso, sclk, ssel);
_bits = 8;
_mode = 0;
_hz = 1000000;
spi_format(&_spi, _bits, _mode, 1);
spi_frequency(&_spi, _hz);
}
SPI::SPI(PinName mosi, PinName miso, PinName sclk, PinName _unused) {
spi_init(&_spi, mosi, miso, sclk, NC);
_bits = 8;
_mode = 0;
_hz = 1000000;
spi_format(&_spi, _bits, _mode, 0);
spi_frequency(&_spi, _hz);
}
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
// determine the SPI to use
SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
obj->spi = (LPC_SSP_TypeDef*)pinmap_merge(spi_data, spi_cntl);
MBED_ASSERT((int)obj->spi != NC);
// enable power and clocking
switch ((int)obj->spi) {
case SPI_0:
LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 11;
LPC_SYSCON->SSP0CLKDIV = 0x01;
LPC_SYSCON->PRESETCTRL |= 1 << 0;
break;
case SPI_1:
LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 18;
LPC_SYSCON->SSP1CLKDIV = 0x01;
LPC_SYSCON->PRESETCTRL |= 1 << 2;
break;
}
// set default format and frequency
if (ssel == NC) {
spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
} else {
spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
}
spi_frequency(obj, 1000000);
// enable the ssp channel
ssp_enable(obj);
// pin out the spi pins
pinmap_pinout(mosi, PinMap_SPI_MOSI);
pinmap_pinout(miso, PinMap_SPI_MISO);
pinmap_pinout(sclk, PinMap_SPI_SCLK);
if (ssel != NC) {
pinmap_pinout(ssel, PinMap_SPI_SSEL);
}
}
// ignore the fact there are multiple physical spis, and always update if it wasn't us last
void SPI::aquire() {
lock();
if (_owner != this) {
spi_format(&_spi, _bits, _mode, 0);
spi_frequency(&_spi, _hz);
_owner = this;
}
unlock();
}
SPISlave::SPISlave(PinName mosi, PinName miso, PinName sclk, PinName ssel) :
_spi(),
_bits(8),
_mode(0),
_hz(1000000)
{
spi_init(&_spi, mosi, miso, sclk, ssel);
spi_format(&_spi, _bits, _mode, 1);
spi_frequency(&_spi, _hz);
}
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
// determine the SPI to use
SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
obj->spi = (SPI_Type*)pinmap_merge(spi_data, spi_cntl);
if ((int)obj->spi == NC) {
error("SPI pinout mapping failed");
}
SIM->SCGC5 |= (1 << 11) | (1 << 12); // PortC & D
SIM->SCGC6 |= 1 << 12; // spi clocks
// halted state
obj->spi->MCR = SPI_MCR_HALT_MASK;
// set default format and frequency
if (ssel == NC) {
spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
} else {
spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
}
spi_frequency(obj, 1000000);
// not halt in the debug mode
obj->spi->SR |= SPI_SR_EOQF_MASK;
// enable SPI
obj->spi->MCR &= (~SPI_MCR_HALT_MASK);
// pin out the spi pins
pinmap_pinout(mosi, PinMap_SPI_MOSI);
pinmap_pinout(miso, PinMap_SPI_MISO);
pinmap_pinout(sclk, PinMap_SPI_SCLK);
if (ssel != NC) {
pinmap_pinout(ssel, PinMap_SPI_SSEL);
}
}
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
// determine the SPI to use
SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
obj->spi = (SPI_Type*)pinmap_merge(spi_data, spi_cntl);
if ((int)obj->spi == NC) {
error("SPI pinout mapping failed");
}
// enable power and clocking
switch ((int)obj->spi) {
case SPI_0: SIM->SCGC5 |= 1 << 11; SIM->SCGC4 |= 1 << 22; break;
case SPI_1: SIM->SCGC5 |= 1 << 13; SIM->SCGC4 |= 1 << 23; break;
}
// set default format and frequency
if (ssel == NC) {
spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
} else {
spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
}
spi_frequency(obj, 1000000);
// enable SPI
obj->spi->C1 |= SPI_C1_SPE_MASK;
// pin out the spi pins
pinmap_pinout(mosi, PinMap_SPI_MOSI);
pinmap_pinout(miso, PinMap_SPI_MISO);
pinmap_pinout(sclk, PinMap_SPI_SCLK);
if (ssel != NC) {
pinmap_pinout(ssel, PinMap_SPI_SSEL);
}
}
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
// determine the SPI to use
SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
obj->spi = (LPC_SSP_TypeDef*)pinmap_merge(spi_data, spi_cntl);
if ((int)obj->spi == NC) {
error("SPI pinout mapping failed");
}
// enable power and clocking
switch ((int)obj->spi) {
case SPI_0: LPC_SC->PCONP |= 1 << 21; break;
case SPI_1: LPC_SC->PCONP |= 1 << 10; break;
}
// set default format and frequency
if (ssel == NC) {
spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
} else {
spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
}
spi_frequency(obj, 1000000);
// enable the ssp channel
ssp_enable(obj);
// pin out the spi pins
pinmap_pinout(mosi, PinMap_SPI_MOSI);
pinmap_pinout(miso, PinMap_SPI_MISO);
pinmap_pinout(sclk, PinMap_SPI_SCLK);
if (ssel != NC) {
pinmap_pinout(ssel, PinMap_SPI_SSEL);
}
}
SPI::SPI(PinName mosi, PinName miso, PinName sclk) :
_spi(),
#if DEVICE_SPI_ASYNCH
_irq(this),
_usage(DMA_USAGE_NEVER),
#endif
_bits(8),
_mode(0),
_order(SPI_MSB),
_hz(1000000) {
spi_init(&_spi, mosi, miso, sclk);
spi_format(&_spi, _bits, _mode, _order);
spi_frequency(&_spi, _hz);
}
void SPI::format(int bits, int mode) {
lock();
_bits = bits;
_mode = mode;
// If changing format while you are the owner then just
// update format, but if owner is changed then even frequency should be
// updated which is done by acquire.
if (_owner == this) {
spi_format(&_spi, _bits, _mode, 0);
} else {
_acquire();
}
unlock();
}
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
// determine the SPI to use
SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
obj->spi = (SPI_Type*)pinmap_merge(spi_data, spi_cntl);
MBED_ASSERT((int)obj->spi != NC);
SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK | SIM_SCGC5_PORTD_MASK;
SIM->SCGC6 |= SIM_SCGC6_SPI0_MASK;
obj->spi->MCR &= ~(SPI_MCR_MDIS_MASK | SPI_MCR_HALT_MASK);
//obj->spi->MCR |= SPI_MCR_DIS_RXF_MASK | SPI_MCR_DIS_TXF_MASK;
// set default format and frequency
if (ssel == NC) {
spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
} else {
spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
}
spi_frequency(obj, 1000000);
// not halt in the debug mode
obj->spi->SR |= SPI_SR_EOQF_MASK;
// pin out the spi pins
pinmap_pinout(mosi, PinMap_SPI_MOSI);
pinmap_pinout(miso, PinMap_SPI_MISO);
pinmap_pinout(sclk, PinMap_SPI_SCLK);
if (ssel != NC) {
pinmap_pinout(ssel, PinMap_SPI_SSEL);
}
}
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
// determine the SPI to use
uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI);
uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO);
uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK);
uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL);
uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso);
uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel);
obj->instance = pinmap_merge(spi_data, spi_cntl);
MBED_ASSERT((int)obj->instance != NC);
// enable power and clocking
clock_manager_set_gate(kClockModuleSPI, obj->instance, true);
dspi_hal_disable(obj->instance);
// set default format and frequency
if (ssel == NC) {
spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
} else {
spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
}
spi_set_delays(obj->instance);
spi_frequency(obj, 1000000);
dspi_hal_enable(obj->instance);
dspi_hal_start_transfer(obj->instance);
// pin out the spi pins
pinmap_pinout(mosi, PinMap_SPI_MOSI);
pinmap_pinout(miso, PinMap_SPI_MISO);
pinmap_pinout(sclk, PinMap_SPI_SCLK);
if (ssel != NC) {
pinmap_pinout(ssel, PinMap_SPI_SSEL);
}
}
/**
* @brief Main program.
* @param None
* @retval None
*/
void main(void)
{
gpio_init(&gpio_reset, GPIO_RESET);
gpio_mode(&gpio_reset, PullUp);
gpio_dir(&gpio_reset, PIN_OUTPUT);
gpio_init(&gpio_cs, GPIO_CS);
gpio_mode(&gpio_cs, PullUp);
gpio_dir(&gpio_cs, PIN_OUTPUT);
spi_init(&spi0_master, SPI0_MOSI, SPI0_MISO, SPI0_SCLK, SPI0_CS);
spi_format(&spi0_master, 8, 3, 0);
spi_frequency(&spi0_master, 800000);
do
{
SPI_PL7223_Reset();
SPI_PL7223_Read(&Read_Data_PL7223[0],0x3860,1);//DSP version :20130322 ver02, 0x3860=0x04
//DSP version :20141009 ver01, 0x3860=0x03
}while( ((Read_Data_PL7223[0]) != 0x04) && ((Read_Data_PL7223[0]) != 0x03) );
SPI_PL7223_DELY(120000);
SPI_PL7223_RelayControl(0); // OFF
SPI_PL7223_DELY(120000);
do{
// As below is read DSP buffer process every time (144 byte)
SPI__PL7223_Read_Status();
SPI_PL7223_Read(&Read_Data_PL7223[0],0x3000,144); // 0x3000~0x308F //144 byte
SPI_PL7223_Read(&Read_Data_PL7223[144],0x3809,2); // Sample_cnt0
SPI_PL7223_Masurement();
SPI_PL7223_DELY(600000);
SPI_PL7223_RelayControl(1); // ON
SPI_PL7223_DELY(120000);
SPI__PL7223_Read_Status();
SPI_PL7223_Read(&Read_Data_PL7223[0],0x3000,144); // 0x3000~0x308F //144 byte
SPI_PL7223_Read(&Read_Data_PL7223[144],0x3809,2); // Sample_cnt0
SPI_PL7223_Masurement();
SPI_PL7223_DELY(600000);
SPI_PL7223_RelayControl(0); // OFF
SPI_PL7223_DELY(120000);
}while(1);
}
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
int altfunction[4];
// determine the SPI to use
SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
obj->spi = (MPS2_SSP_TypeDef*)pinmap_merge(spi_data, spi_cntl);
if ((int)obj->spi == NC) {
error("SPI pinout mapping failed");
}
// enable power and clocking
switch ((int)obj->spi) {
case (int)SPI_0:
obj->spi->CR1 = 0;
obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8;
obj->spi->CPSR = SSP_CPSR_DFLT;
obj->spi->IMSC = 0x8;
obj->spi->DMACR = 0;
obj->spi->CR1 = SSP_CR1_SSE_Msk;
obj->spi->ICR = 0x3;
break;
case (int)SPI_1:
/* Configure SSP used for LCD */
obj->spi->CR1 = 0; /* Synchronous serial port disable */
obj->spi->DMACR = 0; /* Disable FIFO DMA */
obj->spi->IMSC = 0; /* Mask all FIFO/IRQ interrupts */
obj->spi->ICR = ((1ul << 0) | /* Clear SSPRORINTR interrupt */
(1ul << 1) ); /* Clear SSPRTINTR interrupt */
obj->spi->CR0 = ((7ul << 0) | /* 8 bit data size */
(0ul << 4) | /* Motorola frame format */
(0ul << 6) | /* CPOL = 0 */
(0ul << 7) | /* CPHA = 0 */
(1ul << 8) ); /* Set serial clock rate */
obj->spi->CPSR = (2ul << 0); /* set SSP clk to 6MHz (6.6MHz max) */
obj->spi->CR1 = ((1ul << 1) | /* Synchronous serial port enable */
(0ul << 2) ); /* Device configured as master */
break;
case (int)SPI_2:
obj->spi->CR1 = 0;
obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8;
obj->spi->CPSR = SSP_CPSR_DFLT;
obj->spi->IMSC = 0x8;
obj->spi->DMACR = 0;
obj->spi->CR1 = SSP_CR1_SSE_Msk;
obj->spi->ICR = 0x3;
break;
case (int)SPI_3:
obj->spi->CR1 = 0;
obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8;
obj->spi->CPSR = SSP_CPSR_DFLT;
obj->spi->IMSC = 0x8;
obj->spi->DMACR = 0;
obj->spi->CR1 = SSP_CR1_SSE_Msk;
obj->spi->ICR = 0x3;
break;
case (int)SPI_4:
obj->spi->CR1 = 0;
obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8;
obj->spi->CPSR = SSP_CPSR_DFLT;
obj->spi->IMSC = 0x8;
obj->spi->DMACR = 0;
obj->spi->CR1 = SSP_CR1_SSE_Msk;
obj->spi->ICR = 0x3;
break;
}
if(mosi != NC){ altfunction[0] = 1;}else{ altfunction[0] = 0;}
if(miso != NC){ altfunction[1] = 1;}else{ altfunction[1] = 0;}
if(sclk != NC){ altfunction[2] = 1;}else{ altfunction[2] = 0;}
if(ssel != NC){ altfunction[3] = 1;}else{ altfunction[3] = 0;}
// enable alt function
switch ((int)obj->spi) {
case (int)SPI_2:
CMSDK_GPIO1->ALTFUNCSET |= (altfunction[2]<<5 | altfunction[0]<<4 | altfunction[1]<<3 | altfunction[3]<<2);
break;
case (int)SPI_3:
CMSDK_GPIO0->ALTFUNCSET |= (altfunction[2]<<13 | altfunction[1]<<12 | altfunction[0]<<11 | altfunction[3]<<10);
break;
case (int)SPI_4:
CMSDK_GPIO4->ALTFUNCSET |= (altfunction[2]<<3 | altfunction[1]<<2 | altfunction[0]<<1 | altfunction[3]);
break;
}
// set default format and frequency
if (ssel == NC) {
spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
} else {
spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
}
spi_frequency(obj, 1000000);
// enable the ssp channel
ssp_enable(obj);
// pin out the spi pins
pinmap_pinout(mosi, PinMap_SPI_MOSI);
pinmap_pinout(miso, PinMap_SPI_MISO);
pinmap_pinout(sclk, PinMap_SPI_SCLK);
if (ssel != NC) {
pinmap_pinout(ssel, PinMap_SPI_SSEL);
}
}
/**
* @brief Main program.
* @param None
* @retval None
*/
void main(void)
{
int Counter = 0;
int i;
#if SPI_IS_AS_MASTER
spi_init(&spi_master, SPI0_MOSI, SPI0_MISO, SPI0_SCLK, SPI0_CS);
spi_frequency(&spi_master, SCLK_FREQ);
spi_format(&spi_master, 16, (SPI_SCLK_IDLE_LOW|SPI_SCLK_TOGGLE_MIDDLE) , 0);
// wait Slave ready
wait_ms(1000);
while (Counter < TEST_LOOP) {
DBG_8195A("======= Test Loop %d =======\r\n", Counter);
for (i=0;i<TEST_BUF_SIZE;i++) {
TestBuf[i] = i;
}
spi_irq_hook(&spi_master, master_tr_done_callback, (uint32_t)&spi_master);
DBG_8195A("SPI Master Write Test==>\r\n");
TrDone = 0;
#if SPI_DMA_DEMO
spi_master_write_stream_dma(&spi_master, TestBuf, TEST_BUF_SIZE);
#else
spi_master_write_stream(&spi_master, TestBuf, TEST_BUF_SIZE);
#endif
i=0;
DBG_8195A("SPI Master Wait Write Done...\r\n");
while(TrDone == 0) {
wait_ms(10);
i++;
}
DBG_8195A("SPI Master Write Done!!\r\n");
DBG_8195A("SPI Master Read Test==>\r\n");
DBG_8195A("Wait 5 sec for SPI Slave get ready...\r\n");
for (i=0;i<5;i++) {
wait_ms(1000);
}
_memset(TestBuf, 0, TEST_BUF_SIZE);
spi_flush_rx_fifo(&spi_master);
TrDone = 0;
#if SPI_DMA_DEMO
spi_master_read_stream_dma(&spi_master, TestBuf, TEST_BUF_SIZE);
#else
spi_master_read_stream(&spi_master, TestBuf, TEST_BUF_SIZE);
#endif
i=0;
DBG_8195A("SPI Master Wait Read Done...\r\n");
while(TrDone == 0) {
wait_ms(10);
i++;
}
DBG_8195A("SPI Master Read Done!!\r\n");
__rtl_memDump_v1_00(TestBuf, TEST_BUF_SIZE, "SPI Master Read Data:");
Counter++;
}
spi_free(&spi_master);
DBG_8195A("SPI Master Test <==\r\n");
#else
spi_init(&spi_slave, SPI0_MOSI, SPI0_MISO, SPI0_SCLK, SPI0_CS);
spi_format(&spi_slave, 16, (SPI_SCLK_IDLE_LOW|SPI_SCLK_TOGGLE_MIDDLE) , 1);
while (spi_busy(&spi_slave)) {
DBG_8195A("Wait SPI Bus Ready...\r\n");
wait_ms(1000);
}
while (Counter < TEST_LOOP) {
DBG_8195A("======= Test Loop %d =======\r\n", Counter);
_memset(TestBuf, 0, TEST_BUF_SIZE);
DBG_8195A("SPI Slave Read Test ==>\r\n");
spi_irq_hook(&spi_slave, slave_tr_done_callback, (uint32_t)&spi_slave);
TrDone = 0;
spi_flush_rx_fifo(&spi_slave);
#if SPI_DMA_DEMO
spi_slave_read_stream_dma(&spi_slave, TestBuf, TEST_BUF_SIZE);
#else
spi_slave_read_stream(&spi_slave, TestBuf, TEST_BUF_SIZE);
#endif
i=0;
DBG_8195A("SPI Slave Wait Read Done...\r\n");
while(TrDone == 0) {
wait_ms(100);
i++;
if (i>150) {
DBG_8195A("SPI Slave Wait Timeout\r\n");
break;
}
}
__rtl_memDump_v1_00(TestBuf, TEST_BUF_SIZE, "SPI Slave Read Data:");
// Slave Write Test
DBG_8195A("SPI Slave Write Test ==>\r\n");
TrDone = 0;
#if SPI_DMA_DEMO
spi_slave_write_stream_dma(&spi_slave, TestBuf, TEST_BUF_SIZE);
#else
spi_slave_write_stream(&spi_slave, TestBuf, TEST_BUF_SIZE);
#endif
i=0;
DBG_8195A("SPI Slave Wait Write Done...\r\n");
while(TrDone == 0) {
wait_ms(100);
i++;
if (i> 200) {
DBG_8195A("SPI Slave Write Timeout...\r\n");
break;
}
}
DBG_8195A("SPI Slave Write Done!!\r\n");
Counter++;
}
spi_free(&spi_slave);
#endif
DBG_8195A("SPI Demo finished.\n");
for(;;);
}
void SPISlave::format(int bits, int mode)
{
_bits = bits;
_mode = mode;
spi_format(&_spi, _bits, _mode, 1);
}
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk)
{
SPIName spi = SPI_0; // Initialize to avoid compiler warnings
if (i2c0_spi0_peripheral.usage == I2C_SPI_PERIPHERAL_FOR_SPI &&
i2c0_spi0_peripheral.sda_mosi == (uint8_t)mosi &&
i2c0_spi0_peripheral.scl_miso == (uint8_t)miso &&
i2c0_spi0_peripheral.sclk == (uint8_t)sclk) {
// The SPI with the same pins is already initialized
spi = SPI_0;
obj->peripheral = 0x1;
} else if (i2c1_spi1_peripheral.usage == I2C_SPI_PERIPHERAL_FOR_SPI &&
i2c1_spi1_peripheral.sda_mosi == (uint8_t)mosi &&
i2c1_spi1_peripheral.scl_miso == (uint8_t)miso &&
i2c1_spi1_peripheral.sclk == (uint8_t)sclk) {
// The SPI with the same pins is already initialized
spi = SPI_1;
obj->peripheral = 0x2;
} else if (i2c1_spi1_peripheral.usage == 0) {
i2c1_spi1_peripheral.usage = I2C_SPI_PERIPHERAL_FOR_SPI;
i2c1_spi1_peripheral.sda_mosi = (uint8_t)mosi;
i2c1_spi1_peripheral.scl_miso = (uint8_t)miso;
i2c1_spi1_peripheral.sclk = (uint8_t)sclk;
spi = SPI_1;
obj->peripheral = 0x2;
} else if (i2c0_spi0_peripheral.usage == 0) {
i2c0_spi0_peripheral.usage = I2C_SPI_PERIPHERAL_FOR_SPI;
i2c0_spi0_peripheral.sda_mosi = (uint8_t)mosi;
i2c0_spi0_peripheral.scl_miso = (uint8_t)miso;
i2c0_spi0_peripheral.sclk = (uint8_t)sclk;
spi = SPI_0;
obj->peripheral = 0x1;
} else {
// No available peripheral
error("No available SPI");
}
obj->spi = (NRF_SPI_Type *)spi;
obj->spis = (NRF_SPIS_Type *)NC;
//master
obj->spi->POWER = 0;
obj->spi->POWER = 1;
//NRF_GPIO->DIR |= (1<<mosi);
NRF_GPIO->PIN_CNF[mosi] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
| (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
obj->spi->PSELMOSI = mosi;
NRF_GPIO->PIN_CNF[sclk] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
| (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
obj->spi->PSELSCK = sclk;
//NRF_GPIO->DIR &= ~(1<<miso);
NRF_GPIO->PIN_CNF[miso] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
| (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
obj->spi->PSELMISO = miso;
obj->spi->EVENTS_READY = 0U;
spi_format(obj, 8, 0, SPI_MSB); // 8 bits, mode 0, master
spi_frequency(obj, 1000000);
}
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
// determine the SPI to use
SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
#if defined(TARGET_LPC1768) || defined(TARGET_LPC2368)
obj->spi = (LPC_SSP_TypeDef*)pinmap_merge(spi_data, spi_cntl);
#elif defined(TARGET_LPC11U24)
obj->spi = (LPC_SSPx_Type*)pinmap_merge(spi_data, spi_cntl);
#else
#error CPU undefined.
#endif
if ((int)obj->spi == NC) {
error("SPI pinout mapping failed");
}
// enable power and clocking
#if defined(TARGET_LPC1768) || defined(TARGET_LPC2368)
switch ((int)obj->spi) {
case SPI_0: LPC_SC->PCONP |= 1 << 21; break;
case SPI_1: LPC_SC->PCONP |= 1 << 10; break;
}
#elif defined(TARGET_LPC11U24)
switch ((int)obj->spi) {
case SPI_0:
LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 11;
LPC_SYSCON->SSP0CLKDIV = 0x01;
LPC_SYSCON->PRESETCTRL |= 1 << 0;
break;
case SPI_1:
LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 18;
LPC_SYSCON->SSP1CLKDIV = 0x01;
LPC_SYSCON->PRESETCTRL |= 1 << 2;
break;
}
#else
#error CPU undefined.
#endif
// set default format and frequency
if (ssel == NC) {
spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
} else {
spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
}
spi_frequency(obj, 1000000);
// enable the ssp channel
obj->spi->CR1 |= 1 << 1;
// pin out the spi pins
pinmap_pinout(mosi, PinMap_SPI_MOSI);
pinmap_pinout(miso, PinMap_SPI_MISO);
pinmap_pinout(sclk, PinMap_SPI_SCLK);
if (ssel != NC) {
pinmap_pinout(ssel, PinMap_SPI_SSEL);
}
}
