/**
* \brief Start SPI transfer test.
*/
static void spi_master_go(void)
{
/* Configure SPI as master, set up SPI clock. */
spi_master_initialize();
/** Configure xdamc for spi0 and ready to transfer*/
spi_xdmac_configure(SPI0);
}
/*
* @brief Initializes the CC1101 for the A1101R09 to operate at 500kbps
*/
bool cc1101_initialize()
{
// Initialize SPI (Sample on rising, clk idle low)
spi_master_initialize();
// Reset CC1101
cc1101_command_strobe(SRES);
_delay_ms(10); // Wait for reset
// CC1101 Configuration Register Spree
cc1101_write_register(IOCFG0, IOCFG0_DEFAULT);
cc1101_write_register(IOCFG1, IOCFG1_DEFAULT);
cc1101_write_register(IOCFG2, IOCFG2_DEFAULT);
cc1101_write_register(FIFOTHR, FIFOTHR_DEFAULT);
cc1101_write_register(SYNC0, SYNC1_DEFAULT);
cc1101_write_register(SYNC1, SYNC2_DEFAULT);
cc1101_write_register(PKTLEN, PKTLEN_DEFAULT);
cc1101_write_register(PKTCTRL0, PKTCTRL0_DEFAULT);
cc1101_write_register(PKTCTRL1, PKTCTRL1_DEFAULT);
cc1101_write_register(ADDR, ADDR_DEFAULT);
cc1101_write_register(CHANNR, CHANNR_DEFAULT);
cc1101_write_register(FSCTRL0, FSCTRL0_DEFAULT);
cc1101_write_register(FSCTRL1, FSCTRL1_DEFAULT);
cc1101_write_register(FREQ0, FREQ0_DEFAULT);
cc1101_write_register(FREQ1, FREQ1_DEFAULT);
cc1101_write_register(FREQ2, FREQ2_DEFAULT);
cc1101_write_register(MDMCFG0, MDMCFG0_DEFAULT);
cc1101_write_register(MDMCFG1, MDMCFG1_DEFAULT);
cc1101_write_register(MDMCFG2, MDMCFG2_DEFAULT);
cc1101_write_register(MDMCFG3, MDMCFG3_DEFAULT);
cc1101_write_register(MDMCFG4, MDMCFG4_DEFAULT);
cc1101_write_register(DEVIATN, DEVIATN_DEFAULT);
cc1101_write_register(MCSM0, MCSM0_DEFAULT);
cc1101_write_register(MCSM1, MCSM1_DEFAULT);
cc1101_write_register(MCSM2, MCSM2_DEFAULT);
cc1101_write_register(FOCCFG, FOCCFG_DEFAULT); // Anaren 500k spec
cc1101_write_register(BSCFG, BSCFG_DEFAULT); // Anaren 500k spec
cc1101_write_register(AGCCTRL0, AGCCTRL0_DEFAULT); // Anaren 500k spec
cc1101_write_register(AGCCTRL1, AGCCTRL1_DEFAULT); // Anaren 500k spec
cc1101_write_register(AGCCTRL2, AGCCTRL2_DEFAULT); // Anaren 500k spec
cc1101_write_register(WOREVT0, WOREVT0_DEFAULT); // Anaren 500k spec
cc1101_write_register(WOREVT1, WOREVT1_DEFAULT); // Anaren 500k spec
cc1101_write_register(WORCTRL, WORCTRL_DEFAULT); // Anaren 500k spec
cc1101_write_register(FREND0, FREND0_DEFAULT); // Anaren 500k spec
cc1101_write_register(FREND1, FREND1_DEFAULT); // Anaren 500k spec
cc1101_write_register(FSCAL0, FSCAL0_DEFAULT); // Anaren 500k spec
cc1101_write_register(FSCAL1, FSCAL1_DEFAULT); // Anaren 500k spec
cc1101_write_register(FSCAL2, FSCAL2_DEFAULT); // Anaren 500k spec
cc1101_write_register(FSCAL3, FSCAL3_DEFAULT); // Anaren 500k spec
cc1101_write_register(RCCTRL0, RCCTRL0_DEFAULT); // Anaren 500k spec
cc1101_write_register(RCCTRL1, RCCTRL1_DEFAULT); // Anaren 500k spec
// Calibrate
cc1101_calibrate();
cc1101_command_strobe(SRX);
// CC1101 command strobe to turn on
return TRUE;
}
/*
* Initialise the SPI interface to MASTER or SLAVE based on the stacking jumper
*
*/
void stacking_init(bool master)
{
if (master){
spi_slave_initialize();
} else {
spi_master_initialize();
}
return;
}
/**
* \brief Initialize the ATSAM3X8E SPI driver in Master mode.
*
* \return Unused (ANSI-C compatibility).
*/
void spi_initialize(void)
{
//uint32_t* reg_ptr = 0x4000800C; // SPI_TDR (SPI0)
//*reg_ptr |= 0x00BB;
//spi_slave_initialize();
spi_master_initialize();
return;
}
/**
* \brief Set the specified SPI clock configuration.
*
* \param configuration Index of the configuration to set.
*/
static void spi_set_clock_configuration(uint8_t configuration)
{
spi_disable_xdmac();
NVIC_ClearPendingIRQ(SPI_IRQn);
NVIC_DisableIRQ(SPI_IRQn);
NVIC_SetPriority(SPI_IRQn, 0);
NVIC_EnableIRQ(SPI_IRQn);
gs_ul_spi_clock = gs_ul_clock_configurations[configuration];
printf("Setting SPI clock #%lu ... \n\r", (unsigned long)gs_ul_spi_clock);
spi_master_initialize();
spi_xdmac_configure(SPI0);
}
/**
* \brief Start SPI transfer test.
*/
static void spi_master_go(void)
{
uint32_t i;
/* Configure SPI as master, set up SPI clock. */
spi_master_initialize();
spi_master_transfer(gs_uc_spi_m_tbuffer, COMM_BUFFER_SIZE,
gs_uc_spi_m_rbuffer, COMM_BUFFER_SIZE);
for (i = 0; i < COMM_BUFFER_SIZE; i++) {
if(gs_uc_spi_m_rbuffer[i] !=gs_uc_spi_m_tbuffer[i]) {
break;
}
}
if(i == COMM_BUFFER_SIZE) {
puts("SPI transfer test success! \r");
} else {
puts("SPI transfer test fail! \r");
}
}
/**
* \brief Start SPI transfer test.
*/
static void spi_master_go(void)
{
uint32_t cmd;
uint32_t block;
uint32_t i;
/* Configure SPI as master, set up SPI clock. */
spi_master_initialize();
/*
* Send CMD_TEST to indicate the start of test, and device shall return
* RC_RDY.
*/
while (1) {
cmd = CMD_TEST;
puts("-> Master sending CMD_TEST... \r");
spi_master_transfer(&cmd, sizeof(cmd));
if (cmd == RC_RDY) {
puts(" <- Slave response RC_SYN, RC_RDY \r");
break;
}
if (cmd != RC_SYN) {
printf("-E- Response unexpected: 0x%x \n\r", (unsigned)cmd);
return;
}
}
/* Send CMD_DATA with 4 blocks (64 bytes per page). */
puts("-> Master sending CMD_DATA... \r");
cmd = CMD_DATA | MAX_DATA_BLOCK_NUMBER;
spi_master_transfer(&cmd, sizeof(cmd));
puts(" <---- Slave response RC_RDY \r");
for (block = 0; block < MAX_DATA_BLOCK_NUMBER; block++) {
for (i = 0; i < COMM_BUFFER_SIZE; i++) {
gs_uc_spi_buffer[i] = block;
}
printf("-> Master sending block %u ... \n\r", (unsigned)block);
spi_master_transfer(gs_uc_spi_buffer, COMM_BUFFER_SIZE);
if (block) {
for (i = 0; i < COMM_BUFFER_SIZE; i++) {
if (gs_uc_spi_buffer[i] != (block - 1)) {
break;
}
}
if (i < COMM_BUFFER_SIZE) {
printf("-E- block %u contains unexpected data \n\r",
(unsigned)block);
} else {
printf(" <- Slave response last block %x \n\r",
(unsigned)(block - 1));
}
}
}
for (i = 0; i < MAX_RETRY; i++) {
cmd = CMD_STATUS;
puts("-> Master sending CMD_STATUS... \r");
spi_master_transfer(&cmd, sizeof(cmd));
if (cmd == RC_RDY) {
puts(" <- Slave response RC_RDY \r");
break;
}
}
if (i >= MAX_RETRY) {
puts(" <- Slave no response \r");
return;
}
puts("-> Master request slave status... \r");
spi_master_transfer(&gs_spi_status, sizeof(struct status_block_t));
puts(" <- Slave reports status...\r");
printf("-I- Received %u commands:",
(unsigned)gs_spi_status.ul_total_command_number);
for (i = 0; i < gs_spi_status.ul_total_command_number; i++) {
printf(" 0x%08x", (unsigned)gs_spi_status.ul_cmd_list[i]);
}
printf(" \n\r-I- Received %lu data blocks \n\r",
(unsigned long)gs_spi_status.ul_total_block_number);
for (i = 0; i < MAX_RETRY; i++) {
puts("-> Master sending CMD_END... \r");
cmd = CMD_END;
spi_master_transfer(&cmd, sizeof(cmd));
if (cmd == RC_SYN) {
puts(" <- Slave response RC_SYN \r");
break;
}
}
if (i >= MAX_RETRY) {
puts(" <- Slave no response \r");
}
puts("\r");
puts("SPI transfer test finished! \r");
}
/**
* \brief Set the specified SPI clock configuration.
*
* \param configuration Index of the configuration to set.
*/
static void spi_set_clock_configuration(uint8_t configuration)
{
gs_ul_spi_clock = gs_ul_clock_configurations[configuration];
printf("Setting SPI clock #%lu ... \n\r", (unsigned long)gs_ul_spi_clock);
spi_master_initialize();
}
/**
* \brief Set the specified SPI clock configuration.
*
* \param configuration Index of the configuration to set.
*/
static void spi_set_clock_configuration(uint8_t configuration)
{
gs_ul_spi_clock = gs_ul_clock_configurations[configuration];
spi_master_initialize();
}
int main (void) {
global_watt_hours_epoch = epoch;
global_voltage_string = malloc(32);
global_current_string = malloc(32);
global_frequency_string = malloc(32);
global_active_power_string = malloc(32);
global_apparent_power_string = malloc(32);
global_reactive_power_string = malloc(32);
global_power_factor_string = malloc(32);
global_phase_angle_string = malloc(32);
sysclk_init();
board_init();
pmc_enable_periph_clk(PIN_ADE7753_ZX_ID);
pio_handler_set(PIN_ADE7753_ZX_PIO, PIN_ADE7753_ZX_ID, PIN_ADE7753_ZX_MASK, PIN_ADE7753_ZX_ATTR, ZX_Handler);
NVIC_EnableIRQ((IRQn_Type)PIN_ADE7753_ZX_ID);
pio_handler_set_priority(PIN_ADE7753_ZX_PIO, (IRQn_Type)PIN_ADE7753_ZX_ID, IRQ_PRIOR_PIO);
pio_enable_interrupt(PIN_ADE7753_ZX_PIO, PIN_ADE7753_ZX_MASK);
pmc_enable_periph_clk(PIN_ADE7753_IRQ_ID);
pio_handler_set(PIN_ADE7753_IRQ_PIO, PIN_ADE7753_IRQ_ID, PIN_ADE7753_IRQ_MASK, PIN_ADE7753_IRQ_ATTR, IRQ_Handler);
NVIC_EnableIRQ((IRQn_Type)PIN_ADE7753_IRQ_ID);
pio_handler_set_priority(PIN_ADE7753_IRQ_PIO, (IRQn_Type)PIN_ADE7753_IRQ_ID, IRQ_PRIOR_PIO);
pio_enable_interrupt(PIN_ADE7753_IRQ_PIO, PIN_ADE7753_IRQ_MASK);
pmc_enable_periph_clk(PIN_FP_BUTTON_LOAD_ID);
pio_handler_set(PIN_FP_BUTTON_LOAD_PIO, PIN_FP_BUTTON_LOAD_ID, PIN_FP_BUTTON_LOAD_MASK, PIN_FP_BUTTON_LOAD_ATTR, FP_LOAD_Handler);
NVIC_EnableIRQ((IRQn_Type)PIN_FP_BUTTON_LOAD_ID);
pio_handler_set_priority(PIN_FP_BUTTON_LOAD_PIO, (IRQn_Type)PIN_FP_BUTTON_LOAD_ID, IRQ_PRIOR_PIO);
pio_enable_interrupt(PIN_FP_BUTTON_LOAD_PIO, PIN_FP_BUTTON_LOAD_MASK);
pmc_enable_periph_clk(PIN_FP_BUTTON_UP_ID);
pio_handler_set(PIN_FP_BUTTON_UP_PIO, PIN_FP_BUTTON_UP_ID, PIN_FP_BUTTON_UP_MASK, PIN_FP_BUTTON_UP_ATTR, FP_UP_Handler);
NVIC_EnableIRQ((IRQn_Type)PIN_FP_BUTTON_UP_ID);
pio_handler_set_priority(PIN_FP_BUTTON_UP_PIO, (IRQn_Type)PIN_FP_BUTTON_UP_ID, IRQ_PRIOR_PIO);
pio_enable_interrupt(PIN_FP_BUTTON_UP_PIO, PIN_FP_BUTTON_UP_MASK);
pmc_enable_periph_clk(PIN_FP_BUTTON_DOWN_ID);
pio_handler_set(PIN_FP_BUTTON_DOWN_PIO, PIN_FP_BUTTON_DOWN_ID, PIN_FP_BUTTON_DOWN_MASK, PIN_FP_BUTTON_DOWN_ATTR, FP_DOWN_Handler);
NVIC_EnableIRQ((IRQn_Type)PIN_FP_BUTTON_DOWN_ID);
pio_handler_set_priority(PIN_FP_BUTTON_DOWN_PIO, (IRQn_Type)PIN_FP_BUTTON_DOWN_ID, IRQ_PRIOR_PIO);
pio_enable_interrupt(PIN_FP_BUTTON_DOWN_PIO, PIN_FP_BUTTON_DOWN_MASK);
pmc_enable_periph_clk(PIN_FP_BUTTON_BACK_ID);
pio_handler_set(PIN_FP_BUTTON_BACK_PIO, PIN_FP_BUTTON_BACK_ID, PIN_FP_BUTTON_BACK_MASK, PIN_FP_BUTTON_BACK_ATTR, FP_BACK_Handler);
NVIC_EnableIRQ((IRQn_Type)PIN_FP_BUTTON_BACK_ID);
pio_handler_set_priority(PIN_FP_BUTTON_BACK_PIO, (IRQn_Type)PIN_FP_BUTTON_BACK_ID, IRQ_PRIOR_PIO);
pio_enable_interrupt(PIN_FP_BUTTON_BACK_PIO, PIN_FP_BUTTON_BACK_MASK);
/*
pmc_enable_periph_clk(PIN_FP_ENCODER_Q1_ID);
pio_handler_set(PIN_FP_ENCODER_Q1_PIO, PIN_FP_ENCODER_Q1_ID, PIN_FP_ENCODER_Q1_MASK, PIN_FP_ENCODER_Q1_ATTR, FP_ENCODER_Handler);
NVIC_EnableIRQ((IRQn_Type)PIN_FP_ENCODER_Q1_ID);
pio_handler_set_priority(PIN_FP_ENCODER_Q1_PIO, (IRQn_Type)PIN_FP_ENCODER_Q1_ID, IRQ_PRIOR_PIO);
pio_enable_interrupt(PIN_FP_ENCODER_Q1_PIO, PIN_FP_ENCODER_Q1_MASK);
pmc_enable_periph_clk(PIN_FP_ENCODER_Q2_ID);
pio_handler_set(PIN_FP_ENCODER_Q2_PIO, PIN_FP_ENCODER_Q2_ID, PIN_FP_ENCODER_Q2_MASK, PIN_FP_ENCODER_Q2_ATTR, FP_ENCODER_Handler);
NVIC_EnableIRQ((IRQn_Type)PIN_FP_ENCODER_Q2_ID);
pio_handler_set_priority(PIN_FP_ENCODER_Q2_PIO, (IRQn_Type)PIN_FP_ENCODER_Q2_ID, IRQ_PRIOR_PIO);
pio_enable_interrupt(PIN_FP_ENCODER_Q2_PIO, PIN_FP_ENCODER_Q2_MASK);
*/
ioport_set_pin_level(LED1_GPIO, false);
ioport_set_pin_level(LED2_GPIO, false);
ioport_set_pin_level(LED3_GPIO, false);
ioport_set_pin_level(FP_LED0_GPIO, false);
ioport_set_pin_level(FP_LED1_GPIO, false);
ioport_set_pin_level(FP_LED2_GPIO, false);
ioport_set_pin_level(FP_LED3_GPIO, true);
ioport_set_pin_level(RELAY_1_GPIO, false);
ioport_set_pin_level(RELAY_2_GPIO, false);
/* Initialize the console uart */
configure_console();
spi_master_initialize();
// We need to configure the ade7753...
// ...to have a current gain of 2...
uint8_t gain = ADE7753_GAIN_PGA1_2;
ade7753_write(ADE7753_REGISTER_GAIN, &gain, ADE7753_REGISTER_GAIN_BYTES);
// and a measurment of 2000 half line cycles
uint32_t linecyc_int = 200;
ade7753_write(ADE7753_REGISTER_LINECYC, &linecyc_int, ADE7753_REGISTER_LINECYC_BYTES);
uint32_t mode_register = 0x0080;
ade7753_write(ADE7753_REGISTER_MODE, &mode_register, ADE7753_REGISTER_MODE_BYTES);
uint32_t irqen_register = 0x04;
ade7753_write(ADE7753_REGISTER_IRQEN, &irqen_register, ADE7753_REGISTER_IRQEN_BYTES);
uint8_t phase_offset = 14;
ade7753_write(ADE7753_REGISTER_PHCAL, &phase_offset, ADE7753_REGISTER_PHCAL_BYTES);
char input;
vfd_init();
//vfd_cursor_on();
vfd_gui_splash(__DATE__, __TIME__);
delay_s(5);
vfd_clear();
menu_state = MENU_STATE_VAFAAR;
for(;;) {
if (menu_state == MENU_STATE_SPLASH) {
if (changed == true) {
vfd_clear();
vfd_home();
vfd_gui_splash(__DATE__, __TIME__);
//vfd_gui_splash();
changed = false;
}
} else if (menu_state == MENU_STATE_VAFAAR) {
if (changed == true) {
vfd_clear();
changed = false;
}
vfd_home();
vfd_gui_vaf_aar();
} else if (menu_state == MENU_STATE_TRIG) {
if (changed == true) {
vfd_clear();
changed = false;
}
vfd_home();
vfd_gui_trig();
} else if (menu_state == MENU_STATE_COST) {
if (changed == true) {
vfd_clear();
changed = false;
}
vfd_home();
vfd_gui_cost();
} else if (menu_state == MENU_STATE_CONFIG) {
if (changed == true) {
vfd_clear();
changed = false;
}
vfd_home();
vfd_gui_config();
} else {
vfd_clear();
}
}
}
