static inline int spi_read(spi_t *obj)
{
while (!spi_readable(obj)) {
}
obj->spi->EVENTS_READY = 0;
return (int)obj->spi->RXD;
}
int spi_slave_read(spi_t *obj)
{
uint32_t rx_data;
while (!spi_readable(obj));
rx_data = SPI_ReadData(spi_address[obj->instance]);
return rx_data & 0xffff;
}
int spi_slave_read(spi_t *obj)
{
uint32_t rx_data;
while (!spi_readable(obj));
rx_data = DSPI_ReadData(spi_address[obj->spi.instance]);
DSPI_ClearStatusFlags(spi_address[obj->spi.instance], kDSPI_RxFifoDrainRequestFlag);
return rx_data & 0xffff;
}
int spi_master_write(spi_t *obj, int value) {
// wait tx buffer empty
while(!spi_writeable(obj));
obj->spi->D = (value & 0xff);
// wait rx buffer full
while (!spi_readable(obj));
return obj->spi->D & 0xff;
}
int spi_master_write(spi_t *obj, int value) {
// wait tx buffer empty
while(!spi_writeable(obj));
obj->spi->PUSHR = SPI_PUSHR_TXDATA(value & 0xff);
// wait rx buffer full
while (!spi_readable(obj));
return obj->spi->POPR;
}
int spi_master_write(spi_t *obj, int value)
{
uint32_t rx_data;
SPI_WriteData(spi_address[obj->instance], (uint16_t)value, kSPI_FrameAssert);
// wait rx buffer full
while (!spi_readable(obj));
rx_data = SPI_ReadData(spi_address[obj->instance]);
return rx_data & 0xffff;
}
int spi_master_write(spi_t *obj, int value) {
//clear RX buffer flag
obj->spi->SR |= SPI_SR_RFDF_MASK;
// wait tx buffer empty
while(!spi_writeable(obj));
obj->spi->PUSHR = SPI_PUSHR_TXDATA(value & 0xffff) /*| SPI_PUSHR_EOQ_MASK*/;
// wait rx buffer full
while (!spi_readable(obj));
return obj->spi->POPR;
}
int spi_master_write(spi_t *obj, int value) {
// wait tx buffer empty
while(!spi_writeable(obj));
dspi_command_config_t command = {0};
command.isEndOfQueue = true;
command.isChipSelectContinuous = 0;
dspi_hal_write_data_master_mode(obj->instance, &command, (uint16_t)value);
dspi_hal_clear_status_flag(obj->instance, kDspiTxFifoFillRequest);
// wait rx buffer full
while (!spi_readable(obj));
dspi_hal_clear_status_flag(obj->instance, kDspiRxFifoDrainRequest);
return dspi_hal_read_data(obj->instance) & 0xff;
}
int spi_master_write(spi_t *obj, int value)
{
uint32_t rx_data;
LPSPI_WriteData(spi_address[obj->instance], value);
// wait rx buffer full
while (!spi_readable(obj));
rx_data = LPSPI_ReadData(spi_address[obj->instance]);
LPSPI_ClearStatusFlags(spi_address[obj->instance], kLPSPI_TransferCompleteFlag);
return rx_data & 0xffff;
}
int spi_master_write(spi_t *obj, int value) {
// wait tx buffer empty
while(!spi_writeable(obj));
dspi_command_config_t command = {0};
command.isEndOfQueue = true;
command.isChipSelectContinuous = 0;
DSPI_HAL_WriteDataMastermode(obj->spi.address, &command, (uint16_t)value);
DSPI_HAL_ClearStatusFlag(obj->spi.address, kDspiTxFifoFillRequest);
// wait rx buffer full
while (!spi_readable(obj));
DSPI_HAL_ClearStatusFlag(obj->spi.address, kDspiRxFifoDrainRequest);
return DSPI_HAL_ReadData(obj->spi.address) & 0xff;
}
int spi_master_write(spi_t *obj, int value)
{
dspi_command_data_config_t command;
uint32_t rx_data;
DSPI_GetDefaultDataCommandConfig(&command);
command.isEndOfQueue = true;
DSPI_MasterWriteDataBlocking(spi_address[obj->spi.instance], &command, (uint16_t)value);
DSPI_ClearStatusFlags(spi_address[obj->spi.instance], kDSPI_TxFifoFillRequestFlag);
// wait rx buffer full
while (!spi_readable(obj));
rx_data = DSPI_ReadData(spi_address[obj->spi.instance]);
DSPI_ClearStatusFlags(spi_address[obj->spi.instance], kDSPI_RxFifoDrainRequestFlag | kDSPI_EndOfQueueFlag);
return rx_data & 0xffff;
}
int spi_slave_receive(spi_t *obj) {
return spi_readable(obj);
}
int spi_slave_receive(spi_t *obj) {
return (spi_readable(obj) && !spi_busy(obj)) ? (1) : (0);
}
static inline int spi_read(spi_t *obj) {
while (!spi_readable(obj));
return obj->spi->RXDAT;
}
static inline int spi_read(spi_t *obj)
{
while (!spi_readable(obj));
return obj->spi->RXDAT & 0xffff; // Only the lower 16 bits contain data
}
