int lg4573_spi_startup(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int spi_mode)
{
struct spi_slave *spi;
int ret;
spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
if (!spi) {
debug("%s: Failed to set up slave\n", __func__);
return -1;
}
ret = spi_claim_bus(spi);
if (ret) {
debug("%s: Failed to claim SPI bus: %d\n", __func__, ret);
goto err_claim_bus;
}
lb043wv_display_mode_settings(spi);
lb043wv_power_settings(spi);
lb043wv_gamma_settings(spi);
lb043wv_display_on(spi);
return 0;
err_claim_bus:
spi_free_slave(spi);
return -1;
}
ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len)
{
struct spi_slave *slave;
u8 cmd = SPI_EEPROM_READ;
slave = spi_setup_slave(CONFIG_DEFAULT_SPI_BUS, 1, 1000000,
CONFIG_DEFAULT_SPI_MODE);
if (!slave)
return 0;
spi_claim_bus(slave);
/* command */
if (spi_xfer(slave, 8, &cmd, NULL, SPI_XFER_BEGIN))
return -1;
/*
* if alen == 3, addr[0] is the block number, we never use it here.
* All we need are the lower 16 bits.
*/
if (alen == 3)
addr++;
/* address, and data */
if (spi_xfer(slave, 16, addr, NULL, 0))
return -1;
if (spi_xfer(slave, 8 * len, NULL, buffer, SPI_XFER_END))
return -1;
spi_release_bus(slave);
spi_free_slave(slave);
return len;
}
static int lq035q1_control(unsigned char reg, unsigned short value)
{
int ret;
u8 regs[3] = {LQ035_INDEX, 0, 0};
u8 data[3] = {LQ035_DATA, 0, 0};
u8 dummy[3];
regs[2] = reg;
data[1] = value >> 8;
data[2] = value & 0xFF;
if (!slave) {
/* FIXME: Verify the max SCK rate */
slave = spi_setup_slave(CONFIG_LQ035Q1_SPI_BUS,
CONFIG_LQ035Q1_SPI_CS, 20000000,
SPI_MODE_3);
if (!slave)
return -1;
}
if (spi_claim_bus(slave))
return -1;
ret = spi_xfer(slave, 24, regs, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
ret |= spi_xfer(slave, 24, data, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
spi_release_bus(slave);
return ret;
}
struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode)
{
struct mmc *mmc;
mmc = malloc(sizeof(*mmc));
if (!mmc)
return NULL;
memset(mmc, 0, sizeof(*mmc));
mmc->priv = spi_setup_slave(bus, cs, speed, mode);
if (!mmc->priv) {
free(mmc);
return NULL;
}
sprintf(mmc->name, "MMC_SPI");
mmc->send_cmd = mmc_spi_request;
mmc->set_ios = mmc_spi_set_ios;
mmc->init = mmc_spi_init_p;
mmc->getcd = NULL;
mmc->host_caps = MMC_MODE_SPI;
mmc->voltages = MMC_SPI_VOLTAGE;
mmc->f_max = speed;
mmc->f_min = MMC_SPI_MIN_CLOCK;
mmc->block_dev.part_type = PART_TYPE_DOS;
mmc_register(mmc);
return mmc;
}
static struct spi_slave *enbw_cmc_init_spi(void)
{
struct spi_slave *spi;
int ret;
spi = spi_setup_slave(0, 0, 1000000, 0);
if (!spi) {
printf("Failed to set up slave\n");
return NULL;
}
ret = spi_claim_bus(spi);
if (ret) {
debug("Failed to claim SPI bus: %d\n", ret);
goto err_claim_bus;
}
ret = enbw_cmc_switch_read_ident(spi);
if (ret)
goto err_read;
return spi;
err_read:
spi_release_bus(spi);
err_claim_bus:
spi_free_slave(spi);
return NULL;
}
static int do_spi_xfer(int bus, int cs)
{
struct spi_slave *slave;
int rcode = 0;
slave = spi_setup_slave(bus, cs, 1000000, mode);
if (!slave) {
printf("Invalid device %d:%d\n", bus, cs);
return -EINVAL;
}
spi_claim_bus(slave);
if (spi_xfer(slave, bitlen, dout, din,
SPI_XFER_BEGIN | SPI_XFER_END) != 0) {
printf("Error during SPI transaction\n");
rcode = -EIO;
} else {
int j;
for (j = 0; j < ((bitlen + 7) / 8); j++)
printf("%02X", din[j]);
printf("\n");
}
spi_release_bus(slave);
spi_free_slave(slave);
return rcode;
}
int rtc_set(struct rtc_time *rtc)
{
u32 time, day, reg;
if (!slave) {
/* FIXME: Verify the max SCK rate */
slave = spi_setup_slave(CONFIG_MC13783_SPI_BUS,
CONFIG_MC13783_SPI_CS, 1000000,
SPI_MODE_2 | SPI_CS_HIGH);
if (!slave)
return -1;
}
time = mktime(rtc->tm_year, rtc->tm_mon, rtc->tm_mday,
rtc->tm_hour, rtc->tm_min, rtc->tm_sec);
day = time / 86400;
time %= 86400;
if (spi_claim_bus(slave))
return -1;
reg = 0x2c000000 | day | 0x80000000;
spi_xfer(slave, 32, (uchar *)®, (uchar *)&day,
SPI_XFER_BEGIN | SPI_XFER_END);
reg = 0x28000000 | time | 0x80000000;
spi_xfer(slave, 32, (uchar *)®, (uchar *)&time,
SPI_XFER_BEGIN | SPI_XFER_END);
spi_release_bus(slave);
return -1;
}
/* set clock time from *tmp in DS1306 RTC */
void rtc_set (struct rtc_time *tmp)
{
/* Assuming Vcc = 2.0V (lowest speed) */
if (!slave) {
slave = spi_setup_slave(0, CFG_SPI_RTC_DEVID, 600000,
SPI_MODE_3 | SPI_CS_HIGH);
if (!slave)
return;
}
if (spi_claim_bus(slave))
return;
debug ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
rtc_write (RTC_SECONDS, bin2bcd (tmp->tm_sec));
rtc_write (RTC_MINUTES, bin2bcd (tmp->tm_min));
rtc_write (RTC_HOURS, bin2bcd (tmp->tm_hour));
rtc_write (RTC_DAY_OF_WEEK, bin2bcd (tmp->tm_wday + 1));
rtc_write (RTC_DATE_OF_MONTH, bin2bcd (tmp->tm_mday));
rtc_write (RTC_MONTH, bin2bcd (tmp->tm_mon));
rtc_write (RTC_YEAR, bin2bcd (tmp->tm_year - 2000));
spi_release_bus(slave);
}
struct spi_slave *pmic_spi_probe(void)
{
return spi_setup_slave(CONFIG_FSL_PMIC_BUS,
CONFIG_FSL_PMIC_CS,
CONFIG_FSL_PMIC_CLK,
CONFIG_FSL_PMIC_MODE);
}
/* reset the DS1306 */
void rtc_reset (void)
{
/* Assuming Vcc = 2.0V (lowest speed) */
if (!slave) {
slave = spi_setup_slave(0, CFG_SPI_RTC_DEVID, 600000,
SPI_MODE_3 | SPI_CS_HIGH);
if (!slave)
return;
}
if (spi_claim_bus(slave))
return;
/* clear the control register */
rtc_write (RTC_CONTROL, 0x00); /* 1st step: reset WP */
rtc_write (RTC_CONTROL, 0x00); /* 2nd step: reset 1Hz, AIE1, AIE0 */
/* reset all alarms */
rtc_write (RTC_SECONDS_ALARM0, 0x00);
rtc_write (RTC_SECONDS_ALARM1, 0x00);
rtc_write (RTC_MINUTES_ALARM0, 0x00);
rtc_write (RTC_MINUTES_ALARM1, 0x00);
rtc_write (RTC_HOURS_ALARM0, 0x00);
rtc_write (RTC_HOURS_ALARM1, 0x00);
rtc_write (RTC_DAY_OF_WEEK_ALARM0, 0x00);
rtc_write (RTC_DAY_OF_WEEK_ALARM1, 0x00);
spi_release_bus(slave);
}
struct spi_slave *pmic_spi_probe(struct pmic *p)
{
return spi_setup_slave(p->bus,
p->hw.spi.cs,
p->hw.spi.clk,
p->hw.spi.mode);
}
static int sx151x_spi_read(int chip, unsigned char reg)
{
struct spi_slave *slave;
int ret;
slave = spi_setup_slave(CONFIG_SX151X_SPI_BUS, chip, 1000000,
SPI_MODE_0);
if (!slave)
return 0;
spi_claim_bus(slave);
ret = spi_w8r8(slave, reg | 0x80);
if (ret < 0)
printf("spi%d.%d read fail: can't read %02x: %d\n",
CONFIG_SX151X_SPI_BUS, chip, reg, ret);
else
printf("spi%d.%d read register 0x%02x: 0x%02x\n",
CONFIG_SX151X_SPI_BUS, chip, reg, ret);
spi_release_bus(slave);
spi_free_slave(slave);
return ret;
}
static int sx151x_spi_write(int chip, unsigned char reg, unsigned char val)
{
struct spi_slave *slave;
unsigned char buf[2];
int ret;
slave = spi_setup_slave(CONFIG_SX151X_SPI_BUS, chip, 1000000,
SPI_MODE_0);
if (!slave)
return 0;
spi_claim_bus(slave);
buf[0] = reg;
buf[1] = val;
ret = spi_xfer(slave, 16, buf, NULL, SPI_XFER_BEGIN | SPI_XFER_END);
if (ret < 0)
printf("spi%d.%d write fail: can't write %02x to %02x: %d\n",
CONFIG_SX151X_SPI_BUS, chip, val, reg, ret);
else
printf("spi%d.%d write 0x%02x to register 0x%02x\n",
CONFIG_SX151X_SPI_BUS, chip, val, reg);
spi_release_bus(slave);
spi_free_slave(slave);
return ret;
}
struct spi_flash *spi_flash_probe(unsigned int busnum, unsigned int cs,
unsigned int max_hz, unsigned int spi_mode)
{
struct spi_slave *bus;
struct spi_flash *flash;
bus = spi_setup_slave(busnum, cs, max_hz, spi_mode);
if (!bus)
return NULL;
/* Allocate space if needed (not used by sf-uclass */
flash = calloc(1, sizeof(*flash));
if (!flash) {
debug("SF: Failed to allocate spi_flash\n");
return NULL;
}
flash->spi = bus;
if (spi_flash_probe_slave(flash)) {
spi_free_slave(bus);
free(flash);
return NULL;
}
return flash;
}
int google_chromeec_command(struct chromeec_command *cec_command)
{
static struct spi_slave *slave = NULL;
if (!slave)
slave = spi_setup_slave(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS,
CONFIG_EC_GOOGLE_CHROMEEC_SPI_CHIP);
return crosec_command_proto(cec_command, crosec_spi_io, slave);
}
void work_92105_display_init(void)
{
int claim_err;
char *display_contrast_str;
uint8_t display_contrast = CONTRAST_DEFAULT;
uint8_t enable_backlight = 0x96;
slave = spi_setup_slave(0, 0, 500000, 0);
if (!slave) {
printf("Failed to set up SPI slave\n");
return;
}
claim_err = spi_claim_bus(slave);
if (claim_err)
debug("Failed to claim SPI bus: %d\n", claim_err);
/* enable backlight */
i2c_write(0x2c, 0x01, 1, &enable_backlight, 1);
/* set display contrast */
display_contrast_str = getenv("fwopt_dispcontrast");
if (display_contrast_str)
display_contrast = simple_strtoul(display_contrast_str,
NULL, 10);
i2c_write(0x2c, 0x00, 1, &display_contrast, 1);
/* request GPO_15 as an output initially set to 1 */
gpio_request(GPO_15, "MAX6957_nCS");
gpio_direction_output(GPO_15, 1);
/* enable MAX6957 portexpander */
max6957aax_write(MAX6957_CONF, 0x01);
/* configure pin 8 as input, pins 9..19 as outputs */
max6957aax_write(MAX6957_CONF_08_11, 0x56);
max6957aax_write(MAX6957_CONF_12_15, 0x55);
max6957aax_write(MAX6957_CONF_16_19, 0x55);
/* initialize HD44780 */
max6957aax_write(MAX6957AAX_HD44780_EN, 0);
hd44780_instruction(HD44780_FUNCTION_SET);
hd44780_instruction(HD44780_DISPLAY_ON_OFF_CONTROL);
hd44780_instruction(HD44780_ENTRY_MODE_SET);
/* write custom character glyphs */
hd44780_init_char_gen();
/* Show U-Boot version, date and time as a sign-of-life */
hd44780_instruction(HD44780_CLEAR_DISPLAY);
hd44780_instruction(HD44780_SET_DDRAM_ADDR | 0);
hd44780_write_str(U_BOOT_VERSION);
hd44780_instruction(HD44780_SET_DDRAM_ADDR | 64);
hd44780_write_str(U_BOOT_DATE);
hd44780_instruction(HD44780_SET_DDRAM_ADDR | 64 | 20);
hd44780_write_str(U_BOOT_TIME);
}
int google_chromeec_command(struct chromeec_command *cec_command)
{
static struct spi_slave *slave = NULL;
if (!slave) {
slave = spi_setup_slave(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS,
CONFIG_EC_GOOGLE_CHROMEEC_SPI_CHIP);
stopwatch_init(&cs_cooldown_sw);
}
return crosec_command_proto(cec_command, crosec_spi_io, slave);
}
struct spi_flash *spi_flash_probe(unsigned int busnum, unsigned int cs,
unsigned int max_hz, unsigned int spi_mode)
{
struct spi_slave *bus;
bus = spi_setup_slave(busnum, cs, max_hz, spi_mode);
if (!bus)
return NULL;
return spi_flash_probe_tail(bus);
}
int rtc_get(struct rtc_time *rtc)
{
u32 day1, day2, time;
u32 reg;
int err, tim, i = 0;
if (!slave) {
/* FIXME: Verify the max SCK rate */
slave = spi_setup_slave(CONFIG_MC13783_SPI_BUS,
CONFIG_MC13783_SPI_CS, 1000000,
SPI_MODE_2 | SPI_CS_HIGH);
if (!slave)
return -1;
}
if (spi_claim_bus(slave))
return -1;
do {
reg = 0x2c000000;
err = spi_xfer(slave, 32, (uchar *)®, (uchar *)&day1,
SPI_XFER_BEGIN | SPI_XFER_END);
if (err)
return err;
reg = 0x28000000;
err = spi_xfer(slave, 32, (uchar *)®, (uchar *)&time,
SPI_XFER_BEGIN | SPI_XFER_END);
if (err)
return err;
reg = 0x2c000000;
err = spi_xfer(slave, 32, (uchar *)®, (uchar *)&day2,
SPI_XFER_BEGIN | SPI_XFER_END);
if (err)
return err;
} while (day1 != day2 && i++ < 3);
spi_release_bus(slave);
tim = day1 * 86400 + time;
to_tm(tim, rtc);
rtc->tm_yday = 0;
rtc->tm_isdst = 0;
return 0;
}
ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len)
{
struct spi_slave *slave;
char buf[3];
ulong start;
slave = spi_setup_slave(CONFIG_DEFAULT_SPI_BUS, 1, 1000000,
CONFIG_DEFAULT_SPI_MODE);
if (!slave)
return 0;
spi_claim_bus(slave);
buf[0] = SPI_EEPROM_WREN;
if (spi_xfer(slave, 8, buf, NULL, SPI_XFER_BEGIN | SPI_XFER_END))
return -1;
buf[0] = SPI_EEPROM_WRITE;
/* As for reading, drop addr[0] if alen is 3 */
if (alen == 3) {
alen--;
addr++;
}
memcpy(buf + 1, addr, alen);
/* command + addr, then data */
if (spi_xfer(slave, 24, buf, NULL, SPI_XFER_BEGIN))
return -1;
if (spi_xfer(slave, len * 8, buffer, NULL, SPI_XFER_END))
return -1;
start = get_timer(0);
do {
buf[0] = SPI_EEPROM_RDSR;
buf[1] = 0;
spi_xfer(slave, 16, buf, buf, SPI_XFER_BEGIN | SPI_XFER_END);
if (!(buf[1] & 1))
break;
} while (get_timer(start) < CONFIG_SYS_SPI_WRITE_TOUT);
if (buf[1] & 1)
printf("*** spi_write: Timeout while writing!\n");
spi_release_bus(slave);
spi_free_slave(slave);
return len;
}
int google_chromeec_command(struct chromeec_command *cec_command)
{
static int done = 0;
static struct spi_slave slave;
if (!done) {
if (spi_setup_slave(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS,
CONFIG_EC_GOOGLE_CHROMEEC_SPI_CHIP, &slave))
return -1;
stopwatch_init(&cs_cooldown_sw);
done = 1;
}
return crosec_command_proto(cec_command, crosec_spi_io, &slave);
}
/* control backlight pwm (display brightness).
* allow values 0-250 with 0 = turn off and 250 = max brightness
*/
void mergerbox_tft_dim(u16 value)
{
struct spi_slave *slave;
u16 din;
u16 dout = 0;
if (value > 0 && value < 250)
dout = 0x4000 | value;
slave = spi_setup_slave(0, 0, 1000000, SPI_MODE_0 | SPI_CS_HIGH);
spi_claim_bus(slave);
spi_xfer(slave, 16, &dout, &din, SPI_XFER_BEGIN | SPI_XFER_END);
spi_release_bus(slave);
spi_free_slave(slave);
}
struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode)
{
struct mmc *mmc;
struct spi_slave *spi;
spi = spi_setup_slave(bus, cs, speed, mode);
if (spi == NULL)
return NULL;
mmc_spi_cfg.f_max = speed;
mmc = mmc_create(&mmc_spi_cfg, spi);
if (mmc == NULL) {
spi_free_slave(spi);
return NULL;
}
return mmc;
}
static u32 pmic_reg(struct pmic *p, u32 reg, u32 *val, u32 write)
{
u32 pmic_tx, pmic_rx;
u32 tmp;
if (!slave) {
slave = spi_setup_slave(p->bus, p->hw.spi.cs, p->hw.spi.clk,
p->hw.spi.mode);
if (!slave)
return -ENODEV;
}
if (check_reg(p, reg))
return -EINVAL;
if (spi_claim_bus(slave))
return -EBUSY;
pmic_tx = p->hw.spi.prepare_tx(reg, val, write);
tmp = cpu_to_be32(pmic_tx);
if (spi_xfer(slave, pmic_spi_bitlen, &tmp, &pmic_rx,
pmic_spi_flags))
goto err;
if (write) {
pmic_tx = p->hw.spi.prepare_tx(reg, val, 0);
tmp = cpu_to_be32(pmic_tx);
if (spi_xfer(slave, pmic_spi_bitlen, &tmp, &pmic_rx,
pmic_spi_flags))
goto err;
}
spi_release_bus(slave);
*val = cpu_to_be32(pmic_rx);
return 0;
err:
spi_release_bus(slave);
return -ENOTSUPP;
}
static bool board_ksz_init(void)
{
static bool switch_is_alive = false;
if (!switch_is_alive) {
struct spi_slave *slave = spi_setup_slave(0, 1, KSZ_MAX_HZ, SPI_MODE_3);
if (slave) {
if (!spi_claim_bus(slave)) {
bool phy_is_ksz = (ksz8893m_reg_read(slave, KSZ_REG_CHID) == 0x88);
int ret = phy_is_ksz ? ksz8893m_reset(slave) : 0;
switch_is_alive = (ret == 0);
spi_release_bus(slave);
}
spi_free_slave(slave);
}
}
return switch_is_alive;
}
void dmw_amoled_init(void)
{
amoled_spi = spi_setup_slave(CONFIG_DMW_AMOLED_SPI_UNIT, CONFIG_DMW_GPIO_AMOLED_CS, 0, 0);
gpio_direction_output(CONFIG_DMW_GPIO_AMOLED_RESET, LED_ACTIVE);
gpio_enable(CONFIG_DMW_GPIO_AMOLED_RESET);
dmw_amoled_reset();
amoled_write_simple_command(amoled_spi, 0x31, 0x08); // SCTE set
amoled_write_simple_command(amoled_spi, 0x32, 0x14); // SCWE set
amoled_write_simple_command(amoled_spi, 0x30, 0x02); // Gateless signal
amoled_write_simple_command(amoled_spi, 0x27, 0x01); // Gateless signal
/* Display condition set */
amoled_write_simple_command(amoled_spi, 0x12, 0x08); // VBP set
amoled_write_simple_command(amoled_spi, 0x13, 0x08); // VFP set
amoled_write_simple_command(amoled_spi, 0x15, 0x00); // Display con
amoled_write_simple_command(amoled_spi, 0x16, 0x00); // Color depth set
amoled_pentile_key(amoled_spi);
amoled_write_simple_command(amoled_spi, 0x39, 0x44); // Gamma set select
/* Normal gamma table */
amoled_run_sequence(amoled_spi, amoled_gamma_table_l_220);
/* Analog power condition set */
amoled_write_simple_command(amoled_spi, 0x17, 0x22); // VBP set
amoled_write_simple_command(amoled_spi, 0x18, 0x33); // VFP set
amoled_write_simple_command(amoled_spi, 0x19, 0x03); // Display con
amoled_write_simple_command(amoled_spi, 0x1A, 0x01); // Color depth set
amoled_write_simple_command(amoled_spi, 0x22, 0xA4);
amoled_write_simple_command(amoled_spi, 0x23, 0x00); // Gamma set select
amoled_write_simple_command(amoled_spi, 0x26, 0xA0); // Gamma set select
/* STB off */
amoled_write_simple_command(amoled_spi, 0x1D, 0xA0);
mdelay(100);
/* Display ON */
amoled_write_simple_command(amoled_spi, 0x14, 0x03);
}
void nowplus_lcd_disable(void)
{
u32 memsize = gdev.winSizeX*gdev.winSizeY*gdev.gdfBytesPP;
memset((void *)gdev.frameAdrs, 0x00, memsize);
//disable graphics pipeline
//writel(readl(DISPC_GFX_ATTRIBUTES) & ~(0x1), DISPC_GFX_ATTRIBUTES);
#if 0
static unsigned int bus;
static unsigned int cs;
static unsigned int mode;
static int bitlen;
static uchar dout[MAX_SPI_BYTES];
static uchar din[MAX_SPI_BYTES];
static struct spi_slave *slave;
slave = spi_setup_slave(0, 0, 37500000, mode);
if (!slave) {
printf("Invalid device %d:%d\n", bus, cs);
return 1;
}
spi_claim_bus(slave);
//spi1write(0x14, 0x00); // set black
//spi1write(0x1D, 0xA1); // standby on
if(spi_xfer(slave, bitlen, dout, din,
SPI_XFER_BEGIN | SPI_XFER_END) != 0) {
printf("Error during SPI transaction\n");
rcode = 1;
}
spi_release_bus(slave);
spi_free_slave(slave);
//Wait 200ms
msleep(250); //mdelay(200);
#endif
#if 0
//disable display
writel(readl(DISPC_CONTROL) & ~0x3, DISPC_CONTROL);
#endif
}
int tis_init(void)
{
struct spi_slave spi;
struct tpm2_info info;
if (spi_setup_slave(CONFIG_DRIVER_TPM_SPI_BUS,
CONFIG_DRIVER_TPM_SPI_CHIP, &spi)) {
printk(BIOS_ERR, "Failed to setup TPM SPI slave\n");
return -1;
}
if (tpm2_init(&spi)) {
printk(BIOS_ERR, "Failed to initialize TPM SPI interface\n");
return -1;
}
tpm2_get_info(&info);
printk(BIOS_INFO, "Initialized TPM device %s revision %d\n",
tis_get_dev_name(&info), info.revision);
return 0;
}
int do_spi (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
struct spi_slave *slave;
char *cp = 0;
uchar tmp;
int j;
int rcode = 0;
/*
* We use the last specified parameters, unless new ones are
* entered.
*/
if ((flag & CMD_FLAG_REPEAT) == 0)
{
if (argc >= 2) {
mode = CONFIG_DEFAULT_SPI_MODE;
bus = simple_strtoul(argv[1], &cp, 10);
if (*cp == ':') {
cs = simple_strtoul(cp+1, &cp, 10);
} else {
cs = bus;
bus = CONFIG_DEFAULT_SPI_BUS;
}
if (*cp == '.')
mode = simple_strtoul(cp+1, NULL, 10);
}
if (argc >= 3)
bitlen = simple_strtoul(argv[2], NULL, 10);
if (argc >= 4) {
cp = argv[3];
for(j = 0; *cp; j++, cp++) {
tmp = *cp - '0';
if(tmp > 9)
tmp -= ('A' - '0') - 10;
if(tmp > 15)
tmp -= ('a' - 'A');
if(tmp > 15) {
printf("Hex conversion error on %c\n", *cp);
return 1;
}
if((j % 2) == 0)
dout[j / 2] = (tmp << 4);
else
dout[j / 2] |= tmp;
}
}
}
if ((bitlen < 0) || (bitlen > (MAX_SPI_BYTES * 8))) {
printf("Invalid bitlen %d\n", bitlen);
return 1;
}
slave = spi_setup_slave(bus, cs, 1000000, mode);
if (!slave) {
printf("Invalid device %d:%d\n", bus, cs);
return 1;
}
spi_claim_bus(slave);
if(spi_xfer(slave, bitlen, dout, din,
SPI_XFER_BEGIN | SPI_XFER_END) != 0) {
printf("Error during SPI transaction\n");
rcode = 1;
} else {
for(j = 0; j < ((bitlen + 7) / 8); j++) {
printf("%02X", din[j]);
}
printf("\n");
}
spi_release_bus(slave);
spi_free_slave(slave);
return rcode;
}
int do_spi (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
struct spi_slave *slave;
char *cp = 0;
uchar tmp;
int j;
int rcode = 0;
/*
* We use the last specified parameters, unless new ones are
* entered.
*/
if ((flag & CMD_FLAG_REPEAT) == 0)
{
if (argc >= 2)
device = simple_strtoul(argv[1], NULL, 10);
if (argc >= 3)
bitlen = simple_strtoul(argv[2], NULL, 10);
if (argc >= 4) {
cp = argv[3];
for(j = 0; *cp; j++, cp++) {
tmp = *cp - '0';
if(tmp > 9)
tmp -= ('A' - '0') - 10;
if(tmp > 15)
tmp -= ('a' - 'A');
if(tmp > 15) {
printf("Hex conversion error on %c, giving up.\n", *cp);
return 1;
}
if((j % 2) == 0)
dout[j / 2] = (tmp << 4);
else
dout[j / 2] |= tmp;
}
}
}
if ((bitlen < 0) || (bitlen > (MAX_SPI_BYTES * 8))) {
printf("Invalid bitlen %d, giving up.\n", bitlen);
return 1;
}
/* FIXME: Make these parameters run-time configurable */
slave = spi_setup_slave(CONFIG_DEFAULT_SPI_BUS, device, 1000000,
CONFIG_DEFAULT_SPI_MODE);
if (!slave) {
printf("Invalid device %d, giving up.\n", device);
return 1;
}
debug ("spi chipsel = %08X\n", device);
spi_claim_bus(slave);
if(spi_xfer(slave, bitlen, dout, din,
SPI_XFER_BEGIN | SPI_XFER_END) != 0) {
printf("Error with the SPI transaction.\n");
rcode = 1;
} else {
for(j = 0; j < ((bitlen + 7) / 8); j++) {
printf("%02X", din[j]);
}
printf("\n");
}
spi_release_bus(slave);
spi_free_slave(slave);
return rcode;
}
