int spm_set_vcore_dvs_voltage(unsigned int opp)
{
int r;
unsigned long flags;
spin_lock_irqsave(&__spm_lock, flags);
switch (opp) {
case OPP_0:
spm_write(SPM_PCM_SRC_REQ, spm_read(SPM_PCM_SRC_REQ) | SR_PCM_F26M_REQ);
r = wait_pcm_complete_dvs(get_vcore_sta() == VCORE_STA_HPM,
3 * PER_OPP_DVS_US /* 1.15->1.05->1.15 */);
break;
case OPP_1:
spm_write(SPM_PCM_SRC_REQ, spm_read(SPM_PCM_SRC_REQ) & ~SR_PCM_F26M_REQ);
r = 0; /* unrequest, no need to wait */
break;
default:
spm_crit("[VcoreFS] *** FAILED: OPP INDEX IS INCORRECT ***\n");
spin_unlock_irqrestore(&__spm_lock, flags);
return -EINVAL;
}
if (r >= 0) { /* DVS pass */
r = 0;
} else {
spm_dump_vcore_dvs_regs(NULL);
BUG();
}
spin_unlock_irqrestore(&__spm_lock, flags);
return r;
}
static void twam_handler(struct twam_sig *twamsig)
{
spm_crit("sig_high = %u%% %u%% %u%% %u%%, r13 = 0x%x\n",
get_percent(twamsig->sig0,SPM_TWAM_MONITOR_TICK),
get_percent(twamsig->sig1,SPM_TWAM_MONITOR_TICK),
get_percent(twamsig->sig2,SPM_TWAM_MONITOR_TICK),
get_percent(twamsig->sig3,SPM_TWAM_MONITOR_TICK),
spm_read(SPM_PCM_REG13_DATA));
}
static void twam_handler(struct twam_sig *twamsig)
{
spm_crit("sig_high = %u%% %u%% %u%% %u%%, r13 = 0x%x\n",
get_high_percent(twamsig->sig0),
get_high_percent(twamsig->sig1),
get_high_percent(twamsig->sig2),
get_high_percent(twamsig->sig3),
spm_read(SPM_PCM_REG13_DATA));
}
void spm_go_to_vcore_dvfs(u32 spm_flags, u32 spm_data)
{
unsigned long flags;
spin_lock_irqsave(&__spm_lock, flags);
mt_cpufreq_set_pmic_phase(PMIC_WRAP_PHASE_NORMAL);
__go_to_vcore_dvfs(spm_flags, 0, 0);
spm_crit("[VcoreFS] STA: 0x%x, REQ: 0x%x\n", spm_read(SPM_SLEEP_DVFS_STA), spm_read(SPM_PCM_SRC_REQ));
spin_unlock_irqrestore(&__spm_lock, flags);
}