コード例 #1
0
ファイル: ModelValidator.cpp プロジェクト: ufwt/gosat
bool
ModelValidator::isValid(z3::expr smt_expr, const std::vector<double>& model)
{
    auto var_symbols = m_ir_gen->getVars();
    assert((var_symbols.size() == model.size()) && "Model size mismatch!");

    // now substituting fpa wrapped variables with consts from model
    z3::expr_vector src_1(smt_expr.ctx()), dst_1(smt_expr.ctx());
    for (const auto& symbol_pair:m_ir_gen->getVarsFPAWrapped()) {
        src_1.push_back(*symbol_pair.first->expr());
        // XXX: assuming TO_FPA should invert type casting
        auto kind = symbol_pair.second->kind() == SymbolKind::kFP32Var
                    ? SymbolKind::kFP64Var : SymbolKind::kFP32Var;
        dst_1.push_back(genFPConst(smt_expr, kind,
                                   symbol_pair.second->id(), model));
    }
    z3::expr expr_sub_1 = smt_expr.substitute(src_1, dst_1);

    // now substituting actual variables with consts from model
    z3::expr_vector src_2(smt_expr.ctx()), dst_2(smt_expr.ctx());
    for (const auto symbol:var_symbols) {
        src_2.push_back(*symbol->expr());
        dst_2.push_back(genFPConst(smt_expr, symbol->kind(),
                                   symbol->id(), model));
    }
    z3::expr expr_sub_2 = expr_sub_1.substitute(src_2, dst_2);
    z3::solver solver(smt_expr.ctx());
    solver.add(expr_sub_2);
    return solver.check() == z3::check_result::sat;
}
コード例 #2
0
ファイル: testbench.cpp プロジェクト: kaiserhaz/SystemC
int sc_main(int argn, char* argc[])          // SystemC main program
{
  sca_tdf::sca_signal<double> sig_1;         // Signal to connect source w sink

  sin_source_with_noise src_1("src_1");      // Instantiate source
    src_1.out(sig_1);                        // Connect (bind) with signal

  sink sink_1("sink_1");                     // Instantiate sink
    sink_1.in(sig_1);                        // Connect (bind) with signal

  sca_trace_file* tfp =                      // Open trace file
    sca_create_vcd_trace_file("testbench");
    sca_trace(tfp, sig_1, "sig_1");          // Define which signal to trace

  sc_start(10.0, SC_MS);                     // Start simulation for 10 ms

  sca_close_vcd_trace_file(tfp);             // Close trace file

  return 0;                                  // Exit with return code 0
}