/* Interrupt fired when TX shift register becomes empty */ static irqreturn_t spi_stm_irq(int irq, void *dev_id) { struct spi_stm *spi_stm = (struct spi_stm *)dev_id; /* Read RX FIFO */ ssc_read_rx_fifo(spi_stm); /* Fill TX FIFO */ if (spi_stm->words_remaining) { ssc_write_tx_fifo(spi_stm); } else { /* TX/RX complete */ ssc_store32(spi_stm, SSC_IEN, 0x0); complete(&spi_stm->done); } return IRQ_HANDLED; }
/* Interrupt fired when TX shift register becomes empty */ static irqreturn_t spi_st_irq(int irq, void *dev_id) { struct spi_st *spi_st = (struct spi_st *)dev_id; /* Read RX FIFO */ ssc_read_rx_fifo(spi_st); /* Fill TX FIFO */ if (spi_st->words_remaining) { ssc_write_tx_fifo(spi_st); } else { /* TX/RX complete */ writel_relaxed(0x0, spi_st->base + SSC_IEN); /* * read SSC_IEN to ensure that this bit is set * before re-enabling interrupt */ readl(spi_st->base + SSC_IEN); complete(&spi_st->done); } return IRQ_HANDLED; }