static int zyloniteii_wm8753_hifi_prepare(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai_link *machine = rtd->dai;
struct snd_soc_dai *cpu_dai = machine->cpu_dai;
struct ssp_device *ssp = cpu_dai->private_data;
struct snd_pcm_runtime *runtime = substream->runtime;
unsigned long rate = runtime->rate;
int ceoff;
dbg("zyloniteii_wm8753_hifi_prepare\n");
__raw_writel(0xE1C0003F, ssp->mmio_base + SSCR0);
__raw_writel(0x00701DC0, ssp->mmio_base + SSCR1);
__raw_writel(0x3, ssp->mmio_base + SSTSA);
__raw_writel(0x3, ssp->mmio_base + SSRSA);
__raw_writel(0x40200004, ssp->mmio_base + SSPSP);
ceoff = ssp_conf_lookup(rate);
if (ceoff >= 0 )
{
ssp_set_clock(ceoff);
} else {
printk(KERN_ERR "Wrong audio sample rate\n");
}
return 0;
}
static int ts4700_wm8750_prepare(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai_link *machine = rtd->dai;
struct snd_soc_dai *cpu_dai = machine->cpu_dai;
struct ssp_device *ssp = cpu_dai->private_data;
struct snd_pcm_runtime *runtime = substream->runtime;
unsigned long rate = runtime->rate;
int ceoff;
cpu_dai->playback.channels_min = 2;
cpu_dai->playback.channels_max = 2;
#if defined(CONFIG_SND_SOC_SII9022) || defined(CONFIG_SND_SOC_SII9022_MODULE)
__raw_writel(0xE1D0003F, ssp->mmio_base + SSCR0);
__raw_writel(0x10F01DC0, ssp->mmio_base + SSCR1);
__raw_writel(0x00F01DC0, ssp->mmio_base + SSCR1);
__raw_writel(0x42200000, ssp->mmio_base + SSPSP);
#endif
__raw_writel(0x3, ssp->mmio_base + SSTSA);
__raw_writel(0x3, ssp->mmio_base + SSRSA);
ceoff = ssp_conf_lookup(rate);
if (ceoff >= 0 )
{
ssp_set_clock(ceoff);
} else {
printk(KERN_ERR "Wrong audio sample rate\n");
}
/* we have to set the value of FRDC in SSCR0 here because the dai doesn't do it */
__raw_writel(__raw_readl(ssp->mmio_base + SSCR0) | 0x01000000,
ssp->mmio_base + SSCR0);
return 0;
}
/***********************************************************************
*
* Function: ssp_configure
*
* Purpose: Configure SSP interface
*
* Processing:
* Setup the general capabilities of the SSP controller.
*
* Parameters:
* psspcfg : Pointer to an SSP_CONFIG_T structure
* psspdrvdat: Pointer to driver data
*
* Outputs: None
*
* Returns:
* _ERROR if the configuration setup failed, otherwise _NO_ERROR
*
* Notes: None
*
**********************************************************************/
static STATUS ssp_configure(SSP_CONFIG_T *psspcfg,
SSP_DRVDAT_T *psspdrvdat)
{
UNS_32 tmp0, tmp1;
STATUS setup = _NO_ERROR;
SSP_REGS_T *psspregs = psspdrvdat->regptr;
/* Setup CR0 word first */
tmp0 = 0;
if ((psspcfg->databits >= 4) && (psspcfg->databits <= 16))
{
tmp0 = SSP_CR0_DSS(psspcfg->databits);
}
else
{
setup = _ERROR;
}
if (psspcfg->databits <= 8)
{
psspdrvdat->dsize = 1;
}
else
{
psspdrvdat->dsize = 2;
}
/* Mode */
if (((psspcfg->mode & ~SSP_CR0_PRT_MSK) != 0) ||
(psspcfg->mode == (0x3 << 4)))
{
setup = _ERROR;
}
tmp0 |= psspcfg->mode;
/* SPI clock control */
if (psspcfg->highclk_spi_frames == TRUE)
{
tmp0 |= SSP_CR0_CPOL(1);
}
if (psspcfg->usesecond_clk_spi == TRUE)
{
tmp0 |= SSP_CR0_CPHA(1);
}
/* Master/slave mode control */
tmp1 = 0;
if (psspcfg->master_mode == FALSE)
{
tmp1 = SSP_CR1_MS;
}
/* Setup clock */
if (setup == _NO_ERROR)
{
psspregs->cr0 = tmp0;
psspregs->cr1 = tmp1;
setup = ssp_set_clock(psspdrvdat, psspcfg->ssp_clk);
}
return setup;
}
