/* Lock to be held by caller */ static void skl_ipc_tx_msg(struct sst_generic_ipc *ipc, struct ipc_message *msg) { struct skl_ipc_header *header = (struct skl_ipc_header *)(&msg->header); if (msg->tx_size) sst_dsp_outbox_write(ipc->dsp, msg->tx_data, msg->tx_size); sst_dsp_shim_write_unlocked(ipc->dsp, SKL_ADSP_REG_HIPCIE, header->extension); sst_dsp_shim_write_unlocked(ipc->dsp, SKL_ADSP_REG_HIPCI, header->primary | SKL_ADSP_REG_HIPCI_BUSY); }
static int skl_dsp_start_core(struct sst_dsp *ctx) { int ret; /* unset reset state */ ret = skl_dsp_core_unset_reset_state(ctx); if (ret < 0) { dev_dbg(ctx->dev, "dsp unset reset fails\n"); return ret; } /* run core */ dev_dbg(ctx->dev, "run core...\n"); sst_dsp_shim_write_unlocked(ctx, SKL_ADSP_REG_ADSPCS, sst_dsp_shim_read_unlocked(ctx, SKL_ADSP_REG_ADSPCS) & ~SKL_ADSPCS_CSTALL(SKL_DSP_CORES_MASK)); if (!is_skl_dsp_core_enable(ctx)) { skl_dsp_reset_core(ctx); dev_err(ctx->dev, "DSP core enable failed\n"); ret = -EIO; } return ret; }
static void skl_cldma_cleanup_spb(struct sst_dsp *ctx) { sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_CL_SPBFIFO_SPBFCCTL, CL_SPBFIFO_SPBFCCTL_SPIBE_MASK, CL_SPBFIFO_SPBFCCTL_SPIBE(0)); sst_dsp_shim_write_unlocked(ctx, SKL_ADSP_REG_CL_SPBFIFO_SPIB, 0); }
static int skl_dsp_reset_core(struct sst_dsp *ctx) { /* stall core */ sst_dsp_shim_write_unlocked(ctx, SKL_ADSP_REG_ADSPCS, sst_dsp_shim_read_unlocked(ctx, SKL_ADSP_REG_ADSPCS) & SKL_ADSPCS_CSTALL(SKL_DSP_CORES_MASK)); /* set reset state */ return skl_dsp_core_set_reset_state(ctx); }
static void skl_cldma_setup_spb(struct sst_dsp *ctx, unsigned int size, bool enable) { if (enable) sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_CL_SPBFIFO_SPBFCCTL, CL_SPBFIFO_SPBFCCTL_SPIBE_MASK, CL_SPBFIFO_SPBFCCTL_SPIBE(1)); sst_dsp_shim_write_unlocked(ctx, SKL_ADSP_REG_CL_SPBFIFO_SPIB, size); }