/* only port0 of U2/U3 supports device mode */
static int mtu3_device_enable(struct mtu3 *mtu)
{
void __iomem *ibase = mtu->ippc_base;
u32 check_clk = 0;
mtu3_clrbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
if (mtu->is_u3_ip) {
check_clk = SSUSB_U3_MAC_RST_B_STS;
mtu3_clrbits(ibase, SSUSB_U3_CTRL(0),
(SSUSB_U3_PORT_DIS | SSUSB_U3_PORT_PDN |
SSUSB_U3_PORT_HOST_SEL));
}
mtu3_clrbits(ibase, SSUSB_U2_CTRL(0),
(SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN |
SSUSB_U2_PORT_HOST_SEL));
if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG) {
mtu3_setbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL);
if (mtu->is_u3_ip)
mtu3_setbits(ibase, SSUSB_U3_CTRL(0),
SSUSB_U3_PORT_DUAL_MODE);
}
return ssusb_check_clocks(mtu->ssusb, check_clk);
}
static void switch_port_to_device(struct ssusb_mtk *ssusb)
{
u32 check_clk = 0;
dev_dbg(ssusb->dev, "%s\n", __func__);
ssusb_port0_switch(ssusb, USB2_PORT, false);
if (ssusb->otg_switch.is_u3_drd) {
ssusb_port0_switch(ssusb, USB3_PORT, false);
check_clk = SSUSB_U3_MAC_RST_B_STS;
}
ssusb_check_clocks(ssusb, check_clk);
}
static void switch_port_to_host(struct ssusb_mtk *ssusb)
{
u32 check_clk = 0;
dev_dbg(ssusb->dev, "%s\n", __func__);
ssusb_port0_switch(ssusb, USB2_PORT, true);
if (ssusb->otg_switch.is_u3_drd) {
ssusb_port0_switch(ssusb, USB3_PORT, true);
check_clk = SSUSB_U3_MAC_RST_B_STS;
}
ssusb_check_clocks(ssusb, check_clk);
/* after all clocks are stable */
toggle_opstate(ssusb);
}
