コード例 #1
0
ファイル: twi_read_write.c プロジェクト: bsmr-misc-forks/kroc
void ezTWI_MasterMode_Read(unsigned short DeviceAddr, unsigned char *TWI_SensorDataREAD, unsigned short TX_Count, unsigned short TWI_TX_Length)
{
    #define PRESCALE120M    12        // factor = 12, 120MHz/10MHz 
        *pTWI_FIFO_CTL             |= RCVFLUSH;                // Clear the TX FIFO
        *pTWI_MASTER_STAT         = BUFWRERR | BUFRDERR | DNAK | ANAK | LOSTARB; // Clear all status error
        ssync();

        *pTWI_FIFO_CTL             = 0;                        // Clear the bit manually
        *pTWI_CONTROL            = TWI_ENA | PRESCALE120M;    // PRESCALE = fsclk/10MHz
        *pTWI_CLKDIV            = CLKLOW(50) | CLKHI(50);    // For 100KHz SCL speed: CLKDIV = (1/100KHz)/(1/10MHz) = 100 -> SCL symetric: CLKHI = 50, CLKLOW = 50 
        *pTWI_MASTER_ADDR        = DeviceAddr;                // Target address (7-bits plus the read/write bit the TWI controls
    
    for (i = 0; i < TX_Count; i++)
    {

        *pTWI_MASTER_CTL        = (TWI_TX_Length<<6) | MEN | MDIR;                        // Start transmission 

        for (j = 0; j < (TWI_TX_Length-1); j++)
        {            
        while (*pTWI_FIFO_STAT == 0)                        // wait to load the next sample into the TX FIFO
            ssync();
            TWI_SensorDataREAD[j] = *pTWI_RCV_DATA8;        // Load the next sample into the TX FIFO. Pointer to an array where a list of data is located
            ssync();
        }
    
    
        while ((*pTWI_INT_STAT & MCOMP) == 0)                // Wait until transmission complete and MCOMP is set 
        ssync();
        
        *pTWI_INT_STAT = RCVSTAT | MCOMP;                    // service TWI for next transmission
    }
}
コード例 #2
0
void enableSPORT0DMATDMStreams(void)
{
	*pSPORT0_MCMC1 = 0x1000;
	*pSPORT0_MCMC2 = MFD_1 | MCMEN | MCDRXPE | MCDTXPE;
	*pSPORT0_MRCS0 = 0x00FF;
	*pSPORT0_MTCS0 = 0x00FF;

	/* Enable DMA0 for SPORT0 RX autobuffer transfers */
	*pDMA0_CONFIG	= (*pDMA0_CONFIG | 0x0001);

	/* Enable DMA1 for SPORT0 TX autobuffer transfers */
	*pDMA1_CONFIG	= (*pDMA1_CONFIG | 0x0001);

	/* Set SPORT0 TX (DMA1) interrupt priority to 2 = IVG9 */
	*pSIC_IAR1 = 0x33322221;

	/* Remap the vector table pointer from the default __I9HANDLER
	   to the new "Sport0_TX_ISR()" interrupt service routine */
	// SPORT0 TX ISR -> IVG 9
	*pEVT9 =  (void *)sport0TXISRDummy;		// SPORT0 TX ISR -> IVG 9

	/* Unmask peripheral SPORT0 RX interrupt in System Interrupt Mask Register `
	   (SIC_IMASK bit 9 - DMA1/SPORT0 RX */
	*pIMASK |= EVT_IVG9;
	*pSIC_IMASK0	= (*pSIC_IMASK0 | IRQ_DMA1);
	ssync();

	/* Enable TSPEN bit 0 to start SPORT0 TDM Mode Transmitter */
	*pSPORT0_TCR1 	= (*pSPORT0_TCR1 | TSPEN);
	ssync();

	/* Enable RSPEN bit 0 to start SPORT0 TDM Mode Receiver */
	*pSPORT0_RCR1 	= (*pSPORT0_RCR1 | RSPEN);
	ssync();
}
コード例 #3
0
ファイル: kzdev_spi.c プロジェクト: koban/Uzume-Aqua548
/**
 *	@fn			static BOOL get_rx( )
 *	@brief		get from rx buffer
 */
L1CODE
static BOOL get_rx(void)
{
	if( mpCurConfig->mnDeviceBit == KZDEV_SPI_8BIT )
	{
		/* Get 8bit */
		if ( mnRxCount > 0) 
		{
			UH reg = *pSPI0_RDBR;
			ssync();
			
			*mpbyRxBuf = (UB) reg & 0xFF;
			++mpbyRxBuf;
			--mnRxCount;
			return TRUE;
		}
	}
	else
	{
		/* Get 16bit */
		if ( mnRxCount > 0) 
		{	
			UH reg = *pSPI0_RDBR;
			ssync();
			
			*((UH *) mpbyRxBuf) = reg;
			mpbyRxBuf+=2;
			--mnRxCount;
			return TRUE;
		}
	}
	return FALSE;	
	
}
コード例 #4
0
ファイル: uart.c プロジェクト: ANDnXOR/ANDnXOR_DC24_Badge
int uart_putc(char c)
{
    while (0 == (*pUART0_LSR & THRE)) {
        ssync();
    }
    *pUART0_THR = c;
    ssync();
    return c;
}
コード例 #5
0
ファイル: BfRamTest.cpp プロジェクト: ixc-software/lucksi
	Ram() : m_map(1, CRamSize, CPageSize)
	{
		// RAM init
		*pEBIU_SDRRC = 0x03A0;
		ssync();		
		*pEBIU_SDBCTL = 0x13;
		ssync();		
		*pEBIU_SDGCTL = 0x0091998D;
		ssync();			
	}
コード例 #6
0
ファイル: dma1_conf.c プロジェクト: diqiuren/idlab-daq
void EnablePPI1(){
    *pFIO0_FLAG_S = 0x1;	//FIFO WR_EN = 1
    ssync();
    // start transfers
    *pDMA1_1_CONFIG |= DMAEN;
    ssync();
    *pPPI1_CONTROL |= PORT_EN;
    ssync();
    *pTMRS4_ENABLE |= (TIMEN10|TIMEN11);
    ssync();
}
コード例 #7
0
ファイル: Interrupt_InitB.c プロジェクト: diqiuren/idlab-daq
void InitInterrupts_Rx(void)
{ 	
	register_handler(ik_ivg8, PPI0_RxIsr);		// assign ISR to interrupt vector

	*pSICB_IAR1 = Peripheral_IVG(11,8);			// assign interrupt channel 11 (DMA1_0) to IVG8

	*pILAT |= EVT_IVG8;							// clear pending IVG8 interrupts
	ssync();
	*pSICB_IMASK0 |= SIC_MASK(11);
	ssync();

}
コード例 #8
0
ファイル: dma1_conf.c プロジェクト: diqiuren/idlab-daq
void DisablePPI1(){
	*pFIO0_FLAG_C = 0x1;	//FIFO WR_EN = 0
	ssync();
	// stop transfers
    *pTMRS4_DISABLE |= (TIMEN10|TIMEN11);
    ssync();
    *pPPI1_CONTROL &= ~PORT_EN;
    ssync();
    *pDMA1_1_CONFIG &= ~DMAEN;
    ssync();
    buffer_full = false;
    ssync();
}
コード例 #9
0
ファイル: kzdev_spi.c プロジェクト: koban/Uzume-Aqua548
/**
 * @fn			static void spi_start(const SpiDeviceConfigurator_t* config, const void* pTx, int nTx,  void* pRx, int nRx )
 * @brief		Start SPI
 * @param		config a SPI Configuration
 * @param		pTx Tx Buffer pointer
 * @param		nTx number of the send units
 * @param		pRx Rx Buffer pointer
 * @param		nRx number of the receive units
 */
static void spi_start(const SpiDeviceConfigurator_t* config, const void* pTx, int nTx,  void* pRx, int nRx )
{
	volatile UH dummy;
	UH	spi_ctl;
	
	mpCurConfig = config;
	mpbyTxBuf = (UB*) pTx;
	mpbyRxBuf = (UB*) pRx;
	mnTxCount = nTx;
	mnRxCount = nRx;
	
	*pSPI0_BAUD = SYSCLOCK / 2 / config->mdwBPS;

	/* double bufferの空読み */
	dummy = *pSPI0_RDBR;
	dummy = *pSPI0_RDBR;
	
	spi_ctl = ( config->mnDeviceBit == KZDEV_SPI_8BIT )? SPE | MSTR | GM | ( 00 & TIMOD)
			: SPE | MSTR |  0x0100/*16bit*/| GM | ( 00 & TIMOD);
	
	spi_ctl |= ( config->mbCPOL )? CPOL : 0;
	spi_ctl |= ( config->mbCPHA )? CPHA : 0;
			
	*pSPI0_CTL = spi_ctl;
				
	snd();
					
	if( config->mnCS >= 0 )
		*pSPI0_FLG |=  1 <<( config->mnCS );
		
	ssync();
	
	dummy = *pSPI0_RDBR;
}
コード例 #10
0
ファイル: uart.c プロジェクト: ANDnXOR/ANDnXOR_DC24_Badge
int uart_getc(void)
{
    while (0 == (*pUART0_LSR & DR)) {
        ssync();
    }
    return *pUART0_RBR;
}
コード例 #11
0
//---------------------------------------------------------------------------
//#pragma noreturn
void main()
{                 
    //----------------------------------------------------------------------
    //
    //    Set Pcocessor Core clock to 200 MHz, peripheral clock - to 100 MHz
    //    Set Processor Core voltage at 0.85 v
    //
    pll_set_system_vco(8, 0, 0x300);
    pll_set_system_clocks(0, 2);
    ssync();
    
    /////////////////////////////////////////////////////////////////////
    //
    //    System resources setup
    // 
    //-------------------------------------------------------------------
    //
    //  System Timer setup and start
    //
    MMR32(TCNTL)   = 1;                 // turn on the timer
    MMR32(TSCALE)  = 0;                 //
    MMR32(TPERIOD) = SYS_TIMER_PERIOD;  // 5ns * 200 000 = 1 ms
    MMR32(TCNTL)   = 0x07;              // run timer 
    //-------------------------------------------------------------------
    //
    //    Register System Interrupt Handlers
    //
    //
    register_handler_ex(ik_timer, OS::system_timer_isr, 1);
    register_handler_ex(ik_ivg14, context_switcher_isr, 1);
    //-------------------------------------------------------------------
    /////////////////////////////////////////////////////////////////////


    MMR16(FIO_DIR) |= (1 << 8) + (1 << 9);

    register_handler_ex(ik_ivg11, timer0_isr, 1);
    MMR32(SIC_IMASK) = (1ul << 16)  // Timer0
                     | (1ul << 14)  // UART Rx
                     | (1ul << 15)  // UART Tx
                     ;


    
    MMR16(TIMER0_CONFIG) = PWM_OUT  
                         + IRQ_ENA 
                         + PERIOD_CNT 
                         + OUT_DIS; 

    MMR32(TIMER0_PERIOD) = 10011;
    MMR32(TIMER0_WIDTH)  = 5000;
    MMR16(TIMER_ENABLE)  = TIMEN0;                 // timer0 enable

    UART::init();

    OS::run();
}
コード例 #12
0
ファイル: dma1_conf.c プロジェクト: diqiuren/idlab-daq
void InitPPI1(tDMA_descriptor* First_Header)
{
	// configure Timer10 for PPI SIZE_QEV sync - not enabled yet
	*pTMRS4_DISABLE = TIMDIS10;						//disable Timer
	*pTMRS4_STATUS = (TIMIL10 | TOVL_ERR10 | TRUN10);	// clear status

	*pTIMER10_PERIOD = TWICE_NUM_WORD_PACKET;
	*pTIMER10_WIDTH = 0x1;		// some small dutycycle
	*pTIMER10_CONFIG   = TIN_SEL | PWM_OUT | PULSE_HI | PERIOD_CNT | CLK_SEL | EMU_RUN;	
	ssync();
	
	*pTMRS4_DISABLE = TIMDIS11;						//disable Timer
	*pTMRS4_STATUS = (TIMIL11 | TOVL_ERR11 | TRUN11);	// clear status

	*pTIMER11_PERIOD = (SIZE_QEV) * sizeof(short);
	*pTIMER11_WIDTH = SIZE_QEV;		// entire data
	*pTIMER11_CONFIG   = TIN_SEL | PWM_OUT | PULSE_HI | PERIOD_CNT | CLK_SEL | EMU_RUN;	
	ssync();
	
	// configure PPI1 - not enabled yet
	
//                   POLS      | POLC      | DLEN[2:0] | SKIP_EO   | SKIP_EN  | DMA32    | PACK_EN  | FLD_SEL  | PORT_CFG[1:0] | XFR_TYPE[1:0] | PORT_DIR | PORT_EN
//	*pPPI1_CONTROL = (0x0<<15) | (0x0<<14) | (0x7<<11) | (0x0<<10) | (0x0<<9) | (0x1<<8) | (0x1<<7) | (0x0<<6) | (0x2<<4)      | (0x0<<2)      | (0x1<<1) | (0x0<<0);
	*pPPI1_CONTROL = PPI1_CONF;//0x18E;
	
	*pPPI1_COUNT = TWICE_NUM_WORD_PACKET;
	ssync();

	// configure DMA for PPI1 - not enabled yet
	*pDMA1_1_X_COUNT = TWICE_NUM_WORD_PACKET * sizeof(short)/length;
	*pDMA1_1_Y_COUNT = NUM_PACKET_QEV;
	*pDMA1_1_X_MODIFY = length;		
	*pDMA1_1_Y_MODIFY = length;
	*pDMA1_1_NEXT_DESC_PTR = First_Header;
	
//                     FLOW     |  NDSIZE    |  DI_EN   |  DI_SEL  |  RESTART |   DMA2D  |  WDSIZE   |  WNR     |  DMAEN	
//	*pDMA1_1_CONFIG = (0x7<<12) | (0x5<<8)   | (0x0<<7) | (0x1<<6) | (0x1<<5) | (0x0<<4) | (0x2<<2)  | (0x0<<1) | (0x0<<0);
	*pDMA1_1_CONFIG = DMA1_CONF;//0x7498;
	
	ssync();
	
}
コード例 #13
0
ファイル: kzdev_spi.c プロジェクト: koban/Uzume-Aqua548
/**
 * @fn		static BOOL snd(void)
 * @brief	Send
 * @return	TRUE  ... Send Ok
 * @return	FALSE ... No send data
 */
L1CODE
static BOOL snd(void)
{
	if( mpCurConfig->mnDeviceBit == KZDEV_SPI_8BIT )
	{
		/* Send 8bit */
		if( mnTxCount > 0 )
		{
			UH reg;
			reg = (UH) *(mpbyTxBuf) & 0xFF;
			++mpbyTxBuf;
			--mnTxCount;
			
			*pSPI0_TDBR = reg;
			ssync();
			return TRUE;
		}
		
		/* No data, send 0xFF */
		*pSPI0_TDBR = 0xFF;
	}
	else
	{
		/* Send 16bit */
		if( mnTxCount > 0 )
		{
			UH reg;
			reg= *((UH*)mpbyTxBuf);
			mpbyTxBuf+=2;
			--mnTxCount;
			
			*pSPI0_TDBR = reg;
			ssync();
			return TRUE;
		}
		
		/* No data, send 0xFFFF */
		*pSPI0_TDBR = 0xFFFF;
	}
	return FALSE;
	
}
コード例 #14
0
ファイル: NOR_FLASH.c プロジェクト: webom2008/bf512.project
ERROR_CODE SetToAsyncMode(void)
{
    *pEBIU_AMGCTL = 0x0000;                 /* disable the Async Memory */
    /* Set the mode to async Mode (0-async mode, 1-flash mode, 2-page mode, 3-burst mode) */
    *pEBIU_MODE   = ( B0MODE_ASYNC | B1MODE_ASYNC | B2MODE_ASYNC | B3MODE_ASYNC );
    *pEBIU_FCTL   = ( BCLK );
    *pEBIU_AMGCTL = ( AMCKEN | AMBEN );     /* enable the Async Memory */
    ssync();

    return NO_ERR;
}
コード例 #15
0
ファイル: ad7708.c プロジェクト: hericz/atinom_banyu
void init_spi_ad7708(void)	
{
	unsigned int sclk;
	unsigned short baute;
	
	*pSPI_CTL = (MSTR + CPHA + CPOL + 0x01);
	ssync();
   sclk = get_sclk();  
   //baute = (unsigned short) (sclk / (2 * 5000000));		// 5 MHz
   baute = (unsigned short) (sclk / (2 * 20000000));		
   
   printku("\n\r baut %d ", baute);
   
   *pSPI_BAUD = baute;
   ssync();
   *pSPI_FLG = 0xFF00;
   ssync();
   *pSPI_CTL = (SPE + MSTR + CPHA + CPOL + 0x01); 	//start saat read tdbr
   ssync();
}
コード例 #16
0
ファイル: swan.cpp プロジェクト: zhanghonghe/GeneralUtility
void test(int n) {

    LOG_start = LOG_getTimeStart();
    
    for (int i = 0; i < n; ++i)
        spawn( mytask, 0 );

    LOG_mid = LOG_getTimeStop();

    ssync();

    LOG_stop = LOG_getTimeStop();
}
コード例 #17
0
ファイル: mdma_lan91c111.c プロジェクト: webom2008/BF512.VDK
/******************************************************************************
 * Trasfer  num_bytes from source address to the destination address
 *
 *****************************************************************************/
void dma_initiate_transfer(unsigned long src_addr, unsigned long des_addr,
						   unsigned long num_bytes,DMA_DIRECTION dir)
{
	unsigned short 	dma_config_source;
	unsigned short 	dma_config_destination;
	unsigned short 	d0_x_modify, s0_x_modify;

	ENTER_CRITICAL_REGION();

	if(dir == DMA_DIR_TX) {
		d0_x_modify = 0; // auto increment, same port.
		s0_x_modify = DMA_WORD_SIZE;
	} else {	
		d0_x_modify = DMA_WORD_SIZE;
		s0_x_modify = 0; // auto inrement, same port.
	}

	// configure the source address register
	SET_VAL_ADDR((dev->SrcStreamBaseAddr+OFFSET_START_ADDR),src_addr);
	// configure number of bytes to send at the source end
	SET_VAL_SHORT((dev->SrcStreamBaseAddr+OFFSET_X_COUNT),(unsigned short)num_bytes);
	// configure modify at the source end
	SET_VAL_SHORT((dev->SrcStreamBaseAddr+OFFSET_X_MODIFY),(unsigned short)s0_x_modify);

	// configure destination address register
	//*pMDMA_D0_START_ADDR =	(volatile void*)des_addr;
	// configure the source address register
	SET_VAL_ADDR((dev->DstStreamBaseAddr+OFFSET_START_ADDR),des_addr);

	//configure destination x_count register
	SET_VAL_SHORT((dev->DstStreamBaseAddr+OFFSET_X_COUNT),(unsigned short)num_bytes);
	// configure destiantion x_modify register
	SET_VAL_SHORT((dev->DstStreamBaseAddr+OFFSET_X_MODIFY),(unsigned short)d0_x_modify);

	// Configure source DMA config register, enable bit set, and transfer
	// size if 16 bits.
	//
	dma_config_source = (WDSIZE_16 | DMAEN);
	SET_VAL_SHORT((dev->SrcStreamBaseAddr+OFFSET_CONFIG),(unsigned short)dma_config_source);

	// Configure destination config register, enable DMA, transfer size 16
	// bits and enable DMA completion interrupt
	//
	dma_config_destination = (DI_EN | WDSIZE_16 | DMAEN | WNR); 
	// DMA transfer starts here.
	SET_VAL_SHORT((dev->DstStreamBaseAddr+OFFSET_CONFIG),(unsigned short)dma_config_destination);
	ssync();
	
	EXIT_CRTICIAL_REGION();

}
コード例 #18
0
ファイル: dsp.c プロジェクト: heathjohns/iroh
void initDSP() {
	// Clock
	// 158.0544MHz
	int ssel = 8;
	int csel = 0;
	ADI_SYSCTRL_VALUES pll;
	pll.uwPllCtl = SET_MSEL(14);
	pll.uwPllDiv = ssel + (csel << 4);
	pll.uwVrCtl = 0x7000;
	bfrom_SysControl(SYSCTRL_WRITE | SYSCTRL_PLLCTL | SYSCTRL_PLLDIV, &pll, NULL);
	while ((*pPLL_STAT & PLL_LOCKED) == 0);

	// GPIO G
	*pPORTG_FER = 0;
	*pPORTGIO_DIR = CODEC_RESET | CODEC_CS;
	*pPORTGIO_SET = CODEC_CS;
	*pPORTGIO_CLEAR = CODEC_RESET;

	// GPIO F
	*pPORTF_FER = 0;
	*pPORTFIO_DIR = TEST_PIN;
	*pPORTFIO_SET = TEST_PIN;

	// I2C
	*pTWI_CLKDIV = CLKLOW(I2C_CLK_LOHI) | CLKHI(I2C_CLK_LOHI);
	ssync();
	*pTWI_CONTROL = TWI_ENA | 10;

	// I2S
	*pPORTG_FER |= PG1 | PG5 | PG6 | PG7;

	// SPI
	*pPORTF_FER |= PF15 | PF14 | PF13;
	*pSPI0_FLG = 0b00000000000010;
	*pSPI0_BAUD = SPI_BAUD;
	ssync();
	*pSPI0_CTL = 0b0101000000001101;
}
コード例 #19
0
ファイル: mainB.c プロジェクト: diqiuren/idlab-daq
int main( void )
{
	int j;

//----------Set up descriptors
	tDMA_descriptor DMA_PPI0[2];
	DMA_PPI0[0].NDPL = ((unsigned long int)&DMA_PPI0[1]) & 0xffff;
	DMA_PPI0[0].NDPH = (((unsigned long int)&DMA_PPI0[1]) & 0xffff0000)>>16;
	DMA_PPI0[0].SAL = ((unsigned long int)buffer16) & 0xffff;
	DMA_PPI0[0].SAH = (((unsigned long int)buffer16) & 0xffff0000)>>16;
	DMA_PPI0[0].DMACFG = DMA0_CONF|0x1;
	DMA_PPI0[1].NDPL = ((unsigned long int)&DMA_PPI0[1]) & 0xffff;
	DMA_PPI0[1].NDPH = (((unsigned long int)&DMA_PPI0[1]) & 0xffff0000)>>16;
	DMA_PPI0[1].SAL = ((unsigned long int)&term) & 0xffff;
	DMA_PPI0[1].SAH = (((unsigned long int)&term) & 0xffff0000)>>16;
	DMA_PPI0[1].DMACFG = (DMA0_CONF|0x1)&0x00FF;	
//-----------------------------
	
	printf("Entered CoreB\n");
//	printf("B32_addr: 0x%x, B16_addr: 0x%x\n",&buffer32,&buffer16);
	
	buffer_full = false;
	InitInterrupts_Rx();
	
	clear_buffers();

	InitPPI0(&DMA_PPI0[0]);
	ssync();
	EnablePPI0();
	ssync();
	
	while(*pDMA1_0_IRQ_STATUS & DMA_RUN);
	DisablePPI0();
	ssync();


	return 0;
}
コード例 #20
0
ファイル: mdma_lan91c111.c プロジェクト: webom2008/BF512.VDK
/******************************************************************************
 * Mask or Unmask DMA interrupt, if the flag is true then masks the DMA int
 * else unmasks the dma interrupt
 * flag = 1 means enables the DMA interrupt in the SIC
 * flag = 0 means disables the  DMA interrupt in the SIC
 *****************************************************************************/
void dma_mask_en(int flag)
{
unsigned int mask;

    mask = *pSIC_IMASK;

    // 1 means enable
    if(flag)
       mask |= 1 << dev->DmaSICMaskBit;
    else
       mask &= ~(0x0L | (1 << dev->DmaSICMaskBit));

    *pSIC_IMASK = mask;
    ssync();
}
コード例 #21
0
ファイル: NOR_FLASH.c プロジェクト: webom2008/bf512.project
ERROR_CODE SetToPageMode(void)
{
    SetupForFlash();
    GetCodes();

    *pEBIU_AMGCTL = 0x0000;                 /* disable the Async Memory */
    /* Set the mode to async Mode (0-async mode, 1-flash mode, 2-page mode, 3-burst mode) */
    *pEBIU_MODE   = ( B0MODE_PAGE | B1MODE_PAGE | B2MODE_PAGE | B3MODE_PAGE );
    *pEBIU_FCTL   = ( PGWS | BCLK );
    *pEBIU_AMGCTL = ( AMCKEN | AMBEN );     /* enable the Async Memory */
    ssync();

    SetRCR ( uwRCR_Default );
    ResetFlash();

    return NO_ERR;
}
コード例 #22
0
//--------------------------------------------------------------------------//
// Function:	Init_Interrupts												//
//																			//
// Description:	Initialize Interrupt						//
//--------------------------------------------------------------------------//
void Init_Interrupts(void)
{
	// Set Sport0 RX (DMA1) interrupt priority to 2 = IVG9 
	*pSIC_IAR0 = 0xffffffff;
	*pSIC_IAR1 = 0xffffff2f;
	*pSIC_IAR2 = 0xffff5fff;				// FlagA -> ID5

	// assign ISRs to interrupt vectors
	// Sport0 RX ISR -> IVG 9
	// FlagA ISR -> IVG 12	
	register_handler(ik_ivg9, Sport0_RX_ISR);	
	register_handler(ik_ivg12, FlagA_ISR);	

	// enable Sport0 RX interrupt and FlagA 
	*pSIC_IMASK = 0x00080200;
	ssync();
}
コード例 #23
0
ファイル: NOR_FLASH.c プロジェクト: webom2008/bf512.project
ERROR_CODE SetToBurstMode(void)
{
    u16 uwRCRtmp;

    SetupForFlash();
    GetCodes();

    *pEBIU_AMGCTL = 0x0000;                 /* disable the Async Memory */
    /* Set the mode to async Mode (0-async mode, 1-flash mode, 2-page mode, 3-burst mode) */
    *pEBIU_MODE   = ( B0MODE_BURST | B1MODE_BURST | B2MODE_BURST | B3MODE_BURST );
    *pEBIU_FCTL   = ( BCLK );
    *pEBIU_AMGCTL = ( AMCKEN | AMBEN );     /* enable the Async Memory */
    ssync();

    uwRCRtmp = uwRCR_Default & 0x05F0;
    uwRCRtmp |= 0x0003;
    uwRCRtmp |= 3 << 11;
    SetRCR ( uwRCRtmp );
    ResetFlash();

    return NO_ERR;
}
コード例 #24
0
ファイル: kzdev_spi.c プロジェクト: koban/Uzume-Aqua548
/**
 *	@fn			static BOOL rcv_snd(void)
 *	@brief		Receive a data and send a data
 */
L1CODE
static BOOL rcv_snd(void)
{
	if ( mnTxCount <= 0 && mnRxCount <= 1 )
	{
		/* transfer end */
		/* CS disable */
		if( mpCurConfig->mnCS >= 0 )
			*pSPI0_FLG &= ~( 1 << ( mpCurConfig->mnCS  ) );

		/* SPI disable */
		*pSPI0_CTL = 0;
		ssync();
		
		/* Get rest of one rx message, if there is. */
		get_rx();

		/* Complete! */
		mpCurConfig = 0;
		
		return FALSE;
	} 
	else
	{
		/* transfer continue */
		/* Send tx */
		snd();

		if (!get_rx() )
		{
			/* get dummy data for trigger */
			volatile UH dummy = *pSPI0_RDBR;
		}
		return TRUE;
	}
}
コード例 #25
0
ファイル: mainA.c プロジェクト: diqiuren/idlab-daq
int main(void)
{
	int j;
	int chk_sum = 0;
	int temp = 0;
	unsigned int *test_buffer[2];

	*pFIO0_DIR = 0x0007; //Initialize PF[0], PF[1], PF[2] as output
	ssync();
	adi_core_b_enable(); //Call on Core B to sit idle
	ssync();

//----------Set up descriptors
	tDMA_descriptor DMA_PPI1[2];
	DMA_PPI1[0].NDPL = ((unsigned long int)&DMA_PPI1[1]) & 0xffff;
	DMA_PPI1[0].NDPH = (((unsigned long int)&DMA_PPI1[1]) & 0xffff0000)>>16;
	DMA_PPI1[0].SAL = ((unsigned long int)buffer16) & 0xffff;
	DMA_PPI1[0].SAH = (((unsigned long int)buffer16) & 0xffff0000)>>16;
	DMA_PPI1[0].DMACFG = DMA1_CONF|0x1;
	DMA_PPI1[1].NDPL = ((unsigned long int)&DMA_PPI1[1]) & 0xffff;
	DMA_PPI1[1].NDPH = (((unsigned long int)&DMA_PPI1[1]) & 0xffff0000)>>16;
	DMA_PPI1[1].SAL = ((unsigned long int)&term) & 0xffff;
	DMA_PPI1[1].SAH = (((unsigned long int)&term) & 0xffff0000)>>16;
	DMA_PPI1[1].DMACFG = (DMA1_CONF|0x1)&0x00FF;
//-----------------------------

/*
	1. Configure DMA registers as appropriate for desired DMA operating mode.
	2. Enable the DMA channel for operation.
	3. Configure appropriate PPI registers.
	4. Enable the PPI by writing a 1 to bit 0 in PPIx_CONTROL.
*/

	InitInterrupts_Tx();

	InitPPI1(&DMA_PPI1[0]);
	ssync();
	
//	printf("B0_addr: 0x%x, B1_addr: 0x%x, B2_addr: 0x%x, B3_addr: 0x%x\n",&buffer0,&buffer1,&buffer2,&buffer3);
//	printf("PPI1_CONTROL: 0x%x, DMA1_1_CONFIG: 0x%x, DMA1_1_IRQ: 0x%x\n",*pPPI1_CONTROL, *pDMA1_1_CONFIG,*pDMA1_1_IRQ_STATUS);

	*pFIO0_FLAG_S = 0x4;	//Assert FIFO Reset
	for(j=0; j<10;j++);
	ssync();
	*pFIO0_FLAG_C = 0x4;	//Deassert FIFO Reset
	ssync();

	while(!buffer_full);
	EnablePPI1();
	ssync();

	while(*pDMA1_1_IRQ_STATUS & DMA_RUN);
	DisablePPI1();
	ssync();

	printf("PPI1 Disabled\n");

	for(j=0;j<SIZE_QEV/2;j++){
		chk_sum = chk_sum + buffer32[j];
	}

	printf("Chk_Sum: 0x%x\n",chk_sum);
/*	
	test_buffer[0] = (unsigned int)&buffer32[NUM_PACKET_QEV];
	test_buffer[1] = (unsigned int)&buffer32[TWICE_NUM_WORD_PACKET];
	printf("test: 0x%x\n",test_buffer[1][0]);
*/	
	return 0;
}
コード例 #26
0
ファイル: ad7708.c プロジェクト: hericz/atinom_banyu
inline void cs_ad7708(void)
{
	*pFIO_FLAG_C = port_cs_ad7708;
	ssync();
}
コード例 #27
0
ファイル: mainA.c プロジェクト: diqiuren/idlab-daq
int main(void)
{
	int j,i;
	int chk_sum = 0;
	unsigned int *test_buffer[2];

	*pFIO0_DIR = 0x0007; //Initialize PF[0], PF[1], PF[2] as output
	ssync();
	adi_core_b_enable(); //Call on Core B
	ssync();

//----------Set up descriptors

	tDMA_descriptor DMA_PPI1[1];
/*	
	DMA_PPI1[0].NDPL = ((unsigned long int)&DMA_PPI1[0]) & 0xffff;
	DMA_PPI1[0].NDPH = (((unsigned long int)&DMA_PPI1[0]) & 0xffff0000)>>16;
	DMA_PPI1[0].SAL = ((unsigned long int)buffer16[0]) & 0xffff;
	DMA_PPI1[0].SAH = (((unsigned long int)buffer16[0]) & 0xffff0000)>>16;
	DMA_PPI1[0].DMACFG = (DMA1_CONF|0x1)&0x00FF;
*/
//-----------------------------

/*
	1. Configure DMA registers as appropriate for desired DMA operating mode.
	2. Enable the DMA channel for operation.
	3. Configure appropriate PPI registers.
	4. Enable the PPI by writing a 1 to bit 0 in PPIx_CONTROL.
*/

	printf("Entered CoreA\n");	
	InitInterrupts_Tx();
	
	while(1){
		chk_sum = 0;

		if(tx_count != rx_count){
			for(j=0;j<TWICE_NUM_WORD_PACKET/2;j++){
				chk_sum = chk_sum + buffer32[tx_count][j];
			}
			chk_sum = chk_sum - buffer32[tx_count][138];
			printf("Chk_Sum: 0x%x\n",chk_sum);
		
			DMA_PPI1[0].NDPL = ((unsigned long int)&DMA_PPI1[0]) & 0xffff;
			DMA_PPI1[0].NDPH = (((unsigned long int)&DMA_PPI1[0]) & 0xffff0000)>>16;
			DMA_PPI1[0].SAL = ((unsigned long int)buffer16[tx_count]) & 0xffff;
			DMA_PPI1[0].SAH = (((unsigned long int)buffer16[tx_count]) & 0xffff0000)>>16;
			DMA_PPI1[0].DMACFG = (DMA1_CONF|0x1)&0x00FF;

			InitPPI1(&DMA_PPI1[0]);
			ssync();
		
			EnablePPI1();
			while(*pDMA1_1_IRQ_STATUS & DMA_RUN);
			DisablePPI1();
		}
		else{		

		}
	
	}
コード例 #28
0
ファイル: ad7708.c プロジェクト: hericz/atinom_banyu
inline void uncs_ad7708(void)
{
	*pFIO_FLAG_S = port_cs_ad7708;
	ssync();
}
コード例 #29
0
ファイル: fuse_serve.c プロジェクト: pombredanne/fstitch
static void serve_fsyncdir(fuse_req_t req, fuse_ino_t fuse_ino, int datasync,
                           struct fuse_file_info * fi)
{
	Dprintf("%s(ino = %lu, datasync = %d)\n", __FUNCTION__, fuse_ino, datasync);
	ssync(req, fuse_ino, datasync, fi);	
}
コード例 #30
0
ファイル: mdma_lan91c111.c プロジェクト: webom2008/BF512.VDK
/******************************************************************************
 * DMA interrupt handler, Upon completion of the DMA operation this will get
 * called.
 *****************************************************************************/
void dma_interrupt_handler(void *arg,unsigned int v, unsigned int g)
{
	short dma_status=0x0;
	ADI_DCB_RESULT result;
	static int recall_count=0;


	// NO DMA in action. May be spurious interrupt.
	if(dev->m_dma_protect == 0)
	{
		num_dma_protect_zeros++;
		return;
	}

	ENTER_CRITICAL_REGION();

	// set destination config register
	SET_VAL_SHORT((dev->DstStreamBaseAddr+OFFSET_CONFIG),(unsigned short)0x0);
	// set source config register
	SET_VAL_SHORT((dev->SrcStreamBaseAddr+OFFSET_CONFIG),(unsigned short)0x0);
	// get dma status register
	GET_VAL_SHORT((dev->DstStreamBaseAddr+OFFSET_IRQ_STATUS),dma_status);

	// check for the dma complete.
	//
	if(dma_status & DMA_DONE)
	{
		dma_status |= DMA_DONE;
		// acknowledge DMA  completion
		SET_VAL_SHORT((dev->DstStreamBaseAddr+OFFSET_IRQ_STATUS),dma_status);
	}
	// DMA error
	else if (dma_status & DMA_ERR)
	{
		dev->MemDmaErrorCount++;
		dma_status |= DMA_DONE;
		// we will release the DMA
		dma_relinquish();
		// acknowledge dma error
		SET_VAL_SHORT((dev->DstStreamBaseAddr+OFFSET_IRQ_STATUS),dma_status);
		// enable SMSC interrupts
		LAN91C111_enable_int(SMC_INTERRUPT_MASK);
	}
	ssync();

	switch(dev->m_dma_direction)
	{
		//
		// Transmit Complete
		//
		case DMA_DIR_TX:
				transmit_complete();
				EXIT_CRTICIAL_REGION();

        if (dev->DCBHandle != NULL){
                      result = adi_dcb_Post(dev->DCBHandle,
                                            0,
                                            dev->DMCallback, 
                                            dev->DeviceHandle,
                                            ADI_ETHER_EVENT_FRAME_XMIT,
                                            dev->m_TxDequeuedHead->CallbackParameter);
     		}
                else{
                          (dev->DMCallback)(dev->DeviceHandle, 
                                            ADI_ETHER_EVENT_FRAME_XMIT,
                                            dev->m_TxDequeuedHead->CallbackParameter);
			     	result = ADI_DCB_RESULT_SUCCESS;
     		}

               if (result == ADI_DCB_RESULT_SUCCESS) {
		//## what happens if a packet is trasnmitted while in the callback
                    dev->m_TxDequeuedHead = NULL;
                    dev->m_TxDequeuedTail = NULL;
                    dev->m_TxDequeuedCount = 0;
		}
               break;
		//
		// Receive Complete
		//
		case DMA_DIR_RX:
                         receive_complete();
                         dma_relinquish();
                         EXIT_CRTICIAL_REGION();

			if (dev->m_RxDequeuedHead != NULL){
				if (dev->DCBHandle!=NULL) {
                                    result = adi_dcb_Post(dev->DCBHandle,
                                                        0,
                                                        dev->DMCallback,
                                                        dev->DeviceHandle,
                                                        ADI_ETHER_EVENT_FRAME_RCVD, 
							  dev->m_RxDequeuedHead->CallbackParameter); } 
                      else{
                               (dev->DMCallback)(dev->DeviceHandle, 
				  ADI_ETHER_EVENT_FRAME_RCVD, 
				  dev->m_RxDequeuedHead->CallbackParameter); 
                               result = ADI_DCB_RESULT_SUCCESS;
			}
                     if (result == ADI_DCB_RESULT_SUCCESS) {
					//## what happens if a packet is received while in the callback
                         dev->m_RxDequeuedHead = NULL;
                         dev->m_RxDequeuedTail = NULL;
                         dev->m_RxDequeuedCount = 0;  
			}
		}
		break;
		//
		// default
		//
		default:
		     break;
	} // switch end

	// we check if there is any xmted packets to be sent
	// we try on every odd packet.
	//
	if( (recall_count & 0x1) && (dev->m_TxEnqueuedCount > 0)){
		ENTER_CRITICAL_REGION();
		dma_protect(dev,DMA_DIR_TX);
		resend_cnt++;
		if(!SendTxEnqueuedPacket(dev)){
	  	  dma_relinquish();
  		  LAN91C111_enable_int(SMC_INTERRUPT_MASK);
		}
		EXIT_CRTICIAL_REGION();
	}
	else {
		dma_relinquish();
  	LAN91C111_enable_int(SMC_INTERRUPT_MASK);
	}

	recall_count++;
	if(recall_count == UINT_MAX) recall_count =0;
}