int up_prioritize_irq(int irq, int priority) { uint32_t regaddr; uint32_t regval; int shift; DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); if (irq < STM32_IRQ_INTERRUPTS) { irq -= 4; regaddr = NVIC_SYSH_PRIORITY(irq); } else { irq -= STM32_IRQ_INTERRUPTS; regaddr = NVIC_IRQ_PRIORITY(irq); } regval = getreg32(regaddr); shift = ((irq & 3) << 3); regval &= ~(0xff << shift); regval |= (priority << shift); putreg32(regval, regaddr); stm32_dumpnvic("prioritize", irq); return OK; }
int up_prioritize_irq(int irq, int priority) { uint32_t regaddr; uint32_t regval; int shift; DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); if (irq < STM32_IRQ_FIRST) { /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority * registers (0-3 are invalid) */ regaddr = NVIC_SYSH_PRIORITY(irq); irq -= 4; } else { /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ irq -= STM32_IRQ_FIRST; regaddr = NVIC_IRQ_PRIORITY(irq); } regval = getreg32(regaddr); shift = ((irq & 3) << 3); regval &= ~(0xff << shift); regval |= (priority << shift); putreg32(regval, regaddr); stm32_dumpnvic("prioritize", irq); return OK; }
void up_enable_irq(int irq) { uint32_t regaddr; uint32_t regval; uint32_t bit; if (stm32_irqinfo(irq, ®addr, &bit) == 0) { /* Set the appropriate bit in the register to enable the interrupt */ regval = getreg32(regaddr); regval |= bit; putreg32(regval, regaddr); } stm32_dumpnvic("enable", irq); }
int up_prioritize_irq(int irq, int priority) { uint32_t regaddr; uint32_t regval; int shift; #ifdef CONFIG_ARMV7M_USEBASEPRI DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS && priority >= NVIC_SYSH_DISABLE_PRIORITY && priority <= NVIC_SYSH_PRIORITY_MIN); #else DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); #endif if (irq < STM32_IRQ_INTERRUPTS) { /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority * registers (0-3 are invalid) */ regaddr = NVIC_SYSH_PRIORITY(irq); irq -= 4; } else { /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ irq -= STM32_IRQ_INTERRUPTS; regaddr = NVIC_IRQ_PRIORITY(irq); } regval = getreg32(regaddr); shift = ((irq & 3) << 3); regval &= ~(0xff << shift); regval |= (priority << shift); putreg32(regval, regaddr); stm32_dumpnvic("prioritize", irq); return OK; }
void up_enable_irq(int irq) { uintptr_t regaddr; uint32_t regval; uint32_t bit; if (stm32_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) { /* Modify the appropriate bit in the register to enable the interrupt. * For normal interrupts, we need to set the bit in the associated * Interrupt Set Enable register. For other exceptions, we need to * set the bit in the System Handler Control and State Register. */ if (irq >= STM32_IRQ_FIRST) { putreg32(bit, regaddr); } else { regval = getreg32(regaddr); regval |= bit; putreg32(regval, regaddr); } } #ifdef CONFIG_STM32H7_GPIO_IRQ else { /* Maybe it is a (derived) GPIO IRQ */ stm32_gpioirqenable(irq); } #endif #if 0 /* Might be useful in early bring-up */ stm32_dumpnvic("enable", irq); #endif }
void up_irqinitialize(void) { uint32_t regaddr; int num_priority_registers; /* Disable all interrupts */ putreg32(0, NVIC_IRQ0_31_ENABLE); putreg32(0, NVIC_IRQ32_63_ENABLE); /* The standard location for the vector table is at the beginning of FLASH * at address 0x0800:0000. If we are using the STMicro DFU bootloader, then * the vector table will be offset to a different location in FLASH and we * will need to set the NVIC vector location to this alternative location. */ #ifdef CONFIG_STM32_DFU putreg32((uint32_t)stm32_vectors, NVIC_VECTAB); #endif /* Set all interrupts (and exceptions) to the default priority */ putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY); putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY); putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY); /* The NVIC ICTR register (bits 0-4) holds the number of of interrupt * lines that the NVIC supports: * * 0 -> 32 interrupt lines, 8 priority registers * 1 -> 64 " " " ", 16 priority registers * 2 -> 96 " " " ", 32 priority registers * ... */ num_priority_registers = (getreg32(NVIC_ICTR) + 1) * 8; /* Now set all of the interrupt lines to the default priority */ regaddr = NVIC_IRQ0_3_PRIORITY; while (num_priority_registers--) { putreg32(DEFPRIORITY32, regaddr); regaddr += 4; } /* currents_regs is non-NULL only while processing an interrupt */ current_regs = NULL; /* Attach the SVCall and Hard Fault exception handlers. The SVCall * exception is used for performing context switches; The Hard Fault * must also be caught because a SVCall may show up as a Hard Fault * under certain conditions. */ irq_attach(STM32_IRQ_SVCALL, up_svcall); irq_attach(STM32_IRQ_HARDFAULT, up_hardfault); /* Set the priority of the SVCall interrupt */ #ifdef CONFIG_ARCH_IRQPRIO /* up_prioritize_irq(STM32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif #ifdef CONFIG_ARMV7M_USEBASEPRI stm32_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); #endif /* If the MPU is enabled, then attach and enable the Memory Management * Fault handler. */ #ifdef CONFIG_ARMV7M_MPU irq_attach(STM32_IRQ_MEMFAULT, up_memfault); up_enable_irq(STM32_IRQ_MEMFAULT); #endif /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG irq_attach(STM32_IRQ_NMI, stm32_nmi); #ifndef CONFIG_ARMV7M_MPU irq_attach(STM32_IRQ_MEMFAULT, up_memfault); #endif irq_attach(STM32_IRQ_BUSFAULT, stm32_busfault); irq_attach(STM32_IRQ_USAGEFAULT, stm32_usagefault); irq_attach(STM32_IRQ_PENDSV, stm32_pendsv); irq_attach(STM32_IRQ_DBGMONITOR, stm32_dbgmonitor); irq_attach(STM32_IRQ_RESERVED, stm32_reserved); #endif stm32_dumpnvic("initial", NR_IRQS); #ifndef CONFIG_SUPPRESS_INTERRUPTS /* And finally, enable interrupts */ irqenable(); #endif }
void up_irqinitialize(void) { /* Disable all interrupts */ putreg32(0, NVIC_IRQ0_31_ENABLE); putreg32(0, NVIC_IRQ32_63_ENABLE); /* The standard location for the vector table is at the beginning of FLASH * at address 0x0800:0000. If we are using the STMicro DFU bootloader, then * the vector table will be offset to a different location in FLASH and we * will need to set the NVIC vector location to this alternative location. */ #ifdef CONFIG_STM32_DFU putreg32((uint32_t)stm32_vectors, NVIC_VECTAB); #endif /* Set all interrupts (and exceptions) to the default priority */ putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY); putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY); putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY); putreg32(DEFPRIORITY32, NVIC_IRQ0_3_PRIORITY); putreg32(DEFPRIORITY32, NVIC_IRQ4_7_PRIORITY); putreg32(DEFPRIORITY32, NVIC_IRQ8_11_PRIORITY); putreg32(DEFPRIORITY32, NVIC_IRQ12_15_PRIORITY); putreg32(DEFPRIORITY32, NVIC_IRQ16_19_PRIORITY); putreg32(DEFPRIORITY32, NVIC_IRQ20_23_PRIORITY); putreg32(DEFPRIORITY32, NVIC_IRQ24_27_PRIORITY); putreg32(DEFPRIORITY32, NVIC_IRQ28_31_PRIORITY); putreg32(DEFPRIORITY32, NVIC_IRQ32_35_PRIORITY); putreg32(DEFPRIORITY32, NVIC_IRQ36_39_PRIORITY); putreg32(DEFPRIORITY32, NVIC_IRQ40_43_PRIORITY); putreg32(DEFPRIORITY32, NVIC_IRQ44_47_PRIORITY); putreg32(DEFPRIORITY32, NVIC_IRQ48_51_PRIORITY); putreg32(DEFPRIORITY32, NVIC_IRQ52_55_PRIORITY); putreg32(DEFPRIORITY32, NVIC_IRQ56_59_PRIORITY); putreg32(DEFPRIORITY32, NVIC_IRQ60_63_PRIORITY); putreg32(DEFPRIORITY32, NVIC_IRQ64_67_PRIORITY); /* currents_regs is non-NULL only while processing an interrupt */ current_regs = NULL; /* Attach the SVCall and Hard Fault exception handlers. The SVCall * exception is used for performing context switches; The Hard Fault * must also be caught because a SVCall may show up as a Hard Fault * under certain conditions. */ irq_attach(STM32_IRQ_SVCALL, up_svcall); irq_attach(STM32_IRQ_HARDFAULT, up_hardfault); /* Set the priority of the SVCall interrupt */ #ifdef CONFIG_ARCH_IRQPRIO /* up_prioritize_irq(STM32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif /* If the MPU is enabled, then attach and enable the Memory Management * Fault handler. */ #ifdef CONFIG_ARMV7M_MPU irq_attach(STM32_IRQ_MEMFAULT, up_memfault); up_enable_irq(STM32_IRQ_MEMFAULT); #endif /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG irq_attach(STM32_IRQ_NMI, stm32_nmi); #ifndef CONFIG_ARMV7M_MPU irq_attach(STM32_IRQ_MEMFAULT, up_memfault); #endif irq_attach(STM32_IRQ_BUSFAULT, stm32_busfault); irq_attach(STM32_IRQ_USAGEFAULT, stm32_usagefault); irq_attach(STM32_IRQ_PENDSV, stm32_pendsv); irq_attach(STM32_IRQ_DBGMONITOR, stm32_dbgmonitor); irq_attach(STM32_IRQ_RESERVED, stm32_reserved); #endif stm32_dumpnvic("initial", NR_IRQS); #ifndef CONFIG_SUPPRESS_INTERRUPTS /* Initialize FIQs */ #ifdef CONFIG_ARCH_FIQ up_fiqinitialize(); #endif /* And finally, enable interrupts */ setbasepri(NVIC_SYSH_PRIORITY_MAX); irqrestore(0); #endif }
void up_irqinitialize(void) { uintptr_t regaddr; #if defined(CONFIG_DEBUG_SYMBOLS) && !defined(CONFIG_ARMV7M_USEBASEPRI) uint32_t regval; #endif int nintlines; int i; /* The NVIC ICTR register (bits 0-4) holds the number of of interrupt * lines that the NVIC supports, defined in groups of 32. That is, * the total number of interrupt lines is up to (32*(INTLINESNUM+1)). * * 0 -> 32 interrupt lines, 1 enable register, 8 priority registers * 1 -> 64 " " " ", 2 enable registers, 16 priority registers * 2 -> 96 " " " ", 3 enable regsiters, 24 priority registers * ... */ nintlines = (getreg32(NVIC_ICTR) & NVIC_ICTR_INTLINESNUM_MASK) + 1; /* Disable all interrupts. There are nintlines interrupt enable * registers. */ for (i = nintlines, regaddr = NVIC_IRQ0_31_CLEAR; i > 0; i--, regaddr += 4) { putreg32(0xffffffff, regaddr); } /* Make sure that we are using the correct vector table. The default * vector address is 0x0000:0000 but if we are executing code that is * positioned in SRAM or in external FLASH, then we may need to reset * the interrupt vector so that it refers to the table in SRAM or in * external FLASH. */ putreg32((uint32_t)_vectors, NVIC_VECTAB); #ifdef CONFIG_ARCH_RAMVECTORS /* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based * vector table that requires special initialization. */ up_ramvec_initialize(); #endif /* Set all interrupts (and exceptions) to the default priority */ putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY); putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY); putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY); /* Now set all of the interrupt lines to the default priority. There are * nintlines * 8 priority registers. */ for (i = (nintlines << 3), regaddr = NVIC_IRQ0_3_PRIORITY; i > 0; i--, regaddr += 4) { putreg32(DEFPRIORITY32, regaddr); } /* currents_regs is non-NULL only while processing an interrupt */ CURRENT_REGS = NULL; /* Attach the SVCall and Hard Fault exception handlers. The SVCall * exception is used for performing context switches; The Hard Fault * must also be caught because a SVCall may show up as a Hard Fault * under certain conditions. */ irq_attach(STM32_IRQ_SVCALL, up_svcall, NULL); irq_attach(STM32_IRQ_HARDFAULT, up_hardfault, NULL); /* Set the priority of the SVCall interrupt */ #ifdef CONFIG_ARCH_IRQPRIO /* up_prioritize_irq(STM32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif #ifdef CONFIG_ARMV7M_USEBASEPRI stm32_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); #endif /* If the MPU is enabled, then attach and enable the Memory Management * Fault handler. */ #ifdef CONFIG_ARM_MPU irq_attach(STM32_IRQ_MEMFAULT, up_memfault, NULL); up_enable_irq(STM32_IRQ_MEMFAULT); #endif /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG_FEATURES irq_attach(STM32_IRQ_NMI, stm32_nmi, NULL); #ifndef CONFIG_ARM_MPU irq_attach(STM32_IRQ_MEMFAULT, up_memfault, NULL); #endif irq_attach(STM32_IRQ_BUSFAULT, stm32_busfault, NULL); irq_attach(STM32_IRQ_USAGEFAULT, stm32_usagefault, NULL); irq_attach(STM32_IRQ_PENDSV, stm32_pendsv, NULL); irq_attach(STM32_IRQ_DBGMONITOR, stm32_dbgmonitor, NULL); irq_attach(STM32_IRQ_RESERVED, stm32_reserved, NULL); #endif stm32_dumpnvic("initial", STM32_IRQ_NIRQS); /* If a debugger is connected, try to prevent it from catching hardfaults. * If CONFIG_ARMV7M_USEBASEPRI, no hardfaults are expected in normal * operation. */ #if defined(CONFIG_DEBUG_SYMBOLS) && !defined(CONFIG_ARMV7M_USEBASEPRI) regval = getreg32(NVIC_DEMCR); regval &= ~NVIC_DEMCR_VCHARDERR; putreg32(regval, NVIC_DEMCR); #endif #ifndef CONFIG_SUPPRESS_INTERRUPTS /* Initialize logic to support a second level of interrupt decoding for * GPIO pins. */ #ifdef CONFIG_STM32H7_GPIO_IRQ stm32_gpioirqinitialize(); #endif /* And finally, enable interrupts */ up_irq_enable(); #endif }