static int conf_start(void) { /* The application processor (AP) begins by driving the iCE40 CRESET_B pin Low, resetting the iCE40 FPGA. Similarly, the AP holds the iCE40's SPI_SS_B pin Low. The AP must hold the CRESET_B pin Low for at least 200 ns. Ultimately, the AP either releases the CRESET_B pin and allows it to float High via the 10 KOhm pull-up resistor to VCCIO_2 or drives CRESET_B High. */ /* The iCE40 FPGA enters SPI peripheral mode when the CRESET_B pin returns High while the SPI_SS_B pin is Low. */ stm32_gpio_clr(ICE40_SPI_SS); /* reset */ stm32_gpio_clr(ICE40_CRESET); udelay(1); stm32_gpio_set(ICE40_CRESET); if (stm32_gpio_stat(ICE40_CDONE)) { stm32_gpio_set(ICE40_SPI_SS); return -1; } /* After driving CRESET_B High or allowing it to float High the AP must wait a minimum of 300 µs, allowing the iCE40 FPGA to clear its internal configuration memory */ udelay(300); return 0; }
void net_init(void) { printf("%s():...\n", __func__); /* IO init */ stm32_gpio_mode(USART2_TX, ALT_FUNC, PUSH_PULL | SPEED_LOW); stm32_gpio_mode(USART2_RX, ALT_FUNC, PULL_UP); stm32_gpio_af(USART2_RX, GPIO_AF7); stm32_gpio_af(USART2_TX, GPIO_AF7); stm32_gpio_mode(LINK_TXEN, OUTPUT, PUSH_PULL | SPEED_LOW); stm32_gpio_mode(LINK_LOOP, OUTPUT, PUSH_PULL | SPEED_LOW); stm32_gpio_set(LINK_LOOP); stm32_gpio_set(LINK_TXEN); /* initialize the packet buffer pool */ pktbuf_pool_init(); /* DMA configuration for USART2 * TX: DMA1, Stream6, Channel 4 * RX: DMA1, Stream5, Channel 4 */ /* Link init */ rs485_init(&link, STM32_USART2, 1000, STM32F_DMA1, USART2_DMA_STRM_RX, USART2_DMA_CHAN_RX, USART2_DMA_STRM_TX, USART2_DMA_CHAN_TX); cm3_irq_enable(STM32_IRQ_USART2); }
int net_init(void) { tracef("%s():...", __func__); if (lattice_ice40_configure(ice40lp384_bin, sizeof_ice40lp384_bin) < 0) { trace("lattice_ice40_configure() failed!"); return -1; } /* IO init */ stm32_gpio_mode(RS485_RX, ALT_FUNC, PULL_UP); stm32_gpio_af(RS485_RX, GPIO_AF7); stm32_gpio_mode(RS485_TX, ALT_FUNC, PUSH_PULL | SPEED_MED); stm32_gpio_af(RS485_TX, GPIO_AF7); #ifdef RS485_CK stm32_gpio_mode(RS485_CK, ALT_FUNC, PUSH_PULL | SPEED_MED); stm32_gpio_af(RS485_CK, GPIO_AF7); #endif #ifdef RS485_TRIG stm32_gpio_mode(RS485_TRIG, INPUT, PULL_UP); #endif #ifdef RS485_TXEN stm32_gpio_mode(RS485_TXEN, OUTPUT, PUSH_PULL | SPEED_MED); stm32_gpio_set(RS485_TXEN); #endif #ifdef RS485_LOOP stm32_gpio_mode(RS485_LOOP, OUTPUT, PUSH_PULL | SPEED_MED); stm32_gpio_set(RS485_LOOP); #endif #ifdef RS485_MODE stm32_gpio_mode(RS485_MODE, OUTPUT, PUSH_PULL | SPEED_LOW); stm32_gpio_set(RS485_MODE); #endif if (!net.initialized) { /* Link init */ rs485_init(&net.link, RS485_USART, RS485_LINK_SPEED, USART1_DMA, USART1_DMA_CHAN, USART1_RX_DMA_STRM, USART1_TX_DMA_STRM); /* initialize the packet buffer pool */ pktbuf_pool_init(); net_recv_init(); net.probe_flag = thinkos_flag_alloc(); net.initialized = true; } return 0; }
void debug_init(void) { int i; stm32_gpio_clock_en(STM32F_GPIOB); stm32_gpio_mode(STM32F_GPIOB, 9, OUTPUT, SPEED_MED); stm32_gpio_clr(STM32F_GPIOB, 9); stm32_gpio_set(STM32F_GPIOB, 9); for (i = 0; i < 400000; i++) __NOP(); stm32_gpio_clr(STM32F_GPIOB, 9); for (i = 0; i < 400000; i++) __NOP(); stm32_gpio_set(STM32F_GPIOB, 9); for (i = 0; i < 400000; i++) __NOP(); stm32_gpio_clr(STM32F_GPIOB, 9); for (i = 0; i < 400000; i++) __NOP(); stm32_gpio_set(STM32F_GPIOB, 9); for (i = 0; i < 400000; i++) __NOP(); stm32_gpio_clr(STM32F_GPIOB, 9); for (i = 0; i < 400000; i++) __NOP(); }
/* * Initialize IO pins and SPI low level device */ static int lattice_ice40_io_init(unsigned int freq) { struct stm32f_spi * spi = STM32F_SPI3; unsigned int div; int br; /* Enable peripheral clock */ stm32_clk_enable(STM32_RCC, STM32_CLK_GPIOB); stm32_clk_enable(STM32_RCC, STM32_CLK_GPIOC); stm32_clk_enable(STM32_RCC, STM32_CLK_GPIOE); stm32_clk_enable(STM32_RCC, STM32_CLK_SPI3); /* Configure IO pins */ stm32_gpio_mode(ICE40_CDONE, INPUT, PULL_UP); stm32_gpio_set(ICE40_CRESET); stm32_gpio_mode(ICE40_CRESET, OUTPUT, SPEED_MED); stm32_gpio_set(ICE40_SPI_SS); stm32_gpio_mode(ICE40_SPI_SS, OUTPUT, SPEED_MED); stm32_gpio_mode(ICE40_SPI_SCK, ALT_FUNC, PUSH_PULL | SPEED_LOW); stm32_gpio_af(ICE40_SPI_SCK, GPIO_AF6); stm32_gpio_mode(ICE40_SPI_SDO, ALT_FUNC, PULL_UP); stm32_gpio_af(ICE40_SPI_SDO, GPIO_AF6); stm32_gpio_mode(ICE40_SPI_SDI, ALT_FUNC, PUSH_PULL | SPEED_LOW); stm32_gpio_af(ICE40_SPI_SDI, GPIO_AF6); /* Configure SPI */ div = stm32_clk_hz(STM32_CLK_SPI3) / freq / 2; br = 31 - __clz(div); if (div > (1 << br)) br++; DCC_LOG3(LOG_TRACE, "SPI freq=%d div=%d br=%d", freq, div, br); spi->cr1 = 0; spi->cr2 = 0; spi->i2scfgr = 0; spi->i2spr = 0; /* Master mode, MSB first */ spi->cr1 = SPI_SPE | SPI_BR_SET(br) | SPI_MSTR | SPI_SSM | SPI_SSI; return 0; }
void net_probe_disable(void) { #ifdef RS485_MODE DCC_LOG(LOG_TRACE, "Normal mode."); stm32_gpio_set(RS485_MODE); #endif }
/* ------------------------------------------------------------------------- * Test * ------------------------------------------------------------------------- */ void io_init(void) { thinkos_udelay_factor(&udelay_factor); stm32_clk_enable(STM32_RCC, STM32_CLK_GPIOA); stm32_clk_enable(STM32_RCC, STM32_CLK_GPIOB); stm32_clk_enable(STM32_RCC, STM32_CLK_GPIOC); stm32_clk_enable(STM32_RCC, STM32_CLK_GPIOD); stm32_clk_enable(STM32_RCC, STM32_CLK_GPIOE); /* USART5 TX */ stm32_gpio_mode(UART5_TX, ALT_FUNC, PUSH_PULL | SPEED_LOW); stm32_gpio_af(UART5_TX, GPIO_AF8); /* USART5 RX */ stm32_gpio_mode(UART5_RX, ALT_FUNC, PULL_UP); stm32_gpio_af(UART5_RX, GPIO_AF8); stm32_gpio_mode(IO_RS485_RX, ALT_FUNC, PULL_UP); stm32_gpio_af(IO_RS485_RX, RS485_USART_AF); stm32_gpio_mode(IO_RS485_TX, ALT_FUNC, PUSH_PULL | SPEED_MED); stm32_gpio_af(IO_RS485_TX, RS485_USART_AF); stm32_gpio_mode(IO_RS485_MODE, OUTPUT, PUSH_PULL | SPEED_LOW); stm32_gpio_set(IO_RS485_MODE); /* USART6_TX */ stm32_gpio_mode(UART6_TX, ALT_FUNC, PUSH_PULL | SPEED_LOW); stm32_gpio_af(UART6_TX, GPIO_AF7); /* USART6_RX */ stm32_gpio_mode(UART6_RX, ALT_FUNC, PULL_UP); stm32_gpio_af(UART6_RX, GPIO_AF7); }
/* * Configure an ICE40 FPGA device */ int lattice_ice40_configure(const uint8_t * buf, unsigned int max) { int ret; int n; int i; lattice_ice40_io_init(50000); DCC_LOG2(LOG_TRACE, "bin=0x%08x max=%d", buf, max); while ((ret = conf_start()) < 0) { DCC_LOG(LOG_ERROR, "conf_start() failed!"); return ret; } for (n = 0; n < max; ++n) { if (stm32_gpio_stat(ICE40_CDONE)) break; conf_wr(buf[n]); } if (n >= max) { for (i = 0; i < 128; ++i) { if (stm32_gpio_stat(ICE40_CDONE)) break; conf_wr(0x00); } if (!stm32_gpio_stat(ICE40_CDONE)) { stm32_gpio_set(ICE40_SPI_SS); return -2; } } DCC_LOG1(LOG_TRACE, "%d bytes", n); /* After the CDONE output pin goes High, send at least 49 additional dummy bits, effectively 49 additional SPI_SCK clock cycles measured from rising-edge to rising-edge. */ for (i = 0; i < 7; ++i) conf_wr(0x00); stm32_gpio_set(ICE40_SPI_SS); return n; }
int net_probe(void) { void * pkt; int ret; /* drain the transmmit queue */ pkt = rs485_pkt_drain(&net.link); if (pkt != NULL) pktbuf_free(pkt); /* set the probe pin low */ net.probe_mode = true; stm32_gpio_clr(RS485_MODE); DCC_LOG(LOG_TRACE, "Probe mode."); thinkos_flag_clr(net.probe_flag); if ((pkt = pktbuf_alloc()) != NULL) { uint32_t seq; while ((seq = rand()) == 0); /* send a probe packet */ sprintf((char *)pkt, "PRB=%08x", seq); DCC_LOG1(LOG_TRACE, "seq=0x%08x", seq); rs485_pkt_enqueue(&net.link, pkt, 12); net.stat.tx.pkt_cnt++; net.stat.tx.octet_cnt += 12; /* wait for the end of transmission */ pkt = rs485_pkt_drain(&net.link); pktbuf_free(pkt); if ((ret = thinkos_flag_timedwait(net.probe_flag, 10)) == 0) { if (seq != net.probe_seq) { DCC_LOG(LOG_WARNING, "probe sequence mismatch!"); ret = -1; } } else if (ret == THINKOS_ETIMEDOUT) { DCC_LOG(LOG_WARNING, "probe sequence timedout!"); } DCC_LOG1(LOG_TRACE, "seq=0x%08x", seq); } else { DCC_LOG(LOG_ERROR, "pktbuf_alloc() failed!"); ret = -1; } /* set the probe pin high */ net.probe_mode = false; stm32_gpio_set(RS485_MODE); DCC_LOG(LOG_TRACE, "Probe mode."); return ret; }
static inline void __led_on(int id) { stm32_gpio_set(led_io[id].gpio, led_io[id].pin); led_state[id] = 1; }
static void isink_io_cfg(unsigned int mode) { int32_t s1; int32_t s2; int32_t s3; switch (mode) { case 0: /* (128 45)[mA] (640 225)[mV] [ VCC VCC GND ] [ GND VCC GND ] GND */ stm32_gpio_mode(SINK1, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_mode(SINK2, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_mode(SINK3, OUTPUT, PUSH_PULL | SPEED_HIGH); stm32_gpio_clr(SINK4); s1 = -1; s2 = 0; s3 = 0; break; case 1: /* (160 45)[mA] (800 225)[mV] [ VCC VCC NC ] [ GND VCC GND ] GND */ stm32_gpio_mode(SINK1, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_mode(SINK2, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_mode(SINK3, ALT_FUNC, OPEN_DRAIN | SPEED_HIGH); stm32_gpio_clr(SINK4); s1 = -1; s2 = 0; s3 = -1; break; case 2: default: /* (160 57)[mA] (800 285)[mV] [ VCC VCC NC ] [ GND VCC NC ] GND */ stm32_gpio_mode(SINK1, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_mode(SINK2, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_mode(SINK3, ALT_FUNC, OPEN_DRAIN | SPEED_HIGH); stm32_gpio_clr(SINK4); s1 = -1; s2 = 0; s3 = 0; break; case 3: /* (168 76)[mA] (840 380)[mV] [ NC VCC NC ] [ GND VCC GND ] VCC */ stm32_gpio_mode(SINK1, ALT_FUNC, OPEN_DRAIN | SPEED_HIGH); stm32_gpio_mode(SINK2, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_mode(SINK3, ALT_FUNC, OPEN_DRAIN | SPEED_HIGH); stm32_gpio_set(SINK4); s1 = -1; s2 = 0; s3 = -1; break; case 4: /* (179 45)[mA] (895 225)[mV] [ GND VCC VCC ] [ GND VCC GND ] GND */ stm32_gpio_mode(SINK1, OUTPUT, PUSH_PULL | SPEED_HIGH); stm32_gpio_mode(SINK2, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_mode(SINK3, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_clr(SINK4); s1 = 0; s2 = 0; s3 = -1; break; case 5: /* (204 45)[mA] (1020 225)[mV] [ NC VCC VCC ] [ GND VCC GND ] GND */ stm32_gpio_mode(SINK1, ALT_FUNC, OPEN_DRAIN | SPEED_HIGH); stm32_gpio_mode(SINK2, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_mode(SINK3, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_clr(SINK4); s1 = -1; s2 = 0; s3 = -1; break; case 6: /* (204 52)[mA] (1020 260)[mV] [ NC VCC VCC ] [ NC VCC GND ] GND */ stm32_gpio_mode(SINK1, ALT_FUNC, OPEN_DRAIN | SPEED_HIGH); stm32_gpio_mode(SINK2, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_mode(SINK3, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_clr(SINK4); s1 = 0; s2 = 0; s3 = -1; break; case 7: /* (214 76)[mA] (1070 380)[mV] [ VCC VCC GND ] [ GND VCC GND ] VCC */ stm32_gpio_mode(SINK1, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_mode(SINK2, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_mode(SINK3, OUTPUT, PUSH_PULL | SPEED_HIGH); stm32_gpio_set(SINK4); s1 = -1; s2 = 0; s3 = 0; break; case 8: /* (216 82)[mA] (1080 410)[mV] [ VCC GND VCC ] [ VCC GND GND ] GND */ stm32_gpio_mode(SINK1, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_mode(SINK2, OUTPUT, PUSH_PULL | SPEED_HIGH); stm32_gpio_mode(SINK3, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_clr(SINK4); s1 = 0; s2 = 0; s3 = -1; break; case 9: /* (232 82)[mA] (1160 410)[mV] [ VCC NC VCC ] [ VCC GND GND ] GND */ stm32_gpio_mode(SINK1, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_mode(SINK2, ALT_FUNC, OPEN_DRAIN | SPEED_HIGH); stm32_gpio_mode(SINK3, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_clr(SINK4); s1 = 0; s2 = -1; s3 = -1; break; case 10: /* (232 89)[mA] (1160 445)[mV] [ VCC NC VCC ] [ VCC NC GND ] GND */ stm32_gpio_mode(SINK1, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_mode(SINK2, ALT_FUNC, OPEN_DRAIN | SPEED_HIGH); stm32_gpio_mode(SINK3, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_clr(SINK4); s1 = 0; s2 = 0; s3 = -1; break; case 11: /* (261 45)[mA] (1305 225)[mV] [ VCC VCC VCC ] [ GND VCC GND ] GND */ stm32_gpio_mode(SINK1, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_mode(SINK2, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_mode(SINK3, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_clr(SINK4); s1 = -1; s2 = 0; s3 = -1; break; case 12: /* (261 82)[mA] (1305 410)[mV] [ VCC VCC VCC ] [ VCC GND GND ] GND */ stm32_gpio_mode(SINK1, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_mode(SINK2, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_mode(SINK3, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_clr(SINK4); s1 = 0; s2 = -1; s3 = -1; break; case 13: /* (261 128)[mA] (1305 640)[mV] [ VCC VCC VCC ] [ VCC VCC GND ] GND */ stm32_gpio_mode(SINK1, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_mode(SINK2, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_mode(SINK3, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_clr(SINK4); s1 = 0; s2 = 0; s3 = -1; break; case 14: /* (299 76)[mA] (1495 380)[mV] [ GND VCC VCC ] [ GND VCC GND ] VCC */ stm32_gpio_mode(SINK1, OUTPUT, PUSH_PULL | SPEED_HIGH); stm32_gpio_mode(SINK2, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_mode(SINK3, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_set(SINK4); s1 = 0; s2 = 0; s3 = -1; break; case 15: /* (324 76)[mA] (1620 380)[mV] [ VCC VCC NC ] [ GND VCC GND ] VCC */ stm32_gpio_mode(SINK1, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_mode(SINK2, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_mode(SINK3, ALT_FUNC, OPEN_DRAIN | SPEED_HIGH); stm32_gpio_set(SINK4); s1 = -1; s2 = 0; s3 = -1; break; case 16: /* (324 115)[mA] (1620 575)[mV] [ VCC VCC NC ] [ GND VCC NC ] VCC */ stm32_gpio_mode(SINK1, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_mode(SINK2, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_mode(SINK3, ALT_FUNC, OPEN_DRAIN | SPEED_HIGH); stm32_gpio_set(SINK4); s1 = -1; s2 = 0; s3 = 0; break; case 17: /* (324 138)[mA] (1620 690)[mV] [ VCC VCC NC ] [ VCC GND GND ] VCC */ stm32_gpio_mode(SINK1, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_mode(SINK2, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_mode(SINK3, ALT_FUNC, OPEN_DRAIN | SPEED_HIGH); stm32_gpio_set(SINK4); s1 = 0; s2 = -1; s3 = -1; break; case 18: /* (362 138)[mA] (1810 690)[mV] [ VCC GND VCC ] [ VCC GND GND ] VCC */ stm32_gpio_mode(SINK1, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_mode(SINK2, OUTPUT, PUSH_PULL | SPEED_HIGH); stm32_gpio_mode(SINK3, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_set(SINK4); s1 = 0; s2 = 0; s3 = -1; break; case 19: /* (379 76)[mA] (1895 380)[mV] [ NC VCC VCC ] [ GND VCC GND ] VCC */ stm32_gpio_mode(SINK1, ALT_FUNC, OPEN_DRAIN | SPEED_HIGH); stm32_gpio_mode(SINK2, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_mode(SINK3, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_set(SINK4); s1 = -1; s2 = 0; s3 = -1; break; case 20: /* (379 96)[mA] (1895 480)[mV] [ NC VCC VCC ] [ NC VCC GND ] VCC */ stm32_gpio_mode(SINK1, ALT_FUNC, OPEN_DRAIN | SPEED_HIGH); stm32_gpio_mode(SINK2, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_mode(SINK3, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_set(SINK4); s1 = 0; s2 = 0; s3 = -1; break; case 21: /* (409 138)[mA] (2045 690)[mV] [ VCC NC VCC ] [ VCC GND GND ] VCC */ stm32_gpio_mode(SINK1, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_mode(SINK2, ALT_FUNC, OPEN_DRAIN | SPEED_HIGH); stm32_gpio_mode(SINK3, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_set(SINK4); s1 = 0; s2 = -1; s3 = -1; break; case 22: /* (409 156)[mA] (2045 780)[mV] [ VCC NC VCC ] [ VCC NC GND ] VCC */ stm32_gpio_mode(SINK1, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_mode(SINK2, ALT_FUNC, OPEN_DRAIN | SPEED_HIGH); stm32_gpio_mode(SINK3, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_set(SINK4); s1 = 0; s2 = 0; s3 = -1; break; case 23: /* (438 76)[mA] (2190 380)[mV] [ VCC VCC VCC ] [ GND VCC GND ] VCC */ stm32_gpio_mode(SINK1, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_mode(SINK2, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_mode(SINK3, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_set(SINK4); s1 = -1; s2 = 0; s3 = -1; break; case 24: /* (438 138)[mA] (2190 690)[mV] [ VCC VCC VCC ] [ VCC GND GND ] VCC */ stm32_gpio_mode(SINK1, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_mode(SINK2, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_mode(SINK3, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_set(SINK4); s1 = 0; s2 = -1; s3 = -1; break; case 25: /* (438 214)[mA] (2190 1070)[mV] [ VCC VCC VCC ] [ VCC VCC GND ] VCC */ stm32_gpio_mode(SINK1, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_mode(SINK2, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_mode(SINK3, ALT_FUNC, PUSH_PULL | SPEED_HIGH); stm32_gpio_set(SINK4); s1 = 0; s2 = 0; s3 = -1; break; } isink_drv.s1 = s1; isink_drv.s2 = s2; isink_drv.s3 = s3; }
void led_on(int id) { stm32_gpio_set(led_io[id].gpio, led_io[id].pin); }