void cmdq_core_dump_clock_gating(void)
{
uint32_t value[3] = { 0 };
value[0] = CMDQ_REG_GET32(MMSYS_CONFIG_BASE + 0x100);
value[1] = CMDQ_REG_GET32(MMSYS_CONFIG_BASE + 0x110);
/* value[2] = CMDQ_REG_GET32(MMSYS_CONFIG_BASE + 0x890); */
CMDQ_ERR("MMSYS_CG_CON0(deprecated): 0x%08x, MMSYS_CG_CON1: 0x%08x\n", value[0], value[1]);
/* CMDQ_ERR("MMSYS_DUMMY_REG: 0x%08x\n", value[2]); */
#ifdef CONFIG_MTK_LEGACY
#ifndef CONFIG_MTK_FPGA
CMDQ_ERR("ISPSys clock state %d\n", subsys_is_on(SYS_IMG));
CMDQ_ERR("DisSys clock state %d\n", subsys_is_on(SYS_DIS));
/* CMDQ_ERR("VDESys clock state %d\n", subsys_is_on(SYS_VDE)); */
#endif
#endif /* defined(CONFIG_MTK_LEGACY) */
}
static void mt_power_gs_compare_pll(void)
{
int i;
#define ID_NAME(n) {n, __stringify(n)}
struct {
const int id;
const char *name;
} plls[NR_PLLS] = {
ID_NAME(ARMCA15PLL),
ID_NAME(ARMCA7PLL),
ID_NAME(MAINPLL),
ID_NAME(MSDCPLL),
ID_NAME(UNIVPLL),
ID_NAME(MMPLL),
ID_NAME(VENCPLL),
ID_NAME(TVDPLL),
ID_NAME(MPLL),
ID_NAME(VCODECPLL),
ID_NAME(APLL1),
ID_NAME(APLL2),
};
struct {
const int id;
const char *name;
} subsyss[NR_SYSS] = {
ID_NAME(SYS_MD1),
ID_NAME(SYS_DIS),
// ID_NAME(SYS_MFG_ASYNC),
// ID_NAME(SYS_MFG_2D),
ID_NAME(SYS_MFG),
ID_NAME(SYS_ISP),
ID_NAME(SYS_VDE),
ID_NAME(SYS_MJC),
ID_NAME(SYS_VEN),
ID_NAME(SYS_AUD),
};
for (i = 0; i < NR_PLLS; i++) {
if (pll_is_on(i))
printk("%s: on\n", plls[i].name);
}
for (i = 0; i < NR_SYSS; i++) {
if (subsys_is_on(i))
printk("%s: on\n", subsyss[i].name);
}
}
void cmdq_virtual_dump_clock_gating(void)
{
uint32_t value[3] = { 0 };
value[0] = CMDQ_REG_GET32(MMSYS_CONFIG_BASE + 0x100);
value[1] = CMDQ_REG_GET32(MMSYS_CONFIG_BASE + 0x110);
CMDQ_ERR("MMSYS_CG_CON0(deprecated): 0x%08x, MMSYS_CG_CON1: 0x%08x\n", value[0], value[1]);
#ifdef CMDQ_USE_LEGACY
value[2] = CMDQ_REG_GET32(MMSYS_CONFIG_BASE + 0x890);
CMDQ_ERR("MMSYS_DUMMY_REG: 0x%08x\n", value[2]);
#endif
#if !defined(CMDQ_USE_CCF) && !defined(CONFIG_MTK_FPGA)
CMDQ_ERR("DisSys clock state %d\n", subsys_is_on(SYS_DIS));
#ifdef CMDQ_DUMP_IMG_CLOCK_STATE
CMDQ_ERR("IMGSys clock state %d\n", subsys_is_on(SYS_IMG));
#else
CMDQ_ERR("ISPSys clock state %d\n", subsys_is_on(SYS_ISP));
CMDQ_ERR("VDESys clock state %d\n", subsys_is_on(SYS_VDE));
#endif
#endif
}
static void mt_power_gs_compare_pll(void)
{
if (pll_is_on(MSDCPLL)) {
printk("MSDCPLL: %s\n", pll_is_on(MSDCPLL) ? "on" : "off");
}
if (subsys_is_on(SYS_MD1)) {
printk("SYS_MD1: %s\n", subsys_is_on(SYS_MD1) ? "on" : "off");
}
if (subsys_is_on(SYS_CONN)) {
printk("SYS_CONN: %s\n", subsys_is_on(SYS_CONN) ? "on" : "off");
}
if (subsys_is_on(SYS_DIS)) {
printk("SYS_DIS: %s\n", subsys_is_on(SYS_DIS) ? "on" : "off");
}
if (subsys_is_on(SYS_MFG)) {
printk("SYS_MFG: %s\n", subsys_is_on(SYS_MFG) ? "on" : "off");
}
if (subsys_is_on(SYS_ISP)) {
printk("SYS_ISP: %s\n", subsys_is_on(SYS_ISP) ? "on" : "off");
}
if (subsys_is_on(SYS_VDE)) {
printk("SYS_VDE: %s\n", subsys_is_on(SYS_VDE) ? "on" : "off");
}
}
void dcm_dump_regs(unsigned int type)
{
#if 0
//volatile unsigned int dcm_cfg;
mutex_lock(&dcm_lock);
if (type & CPU_DCM) {
volatile unsigned int l2c_sram_ctrl, cci_clk_ctrl;
l2c_sram_ctrl = dcm_readl(L2C_SRAM_CTRL);
cci_clk_ctrl = dcm_readl(CCI_CLK_CTRL);
dcm_info("[CPU_DCM]L2C_SRAM_CTRL(0x%08x)\n", l2c_sram_ctrl);
dcm_info("[CPU_DCM]CCI_CLK_CTRL (0x%08x)\n", cci_clk_ctrl);
}
#if 0
if (type & TOPCKGEN_DCM) {
volatile unsigned int dcm_cfg;
dcm_cfg = dcm_readl(DCM_CFG);
dcm_info("[IFR_DCM]DCM_CFG(0x%08x)\n", dcm_cfg);
}
#endif
if (type & IFR_DCM) {
volatile unsigned int ca7_ckdiv1, infra_topckgen_dcmctl, infra_topckgen_dcmdbc;
volatile unsigned int infra_globalcon_dcmctl,infra_globalcon_dcmdbc;
volatile unsigned int infra_globalcon_dcmsel,dramc;
ca7_ckdiv1 = dcm_readl(CA7_CKDIV1);
infra_topckgen_dcmctl = dcm_readl(INFRA_TOPCKGEN_DCMCTL);
infra_topckgen_dcmdbc = dcm_readl(INFRA_TOPCKGEN_DCMDBC);
infra_globalcon_dcmctl = dcm_readl(INFRA_GLOBALCON_DCMCTL);
infra_globalcon_dcmdbc = dcm_readl(INFRA_GLOBALCON_DCMDBC);
infra_globalcon_dcmsel = dcm_readl(INFRA_GLOBALCON_DCMSEL);
dramc = dcm_readl(DRAMC_PD_CTRL);
dcm_info("[IFR_DCM]CA7_CKDIV1(0x%08x)\n", ca7_ckdiv1);
dcm_info("[IFR_DCM]INFRA_TOPCKGEN_DCMCTL (0x%08x)\n", infra_topckgen_dcmctl);
dcm_info("[IFR_DCM]INFRA_TOPCKGEN_DCMDBC (0x%08x)\n", infra_topckgen_dcmdbc);
dcm_info("[IFR_DCM]INFRA_GLOBALCON_DCMCTL(0x%08x)\n", infra_globalcon_dcmctl);
dcm_info("[IFR_DCM]INFRA_GLOBALCON_DCMDBC(0x%08x)\n", infra_globalcon_dcmdbc);
dcm_info("[IFR_DCM]INFRA_GLOBALCON_DCMSEL(0x%08x)\n", infra_globalcon_dcmsel);
dcm_info("[IFR_DCM]DRAMC_PD_CTRL (0x%08x)\n", dramc);
}
if (type & PER_DCM) {
volatile unsigned int peri_globalcon_dcmctl;
volatile unsigned int peri_globalcon_dcmdbc, peri_globalcon_dcmsel;
volatile unsigned int msdc0_ip_dcm,msdc1_ip_dcm,msdc2_ip_dcm,msdc3_ip_dcm;
volatile unsigned int usb0_dcm,pmic_wrap_dcm_en;
volatile unsigned int i2c0_i2creg_hw_cg_en,i2c1_i2creg_hw_cg_en,i2c2_i2creg_hw_cg_en;
peri_globalcon_dcmctl = dcm_readl(PERI_GLOBALCON_DCMCTL);
peri_globalcon_dcmdbc = dcm_readl(PERI_GLOBALCON_DCMDBC);
peri_globalcon_dcmsel = dcm_readl(PERI_GLOBALCON_DCMFSEL);
msdc0_ip_dcm = dcm_readl(MSDC0_IP_DCM);
msdc1_ip_dcm = dcm_readl(MSDC1_IP_DCM);
msdc2_ip_dcm = dcm_readl(MSDC2_IP_DCM);
msdc3_ip_dcm = dcm_readl(MSDC3_IP_DCM);
usb0_dcm = dcm_readl(USB0_DCM);
pmic_wrap_dcm_en = dcm_readl(PMIC_WRAP_DCM_EN);
i2c0_i2creg_hw_cg_en = dcm_readl(I2C0_I2CREG_HW_CG_EN);
i2c1_i2creg_hw_cg_en = dcm_readl(I2C1_I2CREG_HW_CG_EN);
i2c2_i2creg_hw_cg_en = dcm_readl(I2C2_I2CREG_HW_CG_EN);
dcm_info("[PER_DCM]PERI_GLOBALCON_DCMCTL (0x%08x)\n", peri_globalcon_dcmctl);
dcm_info("[PER_DCM]PERI_GLOBALCON_DCMDBC (0x%08x)\n", peri_globalcon_dcmdbc);
dcm_info("[PER_DCM]PERI_GLOBALCON_DCMFSEL (0x%08x)\n", peri_globalcon_dcmsel);
dcm_info("[PER_DCM]MSDC0_IP_DCM (0x%08x)\n", msdc0_ip_dcm);
dcm_info("[PER_DCM]MSDC1_IP_DCM (0x%08x)\n", msdc1_ip_dcm);
dcm_info("[PER_DCM]MSDC2_IP_DCM (0x%08x)\n", msdc2_ip_dcm);
dcm_info("[PER_DCM]MSDC3_IP_DCM (0x%08x)\n", msdc3_ip_dcm);
dcm_info("[PER_DCM]USB0_DCM (0x%08x)\n", usb0_dcm);
dcm_info("[PER_DCM]PMIC_WRAP_DCM_EN (0x%08x)\n", pmic_wrap_dcm_en);
dcm_info("[PER_DCM]I2C0_I2CREG_HW_CG_EN (0x%08x)\n", i2c0_i2creg_hw_cg_en);
dcm_info("[PER_DCM]I2C1_I2CREG_HW_CG_EN (0x%08x)\n", i2c1_i2creg_hw_cg_en);
dcm_info("[PER_DCM]I2C2_I2CREG_HW_CG_EN (0x%08x)\n", i2c2_i2creg_hw_cg_en);
}
if (type & SMI_DCM) {
volatile unsigned int smi_dcm_control,smi_com_set,mmu_dcm;
smi_dcm_control = dcm_readl(SMI_DCM_CONTROL);
smi_com_set = dcm_readl(SMI_CON_SET);
//m4u_dcm
mmu_dcm = dcm_readl(MMU_DCM);
dcm_info("[PER_DCM]SMI_DCM_CONTROL (0x%08x)\n", smi_dcm_control);
dcm_info("[PER_DCM]SMI_CON_SET (0x%08x)\n", smi_com_set);
dcm_info("[PER_DCM]MMU_DCM (0x%08x)\n", mmu_dcm);
}
#if 0 //ROME not MFG
if (type & MFG_DCM) {
if (subsys_is_on(SYS_MFG)) {
volatile unsigned int mfg0;
mfg0 = dcm_readl(MFG_DCM_CON_0);
dcm_info("[MFG_DCM]MFG_DCM_CON_0(0x%08x)\n",mfg0);
} else {
dcm_info("[MFG_DCM]subsy MFG is off\n");
}
}
#endif
if (type & DIS_DCM) {
if (subsys_is_on(SYS_DIS)) {
volatile unsigned int dis0, dis_set0, dis_clr0,dis1, dis_set1, dis_clr1;
volatile unsigned int smilarb0_dcm_sta,smilarb0_dcm_con,smilarb0_dcm_set,smilarb0_dcm_clr;
dis0 = dcm_readl(MMSYS_HW_DCM_DIS0);
dis_set0 = dcm_readl(MMSYS_HW_DCM_DIS_SET0);
dis_clr0 = dcm_readl(MMSYS_HW_DCM_DIS_CLR0);
dis1 = dcm_readl(MMSYS_HW_DCM_DIS1);
dis_set1 = dcm_readl(MMSYS_HW_DCM_DIS_SET1);
dis_clr1 = dcm_readl(MMSYS_HW_DCM_DIS_CLR1);
smilarb0_dcm_sta = dcm_readl(SMI_LARB0_STA);
smilarb0_dcm_con = dcm_readl(SMI_LARB0_CON);
smilarb0_dcm_set = dcm_readl(SMI_LARB0_CON_SET);
smilarb0_dcm_clr = dcm_readl(SMI_LARB0_CON_CLR);
dcm_info("[DIS_DCM]MMSYS_HW_DCM_DIS0 (0x%08x)\n", dis0);
dcm_info("[DIS_DCM]MMSYS_HW_DCM_DIS_SET0 (0x%08x)\n", dis_set0);
dcm_info("[DIS_DCM]MMSYS_HW_DCM_DIS_CLR0 (0x%08x)\n", dis_clr0);
dcm_info("[DIS_DCM]MMSYS_HW_DCM_DIS1 (0x%08x)\n", dis1);
dcm_info("[DIS_DCM]MMSYS_HW_DCM_DIS_SET1 (0x%08x)\n", dis_set1);
dcm_info("[DIS_DCM]MMSYS_HW_DCM_DIS_CLR1 (0x%08x)\n", dis_clr1);
dcm_info("[DIS_DCM]SMI_LARB0_STA (0x%08x)\n", smilarb0_dcm_sta);
dcm_info("[DIS_DCM]SMI_LARB0_CON (0x%08x)\n", smilarb0_dcm_con);
dcm_info("[DIS_DCM]SMI_LARB0_CON_SET (0x%08x)\n", smilarb0_dcm_set);
dcm_info("[DIS_DCM]SMI_LARB0_CON_CLR (0x%08x)\n", smilarb0_dcm_clr);
} else {
dcm_info("[DIS_DCM]subsys DIS is off\n");
}
}
if (type & ISP_DCM) {
if (subsys_is_on(SYS_ISP)) {
volatile unsigned int cam_ctl_raw_dcm_dis, cam_ctl_rgb_dcm_dis, cam_ctl_yuv_dcm_dis;
volatile unsigned int cam_ctl_cdp_dcm_dis,cam_ctl_dma_dcm_dis;
volatile unsigned int venc_cg_ctrl,venc_ce,venc_clk_dcm_ctrl,jpgenc,smi_larb2_con_set;
cam_ctl_raw_dcm_dis = dcm_readl(CAM_CTL_RAW_DCM_DIS);
cam_ctl_rgb_dcm_dis = dcm_readl(CAM_CTL_RGB_DCM_DIS);
cam_ctl_yuv_dcm_dis = dcm_readl(CAM_CTL_YUV_DCM_DIS);
cam_ctl_cdp_dcm_dis = dcm_readl(CAM_CTL_CDP_DCM_DIS);
cam_ctl_dma_dcm_dis = dcm_readl(CAM_CTL_DMA_DCM_DIS);
venc_cg_ctrl = dcm_readl(VENC_CLK_CG_CTRL);
venc_ce = dcm_readl(VENC_CE);
venc_clk_dcm_ctrl = dcm_readl(VENC_CLK_DCM_CTRL);
jpgenc = dcm_readl(JPGENC_DCM_CTRL);
smi_larb2_con_set = dcm_readl(SMI_LARB2_CON_SET);
dcm_info("[ISP_DCM]CAM_CTL_RAW_DCM_DIS (0x%08x)\n", cam_ctl_raw_dcm_dis);
dcm_info("[ISP_DCM]CAM_CTL_RGB_DCM_DIS (0x%08x)\n", cam_ctl_rgb_dcm_dis);
dcm_info("[ISP_DCM]CAM_CTL_YUV_DCM_DIS (0x%08x)\n", cam_ctl_yuv_dcm_dis);
dcm_info("[ISP_DCM]CAM_CTL_CDP_DCM_DIS (0x%08x)\n", cam_ctl_cdp_dcm_dis);
dcm_info("[ISP_DCM]CAM_CTL_DMA_DCM_DIS (0x%08x)\n", cam_ctl_dma_dcm_dis);
dcm_info("[ISP_DCM]VENC_CLK_CG_CTRL (0x%08x)\n", venc_cg_ctrl);
dcm_info("[ISP_DCM]VENC_CE (0x%08x)\n", venc_ce);
dcm_info("[ISP_DCM]VENC_CLK_DCM_CTRL (0x%08x)\n", venc_clk_dcm_ctrl);
dcm_info("[ISP_DCM]JPGENC_DCM_CTRL (0x%08x)\n", jpgenc);
dcm_info("[ISP_DCM]SMI_LARB2_CON_SET (0x%08x)\n", smi_larb2_con_set);
} else {
dcm_info("[ISP_DCM]subsys ISP is off\n");
}
}
dcm_clrl (VDEC_DCM_CON , 0x00000001); //0x16000018
dcm_setl (SMI_LARB1_CON_SET , 0x00008000); //0x16010014
if (type & VDE_DCM) {
if (subsys_is_on(SYS_VDE)) {
volatile unsigned int vdec_dcm_con,smi_larb1_con_set;
vdec_dcm_con = dcm_readl(VDEC_DCM_CON);
smi_larb1_con_set = dcm_readl(SMI_LARB1_CON_SET);
dcm_info("[VDE_DCM]VDEC_DCM_CON (0x%08x)\n", vdec_dcm_con);
dcm_info("[VDE_DCM]SMI_LARB1_CON_SET (0x%08x)\n", smi_larb1_con_set);
} else {
dcm_info("[VDE_DCM]subsys VDE is off\n");
}
}
if (type & MJC_DCM) {
if (subsys_is_on(SYS_MJC)) {
volatile unsigned int mjc_hw_dcm_dis,mjc_hw_dcm_dis_set,mjc_hw_dcm_dis_clr;
mjc_hw_dcm_dis = dcm_readl(MJC_HW_DCM_DIS);
mjc_hw_dcm_dis_set = dcm_readl(MJC_HW_DCM_DIS_SET);
mjc_hw_dcm_dis_clr = dcm_readl(MJC_HW_DCM_DIS_CLR);
dcm_info("[MJC_DCM]MJC_HW_DCM_DIS (0x%08x)\n", mjc_hw_dcm_dis);
dcm_info("[MJC_DCM]MJC_HW_DCM_DIS_SET(0x%08x)\n", mjc_hw_dcm_dis_set);
dcm_info("[MJC_DCM]MJC_HW_DCM_DIS_CLR(0x%08x)\n", mjc_hw_dcm_dis_clr);
}else {
dcm_info("[SYS_MJC]subsys MJC is off\n");
}
}
mutex_unlock(&dcm_lock);
#endif
}
/*
SMI_LARB0: DISP/MDP(MMSYS)
SMI_LARB1: VDEC
SMI_LARB2: ISP
SMI_LARB3: VENC
SMI_LARB4: MJC
*/
void dcm_enable(unsigned int type)
{
#if 1
dcm_info("[%s]type:0x%08x\n", __func__, type);
mutex_lock(&dcm_lock);
if (type & CPU_DCM) {
dcm_info("[%s][CPU_DCM ]=0x%08x\n", __func__,CPU_DCM);
dcm_clrl (MCUSYS_CONFIG , 0x0F9C0000); //0xF020001C,
dcm_setl (CACHE_CONFIG , 0x00000B00); //0xF0200100,set bit8,bit9,bit11=1,
dcm_clrl (CACHE_CONFIG , 0x00000400); //0xF0200100,clear bit10,
dcm_setl (ARMPLL_CTL , 0x00000010); //0xF0200160,set bit4,
dcm_sta |= CPU_DCM;
}
#if 0 //because in 92 there is no register need to be set in TOPCKGEN
if (type & TOPCKGEN_DCM) {
dcm_info("[%s][TOPCKGEN_DCM]=0x%08x\n", __func__,TOPCKGEN_DCM);
#ifdef DCM_ENABLE_DCM_CFG //AXI bus dcm, don't need to set by KL Tong
//default value are all 0,use default value
dcm_writel(DCM_CFG, 0xFFFFFF7F);//set bit0~bit4=0,bit7=0,bit8~bit14=0,bit15=0????
#endif
dcm_sta |= TOPCKGEN_DCM;
}
#endif
//Infrasys_dcm
if (type & IFR_DCM) {
dcm_info("[%s][IFR_DCM ]=0x%08x\n", __func__,IFR_DCM);
dcm_clrl (CA7_CKDIV1 , 0x0000001F); //0x10001008//5'h0,00xxx: 1/1,
if(CHIP_SW_VER_02 == mt_get_chip_sw_ver()){
dcm_setl (INFRA_TOPCKGEN_DCMCTL , 0x00000001); //0x10001010,set0=1,
dcm_clrl (INFRA_TOPCKGEN_DCMCTL , 0x00000770); //0x10001010,set4,5,6,8,9,10=0
}
else{
dcm_setl (INFRA_TOPCKGEN_DCMCTL , 0x00000771); //0x10001010,set0,4,5,6,8,9,10=1,
}
dcm_setl (INFRA_GLOBALCON_DCMCTL, 0x00000303); //0x10001050//set bit0,bit1,bit8,bit9=1,DCM debouncing counter=0,
dcm_setl (INFRA_GLOBALCON_DCMDBC ,0x01000100); //0xF0001054,set bit8,24=1,
dcm_clrl (INFRA_GLOBALCON_DCMDBC ,0x007F007F); //0xF0001054,clear bit0~6,16~22,
dcm_setl (INFRA_GLOBALCON_DCMFSEL,0x10100000); //0xF0001058,
dcm_clrl (INFRA_GLOBALCON_DCMFSEL,0x0F0F0F07); //0xF0001058,
dcm_clrl (MM_MMU_DCM_DIS , 0x0000007F); //0xF0205050,
dcm_clrl (PERISYS_MMU_DCM_DIS , 0x0000007F); //0xF0214050,
//DRAMC
dcm_setl (channel_A_DRAMC_PD_CTRL, 0xC3000000); //0xF00041DC,
dcm_clrl (channel_A_DRAMC_PD_CTRL, 0x00000008); //0xF00041DC,
dcm_setl (channel_B_DRAMC_PD_CTRL, 0xC3000000); //0xF00111DC,
dcm_clrl (channel_B_DRAMC_PD_CTRL, 0x00000008); //0xF00111DC,
dcm_sta |= IFR_DCM;
}
if (type & PER_DCM) {
dcm_info("[%s][PER_DCM ]=0x%08x\n", __func__,PER_DCM);
dcm_setl (PERI_GLOBALCON_DCMCTL , 0x000000F3); //0xF0003050,set bit0,1,4~7,
dcm_clrl (PERI_GLOBALCON_DCMCTL , 0x00001F00); //0x10003050//clear bit8~12,
dcm_clrl (PERI_GLOBALCON_DCMDBC , 0x0000000F); //0x10003054//clear bit0~3 ,
dcm_setl (PERI_GLOBALCON_DCMDBC , 0x000000F0); //0x10003054//set bit4~7=1 ,
dcm_clrl (PERI_GLOBALCON_DCMFSEL, 0x001F0F07); //0x10003058//clear bit0~bit2,bit8~bit11,bit16~bit20,
//MSDC module
dcm_setl (MSDC0_PATCH_BIT1 , 0x00200000); //0xF12300B4//set bit21=1,
dcm_clrl (MSDC0_PATCH_BIT1 , 0xFF800000); //0xF12300B4//clear bit23~bit31=0,
dcm_setl (MSDC1_PATCH_BIT1 , 0x00200000); //0xF12400B4//set bit21=1,
dcm_clrl (MSDC1_PATCH_BIT1 , 0xFF800000); //0xF12400B4//clear bit23~bit31=0,
dcm_setl (MSDC2_PATCH_BIT1 , 0x00200000); //0xF12500B4//set bit21=1,
dcm_clrl (MSDC2_PATCH_BIT1 , 0xFF800000); //0xF12500B4//clear bit23~bit31=0,
dcm_setl (MSDC3_PATCH_BIT1 , 0x00200000); //0xF12600B4//set bit21=1,
dcm_clrl (MSDC3_PATCH_BIT1 , 0xFF800000); //0xF12600B4//clear bit23~bit31=0,
//USB
dcm_clrl (USB0_DCM , 0x00070000); //0x11200700//clear bit16~bit18=0,
//PMIC
dcm_setl (PMIC_WRAP_DCM_EN , 0x00000001); //0x1000D13C//set bit0=1,
//I2C
dcm_setl (I2C0_I2CREG_HW_CG_EN , 0x00000001); //0xF1007054//set bit0=1,
dcm_setl (I2C1_I2CREG_HW_CG_EN , 0x00000001); //0xF1008054//set bit0=1,
dcm_setl (I2C2_I2CREG_HW_CG_EN , 0x00000001); //0xF1009054//set bit0=1,
dcm_setl (I2C3_I2CREG_HW_CG_EN , 0x00000001); //0xF1010054//set bit0=1,
dcm_setl (I2C4_I2CREG_HW_CG_EN , 0x00000001); //0xF1011054//set bit0=1,
dcm_sta |= PER_DCM;
}
if (type & SMI_DCM) {
dcm_info("[%s][SMI_DCM ]=0x%08x\n", __func__,SMI_DCM);
dcm_writel (SMI_COMMON_SMI_DCM , 0x00000001); //0xF4022300//set bit 0=1,
dcm_sta |= SMI_DCM;
}
if (type & EMI_DCM) {
dcm_info("[%s][EMI_DCM ]=0x%08x\n", __func__,EMI_DCM);
dcm_setl (EMI_CONM , 0x40000000); //0xF0203060,set bit30=1,
dcm_clrl (EMI_CONM , 0xBF000000); //0xF0203060,clear bit31,bit29,bit28,bit27~bit27,
dcm_sta |= EMI_DCM;
}
if (type & DIS_DCM) {
dcm_info("[%s][DIS_DCM ]=0x%08x,subsys_is_on(SYS_DIS)=%d\n", __func__,DIS_DCM,subsys_is_on(SYS_DIS));
if (subsys_is_on(SYS_DIS)) {
dcm_writel (MMSYS_HW_DCM_DIS0 , 0x00000000); //0x14000120,
dcm_writel (MMSYS_HW_DCM_DIS_SET0 , 0x00000000); //0x14000124,
dcm_writel (MMSYS_HW_DCM_DIS_CLR0 , 0xFFFFFFFF); //0x14000128,
dcm_writel (MMSYS_HW_DCM_DIS1 , 0x00000000); //0xF4000130,
dcm_writel (MMSYS_HW_DCM_DIS_SET1 , 0x00000000); //0x14000130,
dcm_writel (MMSYS_HW_DCM_DIS_CLR1 , 0xFFFFFFFF); //0x14000134,
dcm_setl (SMI_LARB0_CON_SET , 0x00000010); //0x14210014//set bit4=1,
dcm_sta |= DIS_DCM;
}
}
if (type & ISP_DCM) { //video encoder : sensor=>ISP=>VENC
dcm_info("[%s][ISP_DCM ]=0x%08x,subsys_is_on(SYS_ISP)=%d,,subsys_is_on(SYS_VEN)=%d\n", __func__,ISP_DCM,subsys_is_on(SYS_ISP),subsys_is_on(SYS_VEN));
if (subsys_is_on(SYS_ISP) && subsys_is_on(SYS_VEN)) {
//dcm_clrl (CTL_RAW_DCM_DIS , 0x03FFFFFF); //0xF5004188,clear bit0~25
dcm_clrl (CTL_RAW_D_DCM_DIS , 0x024EAFE8); //0xF500418C,clear bit0~25
dcm_clrl (CTL_DMA_DCM_DIS , 0x07FFFFFF); //0xF5004190,clear bit0~26
dcm_clrl (CTL_RGB_DCM_DIS , 0x0000007F); //0xF5004194,clear bit0~6
dcm_clrl (CTL_YUV_DCM_DIS , 0x000FFFFF); //0xF5004198,clear bit0~19
dcm_clrl (CTL_TOP_DCM_DIS , 0x0000000F); //0xF500419C,clear bit0~3
dcm_clrl (FDVT_CTRL , 0x0000001F); //0xF500B19C,clear bit25~28
dcm_setl (VENC_CLK_CG_CTRL , 0xFFFFFFFF); //0xF80020FC ,
dcm_setl (VENC_CLK_DCM_CTRL , 0x00000001); //0xF80020F4//set bit0=1,
dcm_clrl (JPGENC_DCM_CTRL , 0x00000001); //0xF8003300//clear bit0=0,
dcm_clrl (JPGDEC_DCM_CTRL , 0x00000001); //0xF8004300//clear bit0=0,
dcm_setl (SMI_LARB2_CON_SET , 0x00000010); //0x15001014//set bit0=1,
dcm_setl (SMI_LARB3_CON_SET , 0x00000010); //0x18001014//set bit0=1,
dcm_sta |= ISP_DCM;
}
}
if (type & VDE_DCM) {
dcm_info("[%s][VDE_DCM ]=0x%08x,subsys_is_on(SYS_VDE)=%d\n", __func__,VDE_DCM,subsys_is_on(SYS_VDE));
if (subsys_is_on(SYS_VDE)) {
dcm_clrl (VDEC_DCM_CON , 0x00000001); //0xF6000018,
dcm_setl (SMI_LARB1_CON_SET , 0x00000010); //0xF6010014,set bit4=1,
dcm_sta |= VDE_DCM;
}
}
if (type & MJC_DCM) { //improve video record resloution
if (subsys_is_on(SYS_MJC)) {
dcm_writel (MJC_HW_DCM_DIS , 0x00000000); //0x17000010,
dcm_writel (MJC_HW_DCM_DIS_SET , 0x00000000); //0x17000014,
dcm_writel (MJC_HW_DCM_DIS_CLR , 0x00000000); //0x17000018,
dcm_setl (SMI_LARB4_CON_SET , 0x00000010); //0x17002014//set bit0=1,
dcm_sta |= MJC_DCM;
}
}
mutex_unlock(&dcm_lock);
#endif
}
void dcm_dump_regs(unsigned int type)
{
//volatile unsigned int dcm_cfg;
mutex_lock(&dcm_lock);
if (type & CPU_DCM) {
volatile unsigned int mcf_biu_con, ca7_misc_config;
mcf_biu_con = dcm_readl(MCU_BIU_CON);
ca7_misc_config = dcm_readl(CA7_MISC_CONFIG);
dcm_info("[CPU_DCM]MCU_BIU_CON(0x%08x), CA7_MISC_CONFIG(0x%08x)\n", mcf_biu_con, ca7_misc_config);
}
if (type & TOPCKGEN_DCM) {
volatile unsigned int dcm_cfg,dcm_scp_cfg_cfg0,dcm_scp_cfg_cfg1;
dcm_cfg = dcm_readl(DCM_CFG);
dcm_scp_cfg_cfg0 = dcm_readl(CLK_SCP_CFG_0);
dcm_scp_cfg_cfg1 = dcm_readl(CLK_SCP_CFG_1);
dcm_info("[IFR_DCM]DCM_CFG(0x%08x)\n", dcm_cfg);
dcm_info("[IFR_DCM]CLK_SCP_CFG_0(0x%08x)\n", dcm_scp_cfg_cfg0);
dcm_info("[IFR_DCM]CLK_SCP_CFG_1(0x%08x)\n", dcm_scp_cfg_cfg1);
}
if (type & IFR_DCM) {
volatile unsigned int fsel, dbc, ctl;
volatile unsigned int dramc;
fsel = dcm_readl(INFRA_DCMFSEL);
dbc = dcm_readl(INFRA_DCMDBC);
ctl = dcm_readl(INFRA_DCMCTL);
dramc = dcm_readl(DRAMC_PD_CTRL);
dcm_info("[IFR_DCM]FSEL(0x%08x), DBC(0x%08x), CTL(0x%08x)\n",fsel, dbc, ctl);
dcm_info("[IFR_DCM]DRAMC_PD_CTRL(0x%08x)\n", dramc);
}
if (type & PER_DCM) {
volatile unsigned int top_ckdiv1, top_dcmctl, top_dcmdbc, infra_dcmctl, infra_dcmdbc, infra_dcmsel, infra_pd_Ctrl;
top_ckdiv1 = dcm_readl(TOP_CKDIV1);
top_dcmctl = dcm_readl(TOP_DCMCTL);
top_dcmdbc = dcm_readl(TOP_DCMDBC);
infra_dcmctl = dcm_readl(INFRA_DCMCTL);
infra_dcmdbc = dcm_readl(INFRA_DCMDBC);
infra_dcmsel = dcm_readl(INFRA_DCMFSEL);
infra_pd_Ctrl = dcm_readl(DRAMC_PD_CTRL);
dcm_info("[PER_DCM]TOP_CKDIV1(0x%08x), TOP_DCMCTL(0x%08x), TOP_DCMDBC(0x%08x), INFRA_DCMCTL(0x%08x), INFRA_DCMDBC(0x%08x), INFRA_DCMFSEL(0x%08x), DRAMC_PD_CTRL(0x%08x)\n",
top_ckdiv1, top_dcmctl, top_dcmdbc,infra_dcmctl,infra_dcmdbc,infra_dcmsel,infra_pd_Ctrl);
}
if (type & SMI_DCM) {
volatile unsigned int smi_dcm_control,smi_common_ao_smi_con,mmu_dcm;
volatile unsigned int smi_common_ao_smi_con_set,smi_common_ao_smi_con_clr;
smi_dcm_control = dcm_readl(SMI_DCM_CONTROL);
smi_common_ao_smi_con = dcm_readl(SMI_COMMON_AO_SMI_CON);
smi_common_ao_smi_con_set = dcm_readl(SMI_COMMON_AO_SMI_CON_SET);
smi_common_ao_smi_con_clr = dcm_readl(SMI_COMMON_AO_SMI_CON_CLR);
mmu_dcm = dcm_readl(MMU_DCM);
dcm_info("[SMI_DCM]SMI_DCM_CONTROL(0x%08x), SMI_COMMON_AO_SMI_CON(0x%08x), MMU_DCM(0x%08x)\n" ,
smi_dcm_control, smi_common_ao_smi_con,mmu_dcm);
dcm_info("[SMI_DCM]SMI_COMMON_AO_SMI_CON_SET(0x%08x)\n",smi_common_ao_smi_con_set);
dcm_info("[SMI_DCM]SMI_COMMON_AO_SMI_CON_CLR(0x%08x)\n",smi_common_ao_smi_con_clr);
}
if (type & MFG_DCM) {
if (subsys_is_on(SYS_MFG)) {
volatile unsigned int mfg0;
mfg0 = dcm_readl(MFG_DCM_CON_0);
dcm_info("[MFG_DCM]MFG_DCM_CON_0(0x%08x)\n",mfg0);
} else {
dcm_info("[MFG_DCM]subsy MFG is off\n");
}
}
if (type & DIS_DCM) {
if (subsys_is_on(SYS_DIS)) {
volatile unsigned int dis0, dis_set0, dis_clr0,dis1, dis_set1, dis_clr1;
volatile unsigned int smilarb0_dcm_sta,smilarb0_dcm_con,smilarb0_dcm_set;
dis0 = dcm_readl(DISP_HW_DCM_DIS0);
dis_set0 = dcm_readl(DISP_HW_DCM_DIS_SET0);
dis_clr0 = dcm_readl(DISP_HW_DCM_DIS_CLR0);
dis1 = dcm_readl(DISP_HW_DCM_DIS1);
dis_set1 = dcm_readl(DISP_HW_DCM_DIS_SET1);
dis_clr1 = dcm_readl(DISP_HW_DCM_DIS_CLR1);
smilarb0_dcm_sta = dcm_readl(SMILARB0_DCM_STA);
smilarb0_dcm_con = dcm_readl(SMILARB0_DCM_CON);
smilarb0_dcm_set = dcm_readl(SMILARB0_DCM_SET);
dcm_info("[DIS_DCM]DISP_HW_DCM_DIS_SET0(0x%08x), DISP_HW_DCM_DIS_CLR0(0x%08x), DISP_HW_DCM_DIS_CLR0(0x%08x)\n",
dis0, dis_set0,dis_clr0);
dcm_info("[DIS_DCM]DISP_HW_DCM_DIS_SET1(0x%08x), DISP_HW_DCM_DIS_CLR1(0x%08x), DISP_HW_DCM_DIS_CLR1(0x%08x)\n",
dis1, dis_set1,dis_clr1);
dcm_info("[DIS_DCM]SMILARB0_DCM_STA(0x%08x),SMILARB0_DCM_CON(0x%08x),SMILARB0_DCM_SET(0x%08x)\n",
smilarb0_dcm_sta,smilarb0_dcm_con,smilarb0_dcm_set);
} else {
dcm_info("[DIS_DCM]subsys DIS is off\n");
}
}
if (type & ISP_DCM) {
if (subsys_is_on(SYS_ISP)) {
volatile unsigned int raw, rgb, yuv, cdp,dma;
volatile unsigned int jpgenc,venc_dcm,venc_cg,smilarb2_dcm_sta,smilarb2_dcm_com;
raw = dcm_readl(CAM_CTL_RAW_DCM);
rgb = dcm_readl(CAM_CTL_RGB_DCM);
yuv = dcm_readl(CAM_CTL_YUV_DCM);
cdp = dcm_readl(CAM_CTL_CDP_DCM);
dma = dcm_readl(CAM_CTL_DMA_DCM);
jpgenc = dcm_readl(JPGENC_DCM_CTRL);
venc_dcm = dcm_readl(VENC_CLK_DCM_CTRL);
venc_cg = dcm_readl(VENC_CLK_CG_CTRL);
smilarb2_dcm_sta = dcm_readl(SMILARB2_DCM_STA);
smilarb2_dcm_com = dcm_readl(SMILARB2_DCM_CON);
dcm_info("[ISP_DCM]CAM_CTL_RAW_DCM(0x%08x), CAM_CTL_RGB_DCM(0x%08x)\n",
raw, rgb);
dcm_info("[ISP_DCM]CAM_CTL_YUV_DCM(0x%08x), CAM_CTL_CDP_DCM(0x%08x)\n",
yuv, cdp);
dcm_info("[ISP_DCM] JPGENC_DCM_CTRL(0x%08x),VENC_CLK_CG_CTRL(0x%08x)\n",
jpgenc,venc_cg);
dcm_info("[ISP_DCM]SMILARB2_DCM_STA(0x%08x)\n", smilarb2_dcm_sta);
dcm_info("[ISP_DCM]SMILARB2_DCM_CON(0x%08x)\n", smilarb2_dcm_com);
} else {
dcm_info("[ISP_DCM]subsys ISP is off\n");
}
}
if (type & VDE_DCM) {
if (subsys_is_on(SYS_VDE)) {
volatile unsigned int vdec, smilarb1_dcm_sta,smilarb1_dcm_com,smilarb1_dcm_set;
vdec = dcm_readl(VDEC_DCM_CON);
smilarb1_dcm_sta = dcm_readl(SMILARB1_DCM_STA);
smilarb1_dcm_com = dcm_readl(SMILARB1_DCM_CON);
smilarb1_dcm_set = dcm_readl(SMILARB1_DCM_SET);
dcm_info("[VDE_DCM]VDEC_DCM_CON(0x%08x), SMILARB1_DCM_STA(0x%08x), SMILARB1_DCM_CON(0x%08x), SMILARB1_DCM_SET(0x%08x)\n",
vdec, smilarb1_dcm_sta,smilarb1_dcm_com,smilarb1_dcm_set);
} else {
dcm_info("[VDE_DCM]subsys VDE is off\n");
}
}
mutex_unlock(&dcm_lock);
}
void dcm_enable(unsigned int type)
{
volatile unsigned int temp;
dcm_info("[%s]type:0x%08x\n", __func__, type);
mutex_lock(&dcm_lock);
if (type & CPU_DCM) {
dcm_info("[%s][CPU_DCM ]=0x%08x\n", __func__,CPU_DCM);
dcm_setl(MCU_BIU_CON, 0x1 << 12);
dcm_setl(CA7_MISC_CONFIG, 0x1 << 9);
dcm_sta |= CPU_DCM;
}
if (type & TOPCKGEN_DCM) {
dcm_info("[%s][TOPCKGEN_DCM]=0x%08x\n", __func__,TOPCKGEN_DCM);
#ifdef DCM_ENABLE_DCM_CFG //AXI bus dcm, don't need to set by KL Tong
//default value are all 0,use default value
dcm_writel(DCM_CFG, 0xFFFFFF7F);//set bit0~bit4=0,bit7=0,bit8~bit14=0,bit15=0????
#endif
dcm_setl(CLK_SCP_CFG_0, 0x3FF);//set bit0~bit9=1,SCP control register 1
dcm_setl(CLK_SCP_CFG_1, ((0x1 << 4) | 0x1));//set bit0=1 and bit4=1,SCP control register 1
dcm_sta |= TOPCKGEN_DCM;
}
//Infrasys_dcm
if (type & IFR_DCM) {
dcm_info("[%s][IFR_DCM ]=0x%08x\n", __func__,IFR_DCM);
dcm_clrl(TOP_CKDIV1, 0x0000001f);//5'h0,00xxx: 1/1
dcm_setl(TOP_DCMCTL, 0x00000007);//set bit0~bit2=1
dcm_setl(TOP_DCMDBC, 0x00000001);//set bit0=1, force to 26M
dcm_setl(INFRA_DCMCTL, 0x00000303);//set bit0,bit1,bit8,bit9=1,DCM debouncing counter=0
dcm_setl(INFRA_DCMDBC, 0x00000300);//set bit8,bit9=1 first
dcm_clrl(INFRA_DCMDBC, 0x0000007F);//then clear b0~b6
#if 0// divided most, save power,
dcm_writel(INFRA_DCMFSEL, 0xFFE0F0F8);//clear bit0~bit2,clear bit8~bit11,clear bit16~bit20
#else//// divided by 1
dcm_writel(INFRA_DCMFSEL, 0xFFF0F0F8);//clear bit0~bit2,clear bit8~bit11,set bit20=1
#endif
dcm_setl(DRAMC_PD_CTRL, 0x3 << 24);////set bit24,bit25=1
dcm_sta |= IFR_DCM;
}
if (type & PER_DCM) {
dcm_info("[%s][PER_DCM ]=0x%08x\n", __func__,PER_DCM);
dcm_clrl(PERI_GLOBALCON_DCMCTL, 0x00001F00);//clear bit8~bit12=0
dcm_setl(PERI_GLOBALCON_DCMCTL, 0x000000F3);//set bit0,bit1,bit4~bit7=1
dcm_setl(PERI_GLOBALCON_DCMDBC, 0x1<<7);//set bit7=1
dcm_clrl(PERI_GLOBALCON_DCMDBC, 0x0000007F);//clear bit0~bit6=0
dcm_clrl(PERI_GLOBALCON_DCMFSEL,0x00000007);//clear bit0~bit2
dcm_clrl(PERI_GLOBALCON_DCMFSEL,0x00000F00);//clear bit8~bit11
dcm_clrl(PERI_GLOBALCON_DCMFSEL,0x001F0000);//clear bit16~bit20
//<<<<<<<<need check module>>>>>>>>>>
//MSDC module
dcm_clrl(MSDC0_IP_DCM, 0xFF800000);//clear bit23~bit31=0
dcm_clrl(MSDC1_IP_DCM, 0xFF800000);//clear bit23~bit31=0
dcm_clrl(MSDC2_IP_DCM, 0xFF800000);//clear bit23~bit31=0
//USB
dcm_clrl(PERI_USB0_DCM, 0x00070000);//clear bit16~bit18=0
//PMIC
dcm_setl(PMIC_WRAP_DCM_EN, 0x1);//set bit0=1
//I2C
dcm_setl(I2C0_I2CREG_HW_CG_EN, 0x1);//set bit0=1
dcm_setl(I2C1_I2CREG_HW_CG_EN, 0x1);//set bit0=1
dcm_setl(I2C2_I2CREG_HW_CG_EN, 0x1);//set bit0=1
dcm_sta |= PER_DCM;
}
if (type & SMI_DCM) {
dcm_info("[%s][SMI_DCM ]=0x%08x\n", __func__,SMI_DCM);
//smi_common
dcm_writel(SMI_DCM_CONTROL, 0x1);//set bit 0=1
//RO
dcm_readl(SMI_COMMON_AO_SMI_CON);
dcm_setl(SMI_COMMON_AO_SMI_CON_SET, 0x1 << 2);
//NA
dcm_readl(SMI_COMMON_AO_SMI_CON_CLR);
//m4u_dcm
dcm_setl(MMU_DCM, 0x1);//set bit0=1
dcm_sta |= SMI_DCM;
}
if (type & MFG_DCM) {
dcm_info("[%s][MFG_DCM ]=0x%08x,subsys_is_on(SYS_MFG)=%d\n", __func__,MFG_DCM,subsys_is_on(SYS_MFG));
if (subsys_is_on(SYS_MFG)) {
temp = dcm_readl(MFG_DCM_CON_0);
temp &= 0xFFFE0000;//set B[0:6]=0111111,B[8:13]=0,,B[14]=1,,B[15]=1,,B[16]=0
temp |= 0x0000C03F;
dcm_writel(MFG_DCM_CON_0, temp);
dcm_sta |= MFG_DCM;
}
}
if (type & DIS_DCM) {
dcm_info("[%s][DIS_DCM ]=0x%08x,subsys_is_on(SYS_DIS)=%d\n", __func__,DIS_DCM,subsys_is_on(SYS_DIS));
if (subsys_is_on(SYS_DIS)) {
dcm_writel(DISP_HW_DCM_DIS0, 0x0);
dcm_writel(DISP_HW_DCM_DIS_SET0, 0x0);
dcm_writel(DISP_HW_DCM_DIS_CLR0, 0xFFFFFFFF);
dcm_writel(DISP_HW_DCM_DIS1, 0x0);
dcm_writel(DISP_HW_DCM_DIS_SET1, 0x0);
dcm_writel(DISP_HW_DCM_DIS_CLR1, 0xFFFFFFFF);
//LARB0 „³ DISP, MDP
//RO,bootup set once status = 1'b0,DCM off setting=N/A
dcm_readl(SMILARB0_DCM_STA);
//RO,bootup set once status = 1'b1,DCM off setting=1'b0
dcm_readl(SMILARB0_DCM_CON);
dcm_setl(SMILARB0_DCM_SET, 0x1<<15);//set bit15=1
//N/A
dcm_readl(SMILARB0_DCM_CON);
dcm_sta |= DIS_DCM;
}
}
if (type & ISP_DCM) {
dcm_info("[%s][ISP_DCM ]=0x%08x,subsys_is_on(SYS_ISP)=%d\n", __func__,ISP_DCM,subsys_is_on(SYS_ISP));
if (subsys_is_on(SYS_ISP)) {
dcm_writel(CAM_CTL_RAW_DCM, 0xFFFF8000);//set bit0~bit14=0
dcm_writel(CAM_CTL_RGB_DCM, 0xFFFFFE00);//set bit0~bit8=0
dcm_writel(CAM_CTL_YUV_DCM, 0xFFFFFFF0);//set bit0~bit3=0
dcm_writel(CAM_CTL_CDP_DCM, 0xFFFFFE00);//set bit0~bit8=0
dcm_writel(CAM_CTL_DMA_DCM, 0xFFFFFFC0);//set bit0~bit5=0
dcm_clrl(JPGENC_DCM_CTRL, 0x1);//clear bit0=0
//dcm_writel(VENC_CE, 0x1);//no need to set
dcm_setl(VENC_CLK_DCM_CTRL, 0x1);//ok
dcm_writel(VENC_CLK_CG_CTRL, 0xFFFFFFFF);
//dcm_writel(VENC_MP4_DCM_CTRL, 0x0);
//dcm_writel(SMILARB0_DCM_SET, 0x3 << 15);
//LARB2 „³ ISP,VENC
//RO,bootup set once status = 1'b0,DCM off setting=N/A
dcm_readl(SMILARB2_DCM_STA);
//RO,bootup set once status = 1'b1,DCM off setting=1'b0
dcm_readl(SMILARB2_DCM_CON);
dcm_setl(SMILARB2_DCM_SET, 0x1<<15);//set bit15=1
//N/A
dcm_readl(SMILARB2_DCM_CON);
dcm_sta |= ISP_DCM;
}
}
if (type & VDE_DCM) {
dcm_info("[%s][VDE_DCM ]=0x%08x,subsys_is_on(SYS_VDE)=%d\n", __func__,VDE_DCM,subsys_is_on(SYS_VDE));
if (subsys_is_on(SYS_VDE)) {
dcm_clrl(VDEC_DCM_CON, 0x1);//clear bit0
//LARB1 „³ VDEC
//RO,bootup set once status = 1'b0,DCM off setting=N/A
dcm_readl(SMILARB1_DCM_STA);
//RO,bootup set once status = 1'b1,DCM off setting=1'b0
dcm_readl(SMILARB1_DCM_CON);
dcm_setl(SMILARB1_DCM_SET, 0x1<<15);//set bit15=1
//N/A
dcm_readl(SMILARB1_DCM_SET);
dcm_sta |= VDE_DCM;
}
}
mutex_unlock(&dcm_lock);
}
void dcm_dump_regs(unsigned int type)
{
volatile unsigned int dcm_cfg;
mutex_lock(&dcm_lock);
dcm_cfg = dcm_readl(DCM_CFG);
dcm_info("[BUS_DCM]DCM_CFG(0x%08x)\n", dcm_cfg);
if (type & CPU_DCM) {
volatile unsigned int fsel, dbc, ctl;
fsel = dcm_readl(TOP_CA7DCMFSEL);
dbc = dcm_readl(TOP_DCMDBC);
ctl = dcm_readl(TOP_DCMCTL);
dcm_info("[CPU_DCM]FSEL(0x%08x), DBC(0x%08x), CTL(0x%08x)\n",
fsel, dbc, ctl);
}
if (type & IFR_DCM) {
volatile unsigned int fsel, dbc, ctl;
volatile unsigned int dramc;
fsel = dcm_readl(INFRA_DCMFSEL);
dbc = dcm_readl(INFRA_DCMDBC);
ctl = dcm_readl(INFRA_DCMCTL);
dramc = dcm_readl(DRAMC_PD_CTRL);
dcm_info("[IFR_DCM]FSEL(0x%08x), DBC(0x%08x), CTL(0x%08x)\n",
fsel, dbc, ctl);
dcm_info("[IFR_DCM]DRAMC_PD_CTRL(0x%08x)\n", dramc);
}
if (type & PER_DCM) {
volatile unsigned int fsel, dbc, ctl;
fsel = dcm_readl(PERI_GCON_DCMFSEL);
dbc = dcm_readl(PERI_GCON_DCMDBC);
ctl = dcm_readl(PERI_GCON_DCMCTL);
dcm_info("[PER_DCM]FSEL(0x%08x), DBC(0x%08x), CTL(0x%08x)\n",
fsel, dbc, ctl);
}
if (type & SMI_DCM) {
volatile unsigned int smi_com_dcm, smi_sec_dcm, m4u_dcm;
smi_com_dcm = dcm_readl(SMI_COMMON_DCM);
smi_sec_dcm = dcm_readl(SMI_SECURE_DCMCON);
m4u_dcm = dcm_readl(M4U_DCM);
dcm_info("[SMI_DCM]SMI_COMMON_DCM(0x%08x), SMI_SECURE_DCM(0x%08x)\n" ,
smi_com_dcm, smi_sec_dcm);
dcm_info("[SMI_DCM]M4U_DCM(0x%08x)\n", m4u_dcm);
}
if (type & MFG_DCM) {
if (subsys_is_on(SYS_MFG)) {
volatile unsigned int mfg0, mfg1;
mfg0 = dcm_readl(MFG_DCM_CON0);
mfg1 = dcm_readl(MFG_DCM_CON0);
dcm_info("[MFG_DCM]MFG_DCM_CON0(0x%08x), MFG_DCM_CON1(0x%08x)\n",
mfg0, mfg1);
} else {
dcm_info("[MFG_DCM]subsy MFG is off\n");
}
}
if (type & DIS_DCM) {
if (subsys_is_on(SYS_DIS)) {
volatile unsigned int dis0, dis1, larb2;
dis0 = dcm_readl(DISP_HW_DCM_DIS0);
dis1 = dcm_readl(DISP_HW_DCM_DIS1);
larb2 = dcm_readl(SMILARB2_DCM_CON);
dcm_info("[DIS_DCM]DISP_HW_DCM_DIS0(0x%08x), DISP_HW_DCM_DIS1(0x%08x)\n",
dis0, dis1);
dcm_info("[DIS_DCM]SMILARB2_DCM_CON(0x%08x)\n", larb2);
} else {
dcm_info("[DIS_DCM]subsys DIS is off\n");
}
}
if (type & ISP_DCM) {
if (subsys_is_on(SYS_ISP)) {
volatile unsigned int raw, rgb, yuv, cdp;
volatile unsigned int jpgdec, jpgenc, isp_com, larb3, larb4;
raw = dcm_readl(CAM_CTL_RAW_DCM);
rgb = dcm_readl(CAM_CTL_RGB_DCM);
yuv = dcm_readl(CAM_CTL_YUV_DCM);
cdp = dcm_readl(CAM_CTL_CDP_DCM);
jpgdec = dcm_readl(JPGDEC_DCM_CTRL);
jpgenc = dcm_readl(JPGENC_DCM_CTRL);
isp_com = dcm_readl(SMI_ISP_COMMON_DCMCON);
larb3 = dcm_readl(SMILARB3_DCM_CON);
larb4 = dcm_readl(SMILARB4_DCM_CON);
dcm_info("[ISP_DCM]CAM_CTL_RAW_DCM(0x%08x), CAM_CTL_RGB_DCM(0x%08x)\n",
raw, rgb);
dcm_info("[ISP_DCM]CAM_CTL_YUV_DCM(0x%08x), CAM_CTL_CDP_DCM(0x%08x)\n",
yuv, cdp);
dcm_info("[ISP_DCM]JPGDEC_DCM_CTRL(0x%08x), JPGENC_DCM_CTRL(0x%08x)\n",
jpgdec, jpgenc);
dcm_info("[ISP_DCM]SMI_ISP_COMMON_DCMCON(0x%08x)\n", isp_com);
dcm_info("[ISP_DCM]SMILARB3_DCM_CON(0x%08x), SMILARB4_DCM_CON(0x%08x)\n",
larb3, larb4);
} else {
dcm_info("[ISP_DCM]subsys ISP is off\n");
}
}
if (type & VDE_DCM) {
if (subsys_is_on(SYS_VDE)) {
volatile unsigned int vdec, larb1;
vdec = dcm_readl(VDEC_DCM_CON);
larb1 = dcm_readl(SMILARB1_DCM_CON);
dcm_info("[VDE_DCM]VDEC_DCM_CON(0x%08x), SMILARB1_DCM_CON(0x%08x)\n",
vdec, larb1);
} else {
dcm_info("[VDE_DCM]subsys VDE is off\n");
}
}
if (type & VEN_DCM) {
if (subsys_is_on(SYS_VEN)) {
volatile unsigned int dcm_ctl, cg_ctl, mp4_dcm, larb0;
dcm_writel(VENC_CE, 0x1);
dcm_ctl = dcm_readl(VENC_CLK_DCM_CTRL);
cg_ctl = dcm_readl(VENC_CLK_CG_CTRL);
mp4_dcm = dcm_readl(VENC_MP4_DCM_CTRL);
larb0 = dcm_readl(SMILARB0_DCM_CON);
dcm_info("[VEN_DCM]VENC_CE=0x%08x", dcm_readl(VENC_CE));
dcm_info("[VEN_DCM]VENC_CLK_DCM_CTRL(0x%08x), VENC_CLK_CG_CTRL(0x%08x)\n",
dcm_ctl, cg_ctl);
dcm_info("[VEN_DCM]VENC_MP4_DCM_CTRL(0x%08x), SMILARB0_DCM_CON(0x%08x)\n",
mp4_dcm, larb0);
} else {
dcm_info("[VEN_DCM]subsys VEN is off\n");
}
}
mutex_unlock(&dcm_lock);
}
void dcm_disable(unsigned int type)
{
dcm_info("[%s]type:0x%08x\n", __func__, type);
mutex_lock(&dcm_lock);
//dcm_sta &= ~(type & ALL_DCM);
if (type & CPU_DCM) {
dcm_clrl(TOP_DCMCTL, 0x3 << 1);
dcm_sta &= ~CPU_DCM;
}
#if 0
if (type & BUS_DCM) {
//1. AXI bus dcm
dcm_clrl(DCM_CFG, 0x1 << 7);
}
#endif
if (type & IFR_DCM) {
dcm_clrl(INFRA_DCMCTL, 0x103);
dcm_clrl(DRAMC_PD_CTRL, 0x1 << 25);
dcm_sta &= ~IFR_DCM;
}
if (type & PER_DCM) {
dcm_writel(PERI_GCON_DCMCTL, 0xF2);
dcm_sta &= ~PER_DCM;
}
if (type & SMI_DCM) {
//smi_common
dcm_writel(SMI_COMMON_DCM, 0x0);
dcm_writel(SMI_SECURE_DCMCLR, 0x1 << 2);
//m4u_dcm
dcm_writel(M4U_DCM, 0x0);
dcm_sta &= ~SMI_DCM;
}
if (type & MFG_DCM) {
if (subsys_is_on(SYS_MFG)) {
dcm_clrl(MFG_DCM_CON0, 0x80008000);
dcm_clrl(MFG_DCM_CON1, 0x8000);
dcm_sta &= ~MFG_DCM;
}
}
if (type & DIS_DCM) {
if (subsys_is_on(SYS_DIS)) {
dcm_writel(DISP_HW_DCM_DIS_SET0, 0xFFFFFF);
dcm_writel(DISP_HW_DCM_DIS_SET1, 0x7);
dcm_writel(SMILARB2_DCM_CLR, 0x3 << 15);
dcm_sta &= ~DIS_DCM;
}
}
if (type & ISP_DCM) {
if (subsys_is_on(SYS_ISP)) {
dcm_writel(CAM_CTL_RAW_DCM, 0x7FFF);
dcm_writel(CAM_CTL_RGB_DCM, 0xFF);
dcm_writel(CAM_CTL_YUV_DCM, 0xF);
dcm_writel(CAM_CTL_CDP_DCM, 0x1FF);
dcm_writel(JPGDEC_DCM_CTRL, 0x1);
dcm_writel(JPGENC_DCM_CTRL, 0x1);
dcm_writel(SMI_ISP_COMMON_DCMCLR, 0x1 << 1);
dcm_writel(SMILARB3_DCM_CLR, 0x3 << 15);
dcm_writel(SMILARB4_DCM_CLR, 0x3 << 15);
dcm_sta &= ~ISP_DCM;
}
}
if (type & VDE_DCM) {
if (subsys_is_on(SYS_VDE)) {
dcm_writel(VDEC_DCM_CON, 0x1);
dcm_writel(SMILARB1_DCM_CLR, 0x3 << 15);
dcm_sta &= ~VDE_DCM;
}
}
if (type & VEN_DCM) {
if (subsys_is_on(SYS_VEN)) {
dcm_writel(VENC_CE, 0x1);
dcm_writel(VENC_CLK_DCM_CTRL, 0x0);
dcm_writel(VENC_CLK_CG_CTRL, 0x0);
dcm_writel(VENC_MP4_DCM_CTRL, 0x1);
dcm_writel(SMILARB0_DCM_CLR, 0x3 << 15);
dcm_sta &= ~VEN_DCM;
}
}
mutex_unlock(&dcm_lock);
}
void dcm_enable(unsigned int type)
{
dcm_info("[%s]type:0x%08x\n", __func__, type);
mutex_lock(&dcm_lock);
//dcm_sta |= type & ALL_DCM;
if (type & CPU_DCM) {
dcm_writel(TOP_CA7DCMFSEL, 0x7000000);
dcm_writel(TOP_DCMDBC, 0x1); // force to 26M
dcm_setl(TOP_DCMCTL, 0x3 << 1);
dcm_sta |= CPU_DCM;
}
#if 0
if (type & BUS_DCM) {
//1. AXI bus dcm
dcm_setl(DCM_CFG, 0x1 << 7);
dcm_sta |= BUS_DCM;
}
#endif
if (type & IFR_DCM) {
//dcm_writel(INFRA_DCMFSEL, 0x0);// divided most
dcm_writel(INFRA_DCMFSEL, 0x001F0000);// divided by 1
dcm_writel(INFRA_DCMDBC, 0x0000037F);
dcm_setl(INFRA_DCMCTL, 0x103);
dcm_setl(DRAMC_PD_CTRL, 0x3 << 24);
dcm_sta |= IFR_DCM;
}
if (type & PER_DCM) {
dcm_writel(PERI_GCON_DCMFSEL, 0x0);
dcm_writel(PERI_GCON_DCMCTL, 0xF3);
dcm_sta |= PER_DCM;
}
if (type & SMI_DCM) {
//smi_common
dcm_writel(SMI_COMMON_DCM, 0x1 << 0);
dcm_writel(SMI_SECURE_DCMSET, 0x1 << 2);
//m4u_dcm
dcm_writel(M4U_DCM, 0x1);
dcm_sta |= SMI_DCM;
}
if (type & MFG_DCM) {
if (subsys_is_on(SYS_MFG)) {
//dcm_setl(MFG_DCM_CON0, 0x80008000);
//dcm_setl(MFG_DCM_CON1, 0x8000);
dcm_writel(MFG_DCM_CON0, 0xC03FC03F);
dcm_writel(MFG_DCM_CON1, 0xC03F);
dcm_sta |= MFG_DCM;
}
}
if (type & DIS_DCM) {
if (subsys_is_on(SYS_DIS)) {
dcm_writel(DISP_HW_DCM_DIS_CLR0, 0xFFFFFF);
dcm_writel(DISP_HW_DCM_DIS_CLR1, 0x7);
dcm_writel(SMILARB2_DCM_SET, 0x3 << 15);
dcm_sta |= DIS_DCM;
}
}
if (type & ISP_DCM) {
if (subsys_is_on(SYS_ISP)) {
dcm_writel(CAM_CTL_RAW_DCM, 0x0);
dcm_writel(CAM_CTL_RGB_DCM, 0x0);
dcm_writel(CAM_CTL_YUV_DCM, 0x0);
dcm_writel(CAM_CTL_CDP_DCM, 0x0);
dcm_writel(JPGDEC_DCM_CTRL, 0x0);
dcm_writel(JPGENC_DCM_CTRL, 0x0);
dcm_writel(SMI_ISP_COMMON_DCMSET, 0x1 << 1);
dcm_writel(SMILARB3_DCM_SET, 0x3 << 15);
dcm_writel(SMILARB4_DCM_SET, 0x3 << 15);
dcm_sta |= ISP_DCM;
}
}
if (type & VDE_DCM) {
if (subsys_is_on(SYS_VDE)) {
dcm_writel(VDEC_DCM_CON, 0x0);
dcm_writel(SMILARB1_DCM_SET, 0x3 << 15);
dcm_sta |= VDE_DCM;
}
}
if (type & VEN_DCM) {
if (subsys_is_on(SYS_VEN)) {
dcm_writel(VENC_CE, 0x1);
dcm_writel(VENC_CLK_DCM_CTRL, 0x1);
dcm_writel(VENC_CLK_CG_CTRL, 0xFFFFFFFF);
dcm_writel(VENC_MP4_DCM_CTRL, 0x0);
dcm_writel(SMILARB0_DCM_SET, 0x3 << 15);
dcm_sta |= VEN_DCM;
}
}
mutex_unlock(&dcm_lock);
}
static void Golden_Setting_Compare_PLL(void)
{
if (pll_is_on(MSDCPLL)) {
clc_notice("MSDCPLL: %s\n", pll_is_on(MSDCPLL) ? "on" : "off");
}
if (pll_is_on(TVDPLL)) {
clc_notice("TVDPLL: %s\n", pll_is_on(TVDPLL) ? "on" : "off");
}
if (pll_is_on(LVDSPLL)) {
clc_notice("LVDSPLL: %s\n", pll_is_on(LVDSPLL) ? "on" : "off");
}
if (pll_is_on(ISPPLL)) {
clc_notice("ISPPLL: %s\n", pll_is_on(ISPPLL) ? "on" : "off");
}
if (subsys_is_on(SYS_MD1)) {
clc_notice("SYS_MD1: %s\n", subsys_is_on(SYS_MD1) ? "on" : "off");
}
if (subsys_is_on(SYS_MD2)) {
clc_notice("SYS_MD2: %s\n", subsys_is_on(SYS_MD2) ? "on" : "off");
}
if (subsys_is_on(SYS_DIS)) {
clc_notice("SYS_DIS: %s\n", subsys_is_on(SYS_DIS) ? "on" : "off");
}
if (subsys_is_on(SYS_MFG)) {
clc_notice("SYS_MFG: %s\n", subsys_is_on(SYS_MFG) ? "on" : "off");
}
if (subsys_is_on(SYS_ISP)) {
clc_notice("SYS_ISP: %s\n", subsys_is_on(SYS_ISP) ? "on" : "off");
}
if (subsys_is_on(SYS_VEN)) {
clc_notice("SYS_VEN: %s\n", subsys_is_on(SYS_VEN) ? "on" : "off");
}
if (subsys_is_on(SYS_VDE)) {
clc_notice("SYS_VDE: %s\n", subsys_is_on(SYS_VDE) ? "on" : "off");
}
}
