static void v202Nrf24Setup(rx_spi_protocol_e protocol) { NRF24L01_Initialize(BV(NRF24L01_00_CONFIG_EN_CRC) | BV(NRF24L01_00_CONFIG_CRCO)); // 2-bytes CRC NRF24L01_WriteReg(NRF24L01_01_EN_AA, 0x00); // No Auto Acknowledgment NRF24L01_WriteReg(NRF24L01_02_EN_RXADDR, BV(NRF24L01_02_EN_RXADDR_ERX_P0)); // Enable data pipe 0 NRF24L01_WriteReg(NRF24L01_03_SETUP_AW, NRF24L01_03_SETUP_AW_5BYTES); // 5-byte RX/TX address NRF24L01_WriteReg(NRF24L01_04_SETUP_RETR, 0xFF); // 4ms retransmit t/o, 15 tries if (protocol == RX_SPI_NRF24_V202_250K) { NRF24L01_WriteReg(NRF24L01_06_RF_SETUP, NRF24L01_06_RF_SETUP_RF_DR_250Kbps | NRF24L01_06_RF_SETUP_RF_PWR_n12dbm); } else { NRF24L01_WriteReg(NRF24L01_06_RF_SETUP, NRF24L01_06_RF_SETUP_RF_DR_1Mbps | NRF24L01_06_RF_SETUP_RF_PWR_n12dbm); } NRF24L01_WriteReg(NRF24L01_07_STATUS, BV(NRF24L01_07_STATUS_RX_DR) | BV(NRF24L01_07_STATUS_TX_DS) | BV(NRF24L01_07_STATUS_MAX_RT)); // Clear data ready, data sent, and retransmit NRF24L01_WriteReg(NRF24L01_11_RX_PW_P0, V2X2_PAYLOAD_SIZE); // bytes of data payload for pipe 0 NRF24L01_WriteReg(NRF24L01_17_FIFO_STATUS, 0x00); // Just in case, no real bits to write here #define RX_TX_ADDR_LEN 5 const uint8_t rx_tx_addr[RX_TX_ADDR_LEN] = {0x66, 0x88, 0x68, 0x68, 0x68}; NRF24L01_WriteRegisterMulti(NRF24L01_0A_RX_ADDR_P0, rx_tx_addr, RX_TX_ADDR_LEN); NRF24L01_WriteRegisterMulti(NRF24L01_10_TX_ADDR, rx_tx_addr, RX_TX_ADDR_LEN); NRF24L01_FlushTx(); NRF24L01_FlushRx(); rf_ch_num = 0; bind_phase = PHASE_NOT_BOUND; prepare_to_bind(); switch_channel(); NRF24L01_SetRxMode(); // enter receive mode to start listening for packets }
/* * Function : start_classifiy_spectral_scan * Description : start the classify spectral scan * Input params : pointer to ath_ssd_info_t * Return : void * */ void start_classifiy_spectral_scan(ath_ssd_info_t *pinfo) { pinfo->channel_index = 0; pinfo->dwell_interval = CHANNEL_CLASSIFY_DWELL_INTERVAL; switch_channel(pinfo); issue_start_spectral_cmd(); alarm(pinfo->dwell_interval); }
static rx_spi_received_e readrx(uint8_t *packet) { if (!(NRF24L01_ReadReg(NRF24L01_07_STATUS) & BV(NRF24L01_07_STATUS_RX_DR))) { uint32_t t = micros() - packet_timer; if (t > rx_timeout) { switch_channel(); packet_timer = micros(); } return RX_SPI_RECEIVED_NONE; } packet_timer = micros(); NRF24L01_WriteReg(NRF24L01_07_STATUS, BV(NRF24L01_07_STATUS_RX_DR)); // clear the RX_DR flag NRF24L01_ReadPayload(packet, V2X2_PAYLOAD_SIZE); NRF24L01_FlushRx(); switch_channel(); return decode_packet(packet); }
void initrx(void) { NRF24L01_Initialize(); reset_beken(); // 2-bytes CRC, radio off uint8_t config = BV(NRF24L01_00_EN_CRC) | BV(NRF24L01_00_CRCO) | BV(NRF24L01_00_PRIM_RX); NRF24L01_WriteReg(NRF24L01_00_CONFIG, config); NRF24L01_WriteReg(NRF24L01_01_EN_AA, 0x00); // No Auto Acknoledgement NRF24L01_WriteReg(NRF24L01_02_EN_RXADDR, 0x01); // Enable data pipe 0 NRF24L01_WriteReg(NRF24L01_03_SETUP_AW, 0x03); // 5-byte RX/TX address NRF24L01_WriteReg(NRF24L01_04_SETUP_RETR, 0xFF); // 4ms retransmit t/o, 15 tries // NRF24L01_WriteReg(NRF24L01_05_RF_CH, 0x08); // Channel 8 - bind //NRF24L01_SetBitrate(NRF24L01_BR_1M); // 1Mbps NRF24L01_SetBitrate(NRF24L01_BR_250K); //250k for longer range. NRF24L01_SetPower(TXPOWER_100mW); NRF24L01_WriteReg(NRF24L01_07_STATUS, 0x70); // Clear data ready, data sent, and retransmit NRF24L01_WriteReg(NRF24L01_11_RX_PW_P0, V2X2_PAYLOAD_SIZE); // bytes of data payload for pipe 0 NRF24L01_WriteReg(NRF24L01_17_FIFO_STATUS, 0x00); // Just in case, no real bits to write here uint8_t rx_tx_addr[] = {0x66, 0x88, 0x68, 0x68, 0x68}; // uint8_t rx_p1_addr[] = {0x88, 0x66, 0x86, 0x86, 0x86}; NRF24L01_WriteRegisterMulti(NRF24L01_0A_RX_ADDR_P0, rx_tx_addr, 5); // NRF24L01_WriteRegisterMulti(NRF24L01_0B_RX_ADDR_P1, rx_p1_addr, 5); NRF24L01_WriteRegisterMulti(NRF24L01_10_TX_ADDR, rx_tx_addr, 5); initialize_beken(); lib_timers_delaymilliseconds(50); NRF24L01_FlushTx(); NRF24L01_FlushRx(); rf_ch_num = 0; // Turn radio power on config |= BV(NRF24L01_00_PWR_UP); NRF24L01_WriteReg(NRF24L01_00_CONFIG, config); // delayMicroseconds(150); lib_timers_delaymilliseconds(1); // 6 times more than needed valid_packets = missed_packets = bad_packets = 0; if (usersettings.boundprotocol == PROTO_NONE) { bind_phase = PHASE_NOT_BOUND; prepare_to_bind(); } else { // Prepare to listen to bound protocol, if fails // try to bind bind_phase = PHASE_JUST_BOUND; set_bound(); } switch_channel(); }
static void * hop_thread(void * info) { const channel_hop_info * hopInfo = (const channel_hop_info *)info; int idx = 0; while (1) { const char * channel = hopInfo->channels[idx]; if (switch_channel(hopInfo->interface, channel)) { die("failed to hop channels."); } idx = (idx + 1) % hopInfo->count; sleep(hopInfo->hopDelay); } return NULL; }
void readrx(void) { int chan; uint16_t data[8]; if (!(NRF24L01_ReadReg(NRF24L01_07_STATUS) & BV(NRF24L01_07_RX_DR))) { uint32_t t = lib_timers_gettimermicroseconds(packet_timer); if (t > rx_timeout) { if (boundprotocol != PROTO_NONE) { if (++missed_packets > 500 && bind_phase == PHASE_JUST_BOUND) { valid_packets = missed_packets = bad_packets = 0; bind_phase = PHASE_LOST_BINDING; prepare_to_bind(); } } else switch_channel(); packet_timer = lib_timers_starttimer(); } return; } packet_timer = lib_timers_starttimer(); NRF24L01_WriteReg(NRF24L01_07_STATUS, BV(NRF24L01_07_RX_DR)); NRF24L01_ReadPayload(packet, V2X2_PAYLOAD_SIZE); NRF24L01_FlushRx(); switch_channel(); if (!decode_packet(packet, data)) return; for (chan = 0; chan < 8; ++chan) { // data = pwmRead(chan); // if (data < 750 || data > 2250) // data = 1500; // convert from 1000-2000 range to -1 to 1 fixedpointnum range and low pass filter to remove glitches lib_fp_lowpassfilter(&global.rxvalues[chan], ((fixedpointnum) data[chan] - 1500) * 131L, global.timesliver, FIXEDPOINTONEOVERONESIXTYITH, TIMESLIVEREXTRASHIFT); } // reset the failsafe timer global.failsafetimer = lib_timers_starttimer(); }
/* * Function : alarm_handler * Description : alarm signal handler, used to switch channel * Input params : pointer to ath_ssd_info_t * Return : void * */ void alarm_handler(ath_ssd_info_t *pinfo) { /* disable the timer */ alarm(0); /* stop any active spectral scan */ issue_stop_spectral_cmd(); /* print debug info */ if (IS_DBG_ENABLED()) { print_ssd_stats(pinfo); } /* switch to new channel */ switch_channel(pinfo); /* enable the timer handler */ alarm(pinfo->dwell_interval); /* start spectral scan */ issue_start_spectral_cmd(); }